279 lines
8.4 KiB
Plaintext
279 lines
8.4 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Example for flash declaration of NXP LPC8xx internal flash.
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;
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; @Description:
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; Script arguments:
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;
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; DO lpc8xx [PREPAREONLY]
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;
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; PREPAREONLY only declares flash but does not execute flash programming
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;
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; List of LPC8xx derivatives and their configuration:
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;
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; CPU-Type FlashSize RamSize
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; [kB] [kB]
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; ---------------------------------
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; LPC802M001JDH16 16. 2.
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; LPC802M001JDH20 16. 2.
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; LPC802M001JHI33 16. 2.
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; LPC802M011JDH20 16. 2.
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; LPC804M101JDH20 32. 4.
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; LPC804M101JDH24 32. 4.
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; LPC804M101JHI33 32. 4.
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; LPC804M111JDH24 32. 4.
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; LPC810M021FN8 4. 1.
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; LPC811M001FDH16 8. 2.
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; LPC812M101FD20 16. 4.
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; LPC812M101FDH16 16. 4.
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; LPC812M101FDH20 16. 4.
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; LPC822M101JHI33 16. 4.
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; LPC822M101JDH20 16. 4.
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; LPC824M201JHI33 32. 8.
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; LPC824M201JDH20 32. 8.
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; LPC832M101FDH20 16. 4.
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; LPC834M101FHI33 32. 4.
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; LPC844M201JBD48 64. 8.
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; LPC844M201JBD64 64. 8.
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; LPC844M201JHI33 64. 8.
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; LPC844M201JHI48 64. 8.
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; LPC845M301JBD48 64. 16.
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; LPC845M301JBD64 64. 16.
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; LPC845M301JHI33 64. 16.
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; LPC845M301JHI48 64. 16.
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;
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; Code Read Protection (CRP):
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;
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; CRP is invoked by programming a specific pattern in flash location
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; at 0x000002FC.
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;
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; Name Pattern Description
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; --------------------------------
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; NO_ISP 0x4E697370 Prevents sampling of pin PIO0_1 for entering ISP mode.
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; PIO0_1 is available for other uses.
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; CRP1 0x12345678 Access to chip via the SWD pins is disabled. This mode
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; allows partial flash update using the following ISP
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; commands and restrictions:
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; * Write to RAM command should not access RAM below
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; 0x10000300. Access to addresses below 0x10000200 is
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; disabled.
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; * Copy RAM to flash command can not write to Sector 0.
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; * Erase command can erase Sector 0 only when all
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; sectors are selected for erase.
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; * Compare command is disabled.
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; * Read Memory command is disabled.
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; This mode is useful when CRP is required and flash
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; field updates are needed but all sectors can not be
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; erased. Since compare command is disabled in case of
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; partial updates the secondary loader should implement
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; checksum mechanism to verify the integrity of the flash.
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; CRP2 0x87654321 Access to chip via the SWD pins is disabled. The
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; following ISP commands are disabled:
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; * Read Memory
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; * Write to RAM
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; * Go
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; * Copy RAM to flash
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; * Compare
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; When CRP2 is enabled the ISP erase command only allows
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; erasure of all user sectors.
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; CRP3 0x43218765 Access to chip via the SWD pins is disabled. ISP entry
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; by pulling PIO0_1 LOW is disabled if a valid user code
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; is present in flash sector 0.
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; This mode effectively disables ISP override using PIO0_1
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; pin. It is up to the user's application to provide a
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; flash update mechanism using IAP calls or call reinvoke
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; ISP command to enable flash update via UART.
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; CAUTION: If CRP3 is selected, no future factory testing
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; can be performed on the device.
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;
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; RAM used by IAP command handler:
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;
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; IAP commands, which results in a flash write/erase operation, use 32 bytes of
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; space in the top portion of the on-chip RAM for execution.
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;
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; HINTS:
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;
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; Flash clock has to match System Clock Frequency (CCLK).
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; FLASH.CLocK.AUTO can be used for automatic flash clock measurement.
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;
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; Boot flash cannot be programmed or erased with builtin flash
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; algorithm.
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;
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; Data has to be loaded to flash alignment to page boundaries.
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;
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; Vector table checksum generation is done by script, so that it
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; can be used or switched off, as needed.
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;
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; @Author: WRD
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; @Chip: LPC8*
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; --------------------------------------------------------------------------------
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; $Rev: 12049 $
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; $Id: lpc8xx.cmm 12049 2023-04-20 12:32:16Z bschroefel $
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LOCAL ¶meters ¶m_prepareonly
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ENTRY %LINE ¶meters
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¶m_prepareonly=(STRing.SCAN(STRing.UPpeR("¶meters"),"PREPAREONLY",0)!=-1)
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; --------------------------------------------------------------------------------
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; Start debugging
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IF SYStem.MODE()<5
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(
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SYStem.RESet
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IF !CPUIS(LPC8*)
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SYStem.CPU LPC8*
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IF !CABLE.TWOWIRE()
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(
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PRINT %ERROR "Serial Wire Debug (SWD) not supported by debug cable"
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ENDDO
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)
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SYStem.CONFIG.DEBUGPORTTYPE SWD
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SYStem.Option.EnReset OFF
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SYStem.Up
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)
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; --------------------------------------------------------------------------------
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; Flash declaration
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FLASH.RESet
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FLASH.CLocK.AUTO
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GOSUB FlashDeclaration
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; Flash script ends here if called with parameter PREPAREONLY
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IF ¶m_prepareonly
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ENDDO PREPAREDONE
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; --------------------------------------------------------------------------------
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; Flash programming example
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DIALOG.YESNO "Program flash memory?"
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LOCAL &progflash
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ENTRY &progflash
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IF &progflash
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(
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; Switch memory mapping to user flash mode, so that on-chip flash is
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; mapped to address 0x0--0x1ff. System Memory Remap register
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; SYSMEMREMAP:0..1 = 10b
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Data.Set 0x40048000 %Long 0x02
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; Example for download
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FLASH.ReProgram.ALL /Erase
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; 1. Download file
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Data.LOAD.auto *
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; 2. Checksum generation
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Data.SUM 0x0--0x1B /Long ;Calculate checksum of all (other) vectors
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Data.Set 0x1C %Long -Data.SUM() ;Write the 2's complement in reserved vector's spot
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; 3. Flash programming
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FLASH.ReProgram.off
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; Reset device and execute boot code until application start
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LOCAL &startAddress
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&startAddress=Data.Long(SD:0x04)&0xFFFFFFFE
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SYStem.Up
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Go.direct &startAddress
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WAIT 100.ms
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IF STATE.RUN()
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(
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Break.direct
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Data.List
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PRINT %ERROR "Boot code didn't branch to application start"
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ENDDO
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)
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)
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ENDDO
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; --------------------------------------------------------------------------------
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; Flash declaration depending on selected CPU
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FlashDeclaration:
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LOCAL &FlashSize
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LOCAL &FlashDriver
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LOCAL &RAMSize
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&FlashDriver="lpc800.bin"
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IF CPUIS(LPC802*)
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(
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&FlashSize=0x4000
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&RAMSize=0x800
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)
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ELSE IF CPUIS(LPC804*)
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(
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&FlashSize=0x8000
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&RAMSize=0x1000
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)
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ELSE IF CPUIS(LPC810*)
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(
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&FlashSize=0x1000
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&RAMSize=0x400
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)
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ELSE IF CPUIS(LPC811*)
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(
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&FlashSize=0x2000
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&RAMSize=0x800
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)
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ELSE IF CPUIS(LPC8?2*)
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(
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&FlashSize=0x4000
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&RAMSize=0x1000
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)
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ELSE IF CPUIS(LPC824*)
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(
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&FlashSize=0x8000
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&RAMSize=0x2000
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)
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ELSE IF CPUIS(LPC832*)
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(
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&FlashSize=0x4000
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&RAMSize=0x1000
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)
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ELSE IF CPUIS(LPC834*)
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(
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&FlashSize=0x8000
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&RAMSize=0x1000
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)
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ELSE IF CPUIS(LPC844*)
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(
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&FlashSize=0x10000
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&RAMSize=0x2000
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&FlashDriver="lpc84x.bin"
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)
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ELSE IF CPUIS(LPC845*)
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(
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&FlashSize=0x10000
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&RAMSize=0x4000
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&FlashDriver="lpc84x.bin"
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)
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ELSE
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(
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PRINT %ERROR "FLASH size of CPU type is unknown"
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ENDDO
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)
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FLASH.Create 1. 0x0--(&FlashSize-1) 0x400 TARGET Long
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IF &RAMSize>=0x1000
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(
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FLASH.TARGET 0x10000800 0x10000000 0x400 ~~/demo/arm/flash/long/&FlashDriver /STACKSIZE 0x200
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)
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ELSE IF &RAMSize>=0x0800
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(
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FLASH.TARGET 0x10000500 0x10000000 0x300 ~~/demo/arm/flash/long/&FlashDriver /STACKSIZE 0x120
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)
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ELSE IF &RAMSize>=0x0400
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(
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FLASH.TARGET 0x10000200 0x10000000 0x0C0 ~~/demo/arm/flash/long/lpc810.bin /STACKSIZE 0x120
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)
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ELSE
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(
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PRINT %ERROR "RAM size is not supported by the script"
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ENDDO
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)
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RETURN
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