364 lines
12 KiB
Plaintext
364 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: OSPI FLASH Program script for the j7vcl-evm (DRA821)
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; @Description:
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; The OSPI flash is connected to the OSPI_CS0 controller.
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; Supported OSPI flash memories:
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; - MT35XU512
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; - S28HS512
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;
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; SRAM:
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; OSPI(controller) Base: 0x47040000
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; OSPI memory mapped ADDRESS: 0x50000000
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;
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; Prerequisites: Switch Settings: CONFIG_SW[1] = OFF (SW3.1 on common board)
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;
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; @Chip: DRA821
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; @Board: J7VCL-EVM
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; @Author: CMO
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; @Keywords: Micron DRA821
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: j7vcl-ospi.cmm 11733 2023-01-16 08:55:12Z bschroefel $
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PRIVATE ¶meters
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ENTRY %LINE ¶meters
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PRIVATE ¶m_prepareonly ¶m_dualport
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¶meters=STRing.UPpeR("¶meters")
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¶m_prepareonly=(STRing.SCAN("¶meters","PREPAREONLY",0)!=-1)
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¶m_dualport=STRing.SCANAndExtract("¶meters","DUALPORT=","1")
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LOCAL &pdd
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&pdd=OS.PresentDemoDirectory()
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; --------------------------------------------------------------------------------
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LOCAL &OSPI_BASE &OSPI_MEMORY_BASE
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&OSPI_BASE=0x47040000
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&OSPI_MEMORY_BASE=0x50000000 ; flash contents memory mapped address
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; --------------------------------------------------------------------------------
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; Open the master core(CM3) to configure system
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; Basic attach via CortexM3
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RESet
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SYStem.RESet
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; Close leftover GUIs
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InterCom OTHERS QUIT
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; Open all SLAVE GUIs
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IF !INTERCOM.PING(CM3)
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TargetSystem.NewInstance CM3 /ARCHitecture ARM
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InterCom CM3 System.CPU DRA821-CM3
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InterCom CM3 SYStem.Option RESBREAK OFF
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InterCom CM3 SYStem.Option EnReset OFF
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InterCom CM3 SYStem.CONFIG SLAVE OFF
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InterCom CM3 SYSTEM.JTAGCLOCK CTCK 10MHz
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IF COMBIPROBE()||UTRACE()
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(
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InterCom CM3 SYStem.CONFIG.CONNECTOR MIPI34 ; because of converter LA-3782
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)
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; --------------------------------------------------------------------------------
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; Use Power-AP to signal initial states
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InterCom CM3 SYStem.Mode PREPARE
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InterCom CM3 Data.Set EDBG:0x400003f0 %Long 0x00190000 ; Ensure Power-AP unlocked
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InterCom CM3 Data.Set EDBG:0x400003f0 %Long 0yxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 ; Soft reset system
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WAIT 500.ms ; Wait some time for the system to stabilize
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InterCom CM3 Data.Set EDBG:0x400003f0 %Long 0x00190000 ; Ensure Power-AP unlocked
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InterCom CM3 Data.Set EDBG:0x40000344 %Long 0x00102098 ; j7vcl: Force M3 Power & Clock to active
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InterCom CM3 SYStem.Up
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; Enable GTC for debug timestamps, 0x3=freeze in debug halt
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InterCom CM3 Data.Set EZAXI:0x00A90000 %LE %Long 0x1
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; --------------------------------------------------------------------------------
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; Basic board setup via CortexM3
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; Disbale CR5-MCU lockstep
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InterCom CM3 Data.Set EZAXI:0x45A50040 %Long 0x00000000
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; Enable necessary clock domains
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 4. 0x1 0x3 ; LPSC_WKUPMCU2MAIN
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InterCom.WAIT CM3
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; Configure PLLs
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_pll MAIN
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_pll DEBUG
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_pll MCU0
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_pll MCU1
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_pll MCU2
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InterCom.WAIT CM3
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; Enable Power
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 0. 0x1 0x3 ; LPSC_WKUP_ALWAYSON
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 1. 0x1 0x3 ; LPSC_DMSC
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 2. 0x1 0x3 ; LPSC_DEBUG2DMSC
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 7. 0x1 0x3 ; LPSC_MCU_DEBUG
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 10. 0x1 0x3 ; LPSC_MCU_OSPI_0
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InterCom.WAIT CM3
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InterCom CM3 Do &pdd/hardware/j7vcl/scripts/configure_psc 0. 0. 11. 0x1 0x3 ; LPSC_MCU_OSPI_1
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InterCom.WAIT CM3
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; Close CM3 GUI
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InterCom OTHERS QUIT
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; --------------------------------------------------------------------------------
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; Connect to MCU-CR5 to program flash
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; The following CPU selections are equivalent:
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SYStem.CPU DRA821-CR5-MCU
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SYStem.CONFIG CORE 3. 1.
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CORE.ASSIGN 1.
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SYStem.Option RB off
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SYStem.Option EnReset OFF
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SYStem.MemAccess DAP ;Enable to use the dualport
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SYStem.Option TRST OFF
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SYStem.Attach
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Break
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GOSUB CLK_INIT
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GOSUB PIN_MUX
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GOSUB OSPI_INIT
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GOSUB CACHE_MMU_INIT
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&pdd=OS.PresentDemoDirectory()
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Break.RESet
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FLASH.RESet
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FLASH.Create 1. &OSPI_MEMORY_BASE++0x03FFFFFF 0x20000 TARGET Byte ; for MT35XU512 sector layout
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IF ("¶m_dualport"!="1")
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FLASH.TARGET 0x41C00000 0x41C00000+0x2000 0x1000 ~~/demo/arm/flash/byte/snor_am752x.bin
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ELSE
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FLASH.TARGET 0x41C00000 E:0x41C00000+0x2000 0x1000 ~~/demo/arm/flash/byte/snor_am752x.bin /DUALPORT
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; Re-enable I cache
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Data.Set C15:0x1 %long (Data.Long(C15:0x1)|(0x1<<12.)) ; enable I cache
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; Read FLASH Manufacturer and Device ID
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SILENT.FLASH.SPI.CMD 1. 0x9F /READ 0x4 vm:0x0
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IF (Data.Long(vm:0)&0xFFFF)==0x5B34 //S28HS512 id code
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(
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PRINT "spi flash is S28HS512"
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GOSUB SPI_4B_ADDRMODE_ENABLE
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SILENT.FLASH.SPI.CMD 1. 0x65 0x00 0x80 0x00 0x04 0x0 /READ 0x1 vm:0 ; Read Any Register to verify CFR3V
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IF (Data.Byte(vm:0)&0x08)==0x00 //00: hybrid
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(
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PRINT "detect the flash is the hybrid mode"
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FLASH.Delete 1.
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FLASH.Create 1. (&OSPI_MEMORY_BASE+0x00000000)++0x0001FFFF 0x01000 TARGET Byte ; 32 x 4K
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FLASH.Create 1. (&OSPI_MEMORY_BASE+0x00020000)++0x0001FFFF 0x20000 TARGET Byte ; 1 x 128k
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FLASH.Create 1. (&OSPI_MEMORY_BASE+0x00040000)++(0x03FFFFFF-0x40000) 0x40000 TARGET Byte ; rest x 256k
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)
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ELSE // uniform mode
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(
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FLASH.Delete 1.
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FLASH.Create 1. &OSPI_MEMORY_BASE++0x03FFFFFF 0x40000 TARGET Byte
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)
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)
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; Flash script ends here if called with parameter PREPAREONLY
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IF ¶m_prepareonly
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ENDDO PREPAREDONE
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; --------------------------------------------------------------------------------
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; Flash programming example
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DIALOG.YESNO "Program flash memory?"
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LOCAL &progflash
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ENTRY &progflash
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IF &progflash
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(
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FLASH.ReProgram.ALL
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Data.LOAD.auto *
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;Data.LOAD.Binary * &OSPI_MEMORY_BASE
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FLASH.ReProgram.off
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; Reset device
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PRINT "Please power-cycle the board after flash program is complete"
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)
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ENDDO
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READ_ID_TEST:
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(
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; In case of errors you can try to read the ID via:
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; GOSUB READ_ID_TEST
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;
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; Check the output of the AREA window.
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; Expected output ID:
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; 0x2C
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; 0x5A (or 0x5B)
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; 0x1A
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; 0x10
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; 0x41
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; 0x00 (or 0x04)
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; ... (Unique ID code)
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LOCAL &rdata
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&CTRLREG=&OSPI_BASE+0x090
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&RXDATA0=&OSPI_BASE+0x0A0
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&RXDATA1=&OSPI_BASE+0x0A4
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&cmd=0x9f<<24. //cmd
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&rd=0x1<<23. //rd data enable
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&rd_num=0x7<<20. //7+1==8bytes
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&cmd_exec=0x1 //cmd execution
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Data.Set EZAXI:&CTRLREG %LE %Long (&cmd|&cmd_exec|&rd_num|&rd) ;write cmd + write data
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WAIT 100.ms
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&rdata=Data.Long(EZAXI:&RXDATA0) ;read lower , 8byte fifo
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PRINT "1st 0x" (&rdata)&0xFF " (Manufacturer)" ; //RXFIFO0
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PRINT "2nd 0x" (&rdata>>8.)&0xFF " (Device ID)"
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PRINT "3rd 0x" (&rdata>>16.)&0xFF
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PRINT "4th 0x" (&rdata>>24.)&0xFF
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&rdata=Data.Long(EZAXI:&RXDATA1) ;read upper , 8byte fifo
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PRINT "5th 0x" (&rdata)&0xFF
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PRINT "6th 0x" (&rdata>>8.)&0xFF
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PRINT "7th 0x" (&rdata>>16.)&0xFF
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PRINT "8th 0x" (&rdata>>24.)&0xFF
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RETURN
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)
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OSPI_INIT:
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(
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Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x0
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Data.Set EZAXI:&OSPI_BASE+0x4 %LE %Long 0x00000013 ; 4B Addr Read
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Data.Set EZAXI:&OSPI_BASE+0x8 %LE %Long 0x00000012 ; 4B Addr Write
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Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x80800000
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Data.Set EZAXI:&OSPI_BASE+0x14 %LE %Long 0x1003; 4B Address mode, 3B Addr: 0x1002
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Data.Set EZAXI:&OSPI_BASE+0x10 %LE %Long 0x21
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Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0xFFFFFFFF
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Data.Set EZAXI:&OSPI_BASE+0xC %LE %Long (0xFF<<16.)|(0xFF<<8.) ; !!!!! OSPI_DEV_DELAY_REG because of writing !!!!!
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Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x00000081|(0x1<<19.)|(0xE<<10.) ; 0x1==baudrate_div4, enable usage of OSPI_CS0
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Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0x04000000 ;ospi_setdirectcutoff, end of the flash address
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RETURN
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)
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PIN_MUX:
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(
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;MMR_unlock
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Data.Set EZAXI:0x4301D008 %Long 0x68EF3490 ;CTRLMMR_WKUP_LOCK7_KICK0
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Data.Set EZAXI:0x4301D00C %Long 0xD172BC5A
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Data.Set EZAXI:0x4301C000 %Long 0x00040000 ;CTRLMMR_WKUP_PADCONFIG0
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Data.Set EZAXI:0x4301C004 %Long 0x00040000
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Data.Set EZAXI:0x4301C008 %Long 0x00040000
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Data.Set EZAXI:0x4301C00C %Long 0x00040000
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Data.Set EZAXI:0x4301C010 %Long 0x00040000
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Data.Set EZAXI:0x4301C014 %Long 0x00040000
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Data.Set EZAXI:0x4301C018 %Long 0x00040000
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Data.Set EZAXI:0x4301C01C %Long 0x00040000
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Data.Set EZAXI:0x4301C020 %Long 0x00040000
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Data.Set EZAXI:0x4301C024 %Long 0x00040000
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Data.Set EZAXI:0x4301C028 %Long 0x00040000
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Data.Set EZAXI:0x4301C02C %Long 0x00040000
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Data.Set EZAXI:0x4301C030 %Long 0x00040000
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Data.Set EZAXI:0x4301C038 %Long 0x00040001
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Data.Set EZAXI:0x4301C03C %Long 0x00040001
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RETURN
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)
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CLK_INIT:
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(
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PRIVATE &HSDIV_OPTION
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; If there are flashing issues or if it fails, try to modfy the following value.
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; The valid range is: 0x3 <= &HSDIV_OPTION <= 0x8
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&HSDIV_OPTION=0x5
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; Set clock source
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Data.Set EZAXI:0x40F09008 %Long 0x68EF3490 ; CTRLMMR_MCU_LOCK2_KICK0
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Data.Set EZAXI:0x40F0900C %Long 0xD172BC5A
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Data.Set EZAXI:0x40F08030 %Long 0x1 ; CTRLMMR_MCU_OSPI0_CLKSEL: 0x1 = MCU_PLL2_HSDIV4_CLKOUT
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; Adjust PLL for MCU_PLL2_HSDIV4_CLKOUT
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Do &pdd/hardware/j7vcl/scripts/configure_pll _CFG_ BYPASS MCU 2.
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Do &pdd/hardware/j7vcl/scripts/configure_pll _CFG_ DIV MCU 2. 0x2 0x1 0x1 0x68 0x2AAAAB
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Do &pdd/hardware/j7vcl/scripts/configure_pll _CFG_ HSDIV MCU 2. 4. &HSDIV_OPTION
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Do &pdd/hardware/j7vcl/scripts/configure_pll _CFG_ ENABLE MCU 2.
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RETURN
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)
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CACHE_MMU_INIT:
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(
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PRIVATE &i &tmpReg
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; Enable MPU and disable I and D caches
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&tmpReg=Data.Long(C15:0x1)
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&tmpReg=&tmpReg|0x1 ; enable MPU
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&tmpReg=(&tmpReg&(~(0x1<<2.))) ; disable D cache
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&tmpReg=(&tmpReg&(~(0x1<<12.))) ; disable I cache
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Data.Set C15:0x1 %long &tmpReg
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; Configure small region setup for flash programming
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PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x016 %Long 0x00000000 ; set default
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PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x216 %Long 0x0000003F
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PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x416 %Long 0x00001310
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PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x016 %Long 0x50000000 ; setup flash window
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PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x216 %Long 0x00000035
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PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x416 %Long 0x00001301
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PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x016 %Long 0x41C00000 ; setup buffer space
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PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x216 %Long 0x00000027
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PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x416 %Long 0x0000030C
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; Reset all other MPU regions
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&i=3.
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while &i<16.
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(
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PER.Set.SaveIndex C15:0x026 %Long &i C15:0x016 %Long 0x0
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PER.Set.SaveIndex C15:0x026 %Long &i C15:0x216 %Long 0x0
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PER.Set.SaveIndex C15:0x026 %Long &i C15:0x416 %Long 0x0
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&i=&i+1.
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)
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RETURN
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)
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// detect the flash address mode by the internal flash register (0x0080_0003)
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// CR2V : should come 0x08(3B) or 0x88(4B)
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SPI_4B_ADDRMODE_ENABLE:
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(
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SILENT.FLASH.SPI.CMD 1. 0x06
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SILENT.FLASH.SPI.CMD 1. 0x71 0x80 0x00 0x03 0x88 ; write 0x88 to CR2V , switch 3B->4B address mode
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Data.Set VM:0x0--0xFF %Long 0x0
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SILENT.FLASH.SPI.CMD 1. 0x65 0x00 0x80 0x00 0x03 0x0 /READ 0x4 vm:0x0 ;4Bytes Address mode
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®Data=Data.Byte(vm:0x0)
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IF ®Data!=0x88
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(
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PRinT "We expect 0x08 latency(dummy) cycles but we got the dummy cycle 0x" %Hex ®Data
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ENDDO
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)
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RETURN
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)
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