328 lines
11 KiB
Plaintext
328 lines
11 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: OSPI FLASH Program script for the AM644x on AM6X-SKEVM
|
|
; @Description:
|
|
; S28HS512 Samper flash is on OSPI_CS0 ( Cortex-R5 MAIN0 )
|
|
;
|
|
; SRAM: 0x70010000
|
|
; OSPI(controller) Base: 0x0FC40000
|
|
; OSPI memory mapped ADDRESS: 0x60000000 (FSS0_DAT_REG1)
|
|
;
|
|
; Prerequisites:
|
|
; * Connect Debug Cable to J14 via adapter LA-3780
|
|
;
|
|
; @Keywords: ARM, Cortex-R5, OSPI, S28HS512
|
|
; @Author: CMO JIM
|
|
; @Board: AM6X-SKEVM
|
|
; @Chip: AM6442-CR5-MAIN0
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: am644x-ospi.cmm 12716 2023-11-14 12:49:25Z mschaeffner $
|
|
|
|
PRIVATE ¶meters
|
|
ENTRY %LINE ¶meters
|
|
|
|
PRIVATE ¶m_prepareonly ¶m_dualport
|
|
¶meters=STRing.UPpeR("¶meters")
|
|
¶m_prepareonly=(STRing.SCAN("¶meters","PREPAREONLY",0)!=-1)
|
|
¶m_dualport=STRing.SCANAndExtract("¶meters","DUALPORT=","1")
|
|
|
|
PRIVATE &pdd &AUX_SCRIPT_DIR
|
|
|
|
LOCAL &OSPI_BASE &OSPI_MEMORY_BASE
|
|
&OSPI_BASE=0x0FC40000
|
|
&OSPI_MEMORY_BASE=0x60000000 ; flash contents memory mapped address FSS0_DAT_REG1
|
|
|
|
WINCLEAR
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Basic attach via CortexM3 (Master)
|
|
System.CPU AM6442-CM3
|
|
SYStem.CONFIG CORE 1. 1.
|
|
SYStem.Option RESBREAK OFF
|
|
SYStem.Option EnReset OFF
|
|
SYSTEM.JTAGCLOCK CTCK 10MHz
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Use Power-AP to signal initial states
|
|
SYStem.Mode PREPARE
|
|
Data.Set EDBG:0x400003f0 %Long 0x00190000 ; Ensure Power-AP unlocked
|
|
Data.Set EDBG:0x400003f0 %Long 0yxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 ; Soft reset system
|
|
WAIT 500.ms ; Wait some time for system to stabilize
|
|
Data.Set EDBG:0x400003f0 %Long 0x00190000 ; Ensure Power-AP unlocked
|
|
Data.Set EDBG:0x40000344 %Long 0x00102098 ; Force M3 Power & Clock to active
|
|
|
|
SYStem.Up
|
|
|
|
&pdd=OS.PresentDemoDirectory()
|
|
&AUX_SCRIPT_DIR="&pdd/hardware/am64xx/am64x-skevm/scripts"
|
|
|
|
; Enable GTC for debug timestamps, 0x3=freeze in debug halt
|
|
Data.Set EZAXI:0x00A90000 %LE %Long 0x1
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Configure R5 cores to halt on power up. Otherwise an attach might not be possible
|
|
Data.Set EZAXI:0x45a00120 %LE %Long 1
|
|
Data.Set EZAXI:0x45a001A0 %LE %Long 1
|
|
|
|
; Configure CR5 ATCM
|
|
Data.Set EZAXI:0x45a00100 %LE %Long 0x888
|
|
Data.Set EZAXI:0x45a00180 %LE %Long 0x888
|
|
|
|
; Disable CR5-MAIN0 lockstep
|
|
Data.Set EZAXI:0x45a00040 %Long 0x00000000
|
|
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Basic board setup via CortexM3
|
|
; Configure PLLs
|
|
Do "&AUX_SCRIPT_DIR/configure_pll.cmm" MAIN
|
|
Do "&AUX_SCRIPT_DIR/configure_pll.cmm" CR5-MAIN
|
|
Do "&AUX_SCRIPT_DIR/configure_pll.cmm" DDR25
|
|
|
|
; Enable Power
|
|
Do "&AUX_SCRIPT_DIR/configure_psc.cmm" 0. 0. 0. 0x1 0x3 ; LPSC_MAIN_ALWAYSON
|
|
Do "&AUX_SCRIPT_DIR/configure_psc.cmm" 0. 0. 3. 0x1 0x3 ; LPSC_DMSC
|
|
|
|
Do "&AUX_SCRIPT_DIR/configure_psc.cmm" 0. 4. 24. 0x1 0x3 ; LPSC_PULSAR_0_R5_0
|
|
Do "&AUX_SCRIPT_DIR/configure_psc.cmm" 0. 4. 25. 0x1 0x3 ; LPSC_PULSAR_0_R5_1
|
|
Do "&AUX_SCRIPT_DIR/configure_psc.cmm" 0. 4. 26. 0x1 0x3 ; LPSC_PULSAR_PBIST_0
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; board setup via CortexR5
|
|
SYStem.Down
|
|
SYStem.CPU AM64XX-CR5-MAIN0
|
|
SYStem.CONFIG CORE 3. 1.
|
|
CORE.ASSIGN 1.
|
|
SYStem.Option RB off
|
|
SYStem.Option EnReset OFF
|
|
SYStem.MemAccess DAP ;Enable to use the dualport
|
|
|
|
SYStem.Option TRST OFF
|
|
SYStem.Attach
|
|
Break
|
|
|
|
; Enable GTC for debug timestamps, 0x3=freeze in debug halt
|
|
Data.Set EZAXI:0x00A90000 %LE %Long 0x1
|
|
|
|
SCREEN.OFF
|
|
GOSUB PIN_MUX
|
|
GOSUB OSPI_INIT
|
|
GOSUB CACHE_MMU_INIT
|
|
SCREEN.ON
|
|
|
|
PER.Set.simple C15:0x1 %Long data.long(C15:0x1)&~0x1005 ;disable mmu
|
|
|
|
GOSUB READ_ID_TEST
|
|
|
|
Break.RESet
|
|
FLASH.RESet
|
|
FLASH.Create 1. &OSPI_MEMORY_BASE++0x03FFFFFF 0x40000 TARGET Byte ; for MT35XU512 sector layout
|
|
|
|
IF ("¶m_dualport"!="1")
|
|
FLASH.TARGET 0x70010000 0x70010000+0x2000 0x1000 ~~/demo/arm/flash/byte/snor_am644x.bin
|
|
ELSE
|
|
FLASH.TARGET 0x70010000 E:0x70010000+0x2000 0x1000 ~~/demo/arm/flash/byte/snor_am644x.bin /DUALPORT
|
|
|
|
; Read FLASH Manufacturer and Device ID
|
|
SILENT.FLASH.SPI.CMD 1. 0x9F /READ 0x4 vm:0x0
|
|
IF (Data.Long(vm:0)&0xFFFF)==0x5B34 //S28HS512 id code
|
|
(
|
|
PRINT "spi flash is S28HS512"
|
|
|
|
GOSUB SPI_4B_ADDRMODE_ENABLE
|
|
SILENT.FLASH.SPI.CMD 1. 0x65 0x00 0x80 0x00 0x04 0x0 /READ 0x1 vm:0 ; Read Any Register to verify CFR3V
|
|
IF (Data.Byte(vm:0)&0x08)==0x00 //00: hybrid
|
|
(
|
|
PRINT "detect the flash is the hybrid mode"
|
|
FLASH.Delete 1.
|
|
FLASH.Create 1. (&OSPI_MEMORY_BASE+0x00000000)++0x0001FFFF 0x01000 TARGET Byte ; 32 x 4K
|
|
FLASH.Create 1. (&OSPI_MEMORY_BASE+0x00020000)++0x0001FFFF 0x20000 TARGET Byte ; 1 x 128k
|
|
FLASH.Create 1. (&OSPI_MEMORY_BASE+0x00040000)++(0x03FFFFFF-0x40000) 0x40000 TARGET Byte ; rest x 256k
|
|
)
|
|
ELSE // uniform mode
|
|
(
|
|
FLASH.Delete 1.
|
|
FLASH.Create 1. &OSPI_MEMORY_BASE++0x03FFFFFF 0x40000 TARGET Byte
|
|
)
|
|
)
|
|
|
|
; Flash script ends here if called with parameter PREPAREONLY
|
|
IF ¶m_prepareonly
|
|
ENDDO PREPAREDONE
|
|
|
|
; --------------------------------------------------------------------------------
|
|
; Flash programming example
|
|
DIALOG.YESNO "Program flash memory?"
|
|
LOCAL &progflash
|
|
ENTRY &progflash
|
|
IF &progflash
|
|
(
|
|
FLASH.ReProgram.ALL
|
|
Data.LOAD.auto *
|
|
;Data.LOAD.Binary * &OSPI_MEMORY_BASE
|
|
FLASH.ReProgram.off
|
|
|
|
; Reset device
|
|
PRINT "Please power-cycle the board after flash program is complete"
|
|
)
|
|
|
|
ENDDO
|
|
|
|
|
|
READ_ID_TEST:
|
|
(
|
|
; In case of errors you can try to read the ID via:
|
|
; GOSUB READ_ID_TEST
|
|
;
|
|
; Check the output of the AREA window.
|
|
; Expected output ID for S28HS512
|
|
; 0x34
|
|
; 0x5B (or 0x5B)
|
|
; 0x1A
|
|
; 0x0F
|
|
; 0x3
|
|
; 0x90
|
|
; ...
|
|
|
|
|
|
LOCAL &rdata
|
|
&CTRLREG=&OSPI_BASE+0x090
|
|
&RXDATA0=&OSPI_BASE+0x0A0
|
|
&RXDATA1=&OSPI_BASE+0x0A4
|
|
|
|
&cmd=0x9f<<24. //cmd
|
|
&rd=0x1<<23. //rd data enable
|
|
&rd_num=0x7<<20. //7+1==8bytes
|
|
&cmd_exec=0x1 //cmd execution
|
|
|
|
Data.Set EZAXI:&CTRLREG %LE %Long (&cmd|&cmd_exec|&rd_num|&rd) ;write cmd + write data
|
|
WAIT 100.ms
|
|
|
|
&rdata=Data.Long(EZAXI:&RXDATA0) ;read lower , 8byte fifo
|
|
PRinT "1st 0x" (&rdata)&0xFF " (Manufacturer)" ; //RXFIFO0
|
|
PRinT "2nd 0x" (&rdata>>8.)&0xFF " (Device ID)"
|
|
PRinT "3rd 0x" (&rdata>>16.)&0xFF
|
|
PRinT "4th 0x" (&rdata>>24.)&0xFF
|
|
&rdata=Data.Long(EZAXI:&RXDATA1) ;read upper , 8byte fifo
|
|
PRinT "5th 0x" (&rdata)&0xFF
|
|
PRinT "6th 0x" (&rdata>>8.)&0xFF
|
|
PRinT "7th 0x" (&rdata>>16.)&0xFF
|
|
PRinT "8th 0x" (&rdata>>24.)&0xFF
|
|
|
|
RETURN
|
|
)
|
|
|
|
PIN_MUX:
|
|
(
|
|
; PinMux
|
|
Data.Set ZAXI:0x000F5008 %Long 0x68ef3490 ; PADMMR_LOCK5_KICK0 -> unlock I/O partition
|
|
Data.Set ZAXI:0x000F500C %Long 0xd172bc5a ; PADMMR_LOCK5_KICK1
|
|
screen.wait 10.ms
|
|
|
|
Data.Set EZAXI:0x000F4000 %Long 0x00000000 ; N20: PADCONFIG0 OSPI0_CLK
|
|
Data.Set EZAXI:0x000F4004 %Long 0x00040000 ; N21: PADCONFIG1 OSPI0_LBCLKO
|
|
Data.Set EZAXI:0x000F4008 %Long 0x00240000 ; N19: PADCONFIG2 OSPI0_DQS
|
|
Data.Set EZAXI:0x000F400C %Long 0x00040000 ; M19: PADCONFIG3 OSPI0_D0
|
|
Data.Set EZAXI:0x000F4010 %Long 0x00040000 ; M18: PADCONFIG4 OSPI0_D1
|
|
Data.Set EZAXI:0x000F4014 %Long 0x00040000 ; M20: PADCONFIG5 OSPI0_D2
|
|
Data.Set EZAXI:0x000F4018 %Long 0x00040000 ; M21: PADCONFIG6 OSPI0_D3
|
|
Data.Set EZAXI:0x000F401C %Long 0x00040000 ; P21: PADCONFIG7 OSPI0_D4
|
|
Data.Set EZAXI:0x000F4020 %Long 0x00040000 ; P20: PADCONFIG8 OSPI0_D5
|
|
Data.Set EZAXI:0x000F4024 %Long 0x00040000 ; N18: PADCONFIG9 OSPI0_D6
|
|
Data.Set EZAXI:0x000F4028 %Long 0x00040000 ; M17: PADCONFIG10 OSPI0_D7
|
|
Data.Set EZAXI:0x000F402C %Long 0x00000000 ; L19: PADCONFIG11 OSPI0_CSn0
|
|
Data.Set EZAXI:0x000F4030 %Long 0x00000000 ; L18: PADCONFIG12 OSPI0_CSn1
|
|
Data.Set EZAXI:0x000F4034 %Long 0x00000002 ; K17: PADCONFIG13 OSPI0_CSn2
|
|
Data.Set EZAXI:0x000F4038 %Long 0x00000001 ; L17: PADCONFIG14 OSPI0_CSn3
|
|
|
|
Data.Set ZAXI:0x000F5008 %Long 0x43015008 ; PADMMR_LOCK5_KICK0 -> lock I/O partition
|
|
Data.Set ZAXI:0x000F500C %Long 0x4301500C ; PADLMMR_LOCK5_KICK1
|
|
|
|
RETURN
|
|
)
|
|
|
|
CLK_INIT:
|
|
(
|
|
RETURN
|
|
)
|
|
|
|
|
|
CACHE_MMU_INIT:
|
|
(
|
|
PRIVATE &i &tmpReg
|
|
|
|
; Enable MPU and disable I and D caches
|
|
&tmpReg=Data.Long(C15:0x1)
|
|
&tmpReg=&tmpReg|0x1 ; enable MPU
|
|
&tmpReg=(&tmpReg&(~(0x1<<2.))) ; disable D cache
|
|
&tmpReg=(&tmpReg&(~(0x1<<12.))) ; disable I cache
|
|
Data.Set C15:0x1 %Long &tmpReg
|
|
|
|
; Configure small region setup for flash programming
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x016 %Long 0x00000000 ; set default
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x216 %Long 0x0000003F
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x0 C15:0x416 %Long 0x00001310
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x016 %Long 0x60000000 ; setup flash window
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x216 %Long 0x00000035
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x1 C15:0x416 %Long 0x00001301
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x016 %Long 0x70000000 ; setup buffer space
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x216 %Long 0x00000027
|
|
PER.Set.SaveIndex C15:0x026 %Long 0x2 C15:0x416 %Long 0x0000030C
|
|
; Reset all other MPU regions
|
|
&i=3.
|
|
WHILE &i<16.
|
|
(
|
|
PER.Set.SaveIndex C15:0x026 %Long &i C15:0x016 %Long 0x0
|
|
PER.Set.SaveIndex C15:0x026 %Long &i C15:0x216 %Long 0x0
|
|
PER.Set.SaveIndex C15:0x026 %Long &i C15:0x416 %Long 0x0
|
|
&i=&i+1.
|
|
)
|
|
|
|
RETURN
|
|
)
|
|
|
|
OSPI_INIT:
|
|
(
|
|
Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x0
|
|
Data.Set EZAXI:&OSPI_BASE+0x4 %LE %Long 0x00000013 ; 4B Addr Read
|
|
Data.Set EZAXI:&OSPI_BASE+0x8 %LE %Long 0x00000012 ; 4B Addr Write
|
|
|
|
Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x80800000
|
|
Data.Set EZAXI:&OSPI_BASE+0x14 %LE %Long 0x1003; 4B Address mode, 3B Addr: 0x1002
|
|
Data.Set EZAXI:&OSPI_BASE+0x10 %LE %Long 0x21
|
|
|
|
Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0xFFFFFFFF
|
|
Data.Set EZAXI:&OSPI_BASE+0xC %LE %Long (0xFF<<16.)|(0xFF<<8.) ; !!!!! OSPI_DEV_DELAY_REG because of writing !!!!!
|
|
Data.Set EZAXI:&OSPI_BASE+0x0 %LE %Long 0x00000081|(0x1<<19.)|(0xE<<10.) ; 0x1==baudrate_div4, enable usage of OSPI_CS0
|
|
Data.Set EZAXI:&OSPI_BASE+0x1C %LE %Long 0x04000000 ;ospi_setdirectcutoff, end of the flash address
|
|
|
|
RETURN
|
|
)
|
|
|
|
SPI_4B_ADDRMODE_ENABLE:
|
|
(
|
|
Data.Set VM:0x0--0xFF %Long 0x0
|
|
SILENT.FLASH.SPI.CMD 1. 0x65 0x80 0x00 0x03 0x0 /READ 0x1 vm:0x0 ;3Bytes Address mode
|
|
®Data=Data.Byte(vm:0x0)
|
|
IF ®Data==0x08
|
|
( // it means the current flash is 3Byte address mode, so it should switch to the 4Byte address mode for the 4b flash driver file.
|
|
SILENT.FLASH.SPI.CMD 1. 0x65 0x80 0x00 0x03 0x00 /READ 0x1 vm:0x0 ;3Bytes Address mode
|
|
SILENT.FLASH.SPI.CMD 1. 0x06
|
|
SILENT.FLASH.SPI.CMD 1. 0x71 0x80 0x00 0x03 0x88 ; write 0x88 to CR2V , switch 3B->4B address mode
|
|
WAIT 10.ms
|
|
)
|
|
|
|
SILENT.FLASH.SPI.CMD 1. 0x65 0x00 0x80 0x00 0x03 0x0 /READ 0x1 vm:0x0 ;4Bytes Address mode
|
|
®Data=Data.Byte(vm:0x0)
|
|
IF ®Data==0x88
|
|
(
|
|
PRINT "4Bytes address mode enabled"
|
|
)
|
|
ELSE
|
|
(
|
|
PRINT "We expect 0x08 latency(dummy) cycles but we got the dummy cycle 0x" %Hex ®Data
|
|
ENDDO
|
|
)
|
|
RETURN
|
|
)
|