231 lines
4.2 KiB
C
231 lines
4.2 KiB
C
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/**************************************************************************
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ARM DCC communication variant
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DEFINES:
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ARM7 : Use Communication Registers for ARM7
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ARM9 : Use Communication Registers for ARM9
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ARM11 : Use Communication Registers for ARM11
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XSCALE : Use Communication Registers for XSCALE
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CORTEXR: Use Communication Registers for CortexRx (AArch32 & AArch64)
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CORTEXA: Use Communication Registers for CortexAx (AArch32 & AArch64)
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**************************************************************************/
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#if defined(T32_FDX_DCC)||defined(T32_FDX_DCC3)
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#if defined(ARM9)||defined(ARM7)
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unsigned int T32_TsMon_SendStatus(void)
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{
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int status;
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#ifdef __GNUC__
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__asm__ volatile("mrc p14, 0, %0, c0, c0" : "=r" (status));
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#else
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__asm
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{
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MRC p14, 0, status, c0, c0;
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}
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#endif
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return (status & 2);
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}
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void T32_TsMon_SendWord(unsigned int data)
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{
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#ifdef __GNUC__
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__asm__ volatile("mcr p14, 0, %0, c1, c0" : :"r" (data));
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#else
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__asm
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{
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MCR p14, 0, data, c1, c0
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}
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#endif
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}
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unsigned int T32_TsMon_ReceiveStatus(void)
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{
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int status;
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#ifdef __GNUC__
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__asm__ volatile("mrc p14, 0, %0, c0, c0" : "=r" (status));
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#else
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__asm
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{
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MRC p14, 0, status, c0, c0;
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}
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#endif
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return (status & 1);
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}
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unsigned int T32_TsMon_ReceiveWord(void)
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{
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unsigned int data;
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#ifdef __GNUC__
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__asm__ volatile("mrc p14, 0, %0, c1, c0" : "=r" (data));
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#else
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__asm
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{
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MRC p14, 0, data, c1, c0;
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}
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#endif
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return data;
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}
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#endif
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#if defined(ARM11)||defined(CORTEXA)||defined(CORTEXR)
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unsigned int T32_TsMon_SendStatus(void)
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{
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int status;
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#ifdef __GNUC__
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#ifdef __aarch64__
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__asm__ volatile("mrs %0, mdccsr_el0" : "=r" (status));
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#else
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__asm__ volatile("mrc p14, 0, %0, c0, c1" : "=r" (status));
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#endif
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#else
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__asm
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{
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MRC p14, 0, status, c0, c1;
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}
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#endif
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return (status & 0x20000000);
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}
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void T32_TsMon_SendWord(unsigned int data)
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{
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#ifdef __GNUC__
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#ifdef __aarch64__
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__asm__ volatile("msr dbgdtrtx_el0, %0" : : "r" (data));
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#else
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__asm__ volatile("mcr p14, 0, %0, c0, c5" : : "r" (data));
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#endif
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#else
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__asm
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{
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MCR p14, 0, data, c0, c5
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}
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#endif
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}
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unsigned int T32_TsMon_ReceiveStatus(void)
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{
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int status;
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#ifdef __GNUC__
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#ifdef __aarch64__
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__asm__ volatile("mrs %0, mdccsr_el0" : "=r" (status));
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#else
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__asm__ volatile("mrc p14, 0, %0, c0, c1" : "=r" (status));
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#endif
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#else
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__asm
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{
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MRC p14, 0, status, c0, c1;
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}
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#endif
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return (status & 0x40000000);
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}
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unsigned int T32_TsMon_ReceiveWord(void)
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{
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unsigned int data;
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#ifdef __GNUC__
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#ifdef __aarch64__
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__asm__ volatile("mrs %0, dbgdtrrx_el0" : "=r" (data));
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#else
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__asm__ volatile("mrc p14, 0, %0, c0, c5" : "=r" (data));
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#endif
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#else
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__asm
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{
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MRC p14, 0, data, c0, c5;
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}
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#endif
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return data;
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}
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#endif
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#ifdef XSCALE
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unsigned int T32_TsMon_SendStatus(void)
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{
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int status;
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#ifdef __GNUC__
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__asm__ volatile("mrc p14, 0, %0, c14, c0" : "=r" (status));
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#else
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__asm
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{
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MRC p14, 0, status, c14, c0, 0;
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}
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#endif
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return (status & 0x10000000);
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}
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void T32_TsMon_SendWord(unsigned int data)
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{
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#ifdef __GNUC__
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__asm__ volatile("mcr p14, 0, %0, c8, c0" : : "r" (data));
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#else
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__asm
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{
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MCR p14, 0, data, c8, c0, 0
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}
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#endif
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}
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unsigned int T32_TsMon_ReceiveStatus(void)
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{
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int status;
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#ifdef __GNUC__
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__asm__ volatile("mrc p14, 0, %0, c14, c0" : "=r" (status));
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#else
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__asm
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{
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MRC p14, 0, status, c14, c0, 0;
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}
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#endif
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return (status & 0x80000000);
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}
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unsigned int T32_TsMon_ReceiveWord(void)
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{
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unsigned int data;
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#ifdef __GNUC__
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__asm__ volatile("mrc p14, 0, %0, c9, c0" : "=r" (data));
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#else
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__asm
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{
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MRC p14, 0, data, c9, c0, 0;
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}
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#endif
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return data;
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}
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#endif
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#endif
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/**************************************************************************
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ARM timebase (enter code here)
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**************************************************************************/
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unsigned long T32_Fdx_GetTimebase()
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{
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return 0;
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}
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