; -------------------------------------------------------------------------------- ; @Title: STM32L4 On-Chip Peripherals ; @Props: Released ; @Author: MKK, MAJ, KOL, WWI, KAW, BCA, DPR, TRJ, ASK ; @Changelog: 2015-11-03 MAJ ; 2016-09-08 WWI ; 2016-11-21 KOL ; 2017-01-30 KAW ; 2017-11-07 KOL ; 2017-11-17 DPR ; 2017-12-13 ASK ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: RM0351_Rev0.2.pdf ; RM0351_Rev0.3.pdf ; DM00108832_L476xx.pdf ; DM00108833_L486xx.pdf ; DM00149404_L471xx.pdf ; DM00172872_L475xx.pdf ; DM00254865_L443xx.pdf ; DM00257192_L433xx.pdf ; DM00257195_L442KC.pdf ; DM00257205_L432xx.pdf ; RM0351_L4x6.pdf (Rev 4 2016-06) ; RM0392_L4x1.pdf ; RM0393_L4x2.pdf ; RM0394_L4x3.pdf ; RM0395_L4x5.pdf ; RM0394_L431_L433_L443.pdf ; DM00257211_L431xx.pdf ; DM00284207_L4A6xG.pdf (Rev 1 2017-02) ; DM00284211_L496.pdf (Rev 1 2017-02) ; RM_DM00083560_L4x5_L4x6.pdf (Rev 5 2017-03) ; en.DM00083560.pdf (Rev 5 2017-03) ; en.DM00149427.pdf (Rev 2 2016-05) ; en.DM00151940.pdf (Rev 3 2017-04) ; en.DM00151935.pdf (Rev 2 2016-05) ; en.DM00257205.pdf (Rev 3 2017-06) ; en.DM00257192.pdf (Rev 4 2017-06) ; en.DM00257195.pdf (Rev 3 2017-06) ; en.DM00254865.pdf (Rev 3 2017-06) ; en.DM00149404.pdf (Rev 1 2016-02) ; en.DM00172872.pdf (Rev 3 2017-10) ; @Chip: STM32L476JG, STM32L476QE, STM32L476QG, STM32L476RC, STM32L476RE, ; STM32L476RG, STM32L476VC, STM32L476VE, STM32L476VG, STM32L476ZE, ; STM32L476ZG, STM32L432KC, STM32L433CC, STM32L433RC, STM32L433VC, ; STM32L442KC, STM32L443CC, STM32L443RC, STM32L443VC, STM32L471QE, ; STM32L471QG, STM32L471RE, STM32L471RG, STM32L471VE, STM32L471VG, ; STM32L471ZE, STM32L471ZG, STM32L475RC, STM32L475RE, STM32L475RG, ; STM32L475VC, STM32L475VE, STM32L475VG, STM32L476JE, STM32L476ME, ; STM32L476MG, STM32L486JG, STM32L431CB, STM32L431CC, STM32L431KB, ; STM32L431KC, STM32L431RB, STM32L431RC, STM32L431VC, STM32L432KB, ; STM32L433CB, STM32L433RB, STM32L4A6RG, STM32L4A6VG, STM32L4A6QG, ; STM32L4A6ZG, STM32L4A6AG, STM32L496RG, STM32L496RE, STM32L496VG, ; STM32L496VE, STM32L496QG, STM32L496QE, STM32L496ZG, STM32L496ZE, ; STM32L496AG, STM32L496AE, STM32L451CC, STM32L451CE, STM32L451RC, ; STM32L451RE, STM32L451VC, STM32L451VE, STM32L452CC, STM32L452CE, ; STM32L452RC, STM32L452RE, STM32L452VC, STM32L452VE, STM32L462CE, ; STM32L462RE, STM32L462VE ; @Core: Cortex-M4, Cortex-M4F ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32l4.per 17736 2024-04-08 09:26:07Z kwisniewski $ sif STRING.SCAN(CORENAME(),"M4F",0.)>0. tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end else tree.close "Core Registers (Cortex-M4)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif config 16. 8. tree "FLASH (Embedded flash memory)" base ad:0x40022000 width 16. if ((((per.l(ad:0x40022000))&0x400)==0x00)&&(((per.l(ad:0x40022000))&0x200)==0x00)) group.long 0x00++0x03 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 14. " SLEEP_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power sleep mode" "Idle,Power-down" bitfld.long 0x00 13. " RUN_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power run mode" "Idle,Power-down" bitfld.long 0x00 12. " DCRST ,Data cache reset" "Not reset,Reset" bitfld.long 0x00 11. " ICRST ,Instruction cache reset" "Not reset,Reset" textline " " bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LATENCY ,These bits represent the ratio of the SYSCLK (System clock) period to the flash access time" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,?..." elif ((((per.l(ad:0x40022000))&0x400)==0x00)&&(((per.l(ad:0x40022000))&0x200)==0x200)) group.long 0x00++0x03 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 14. " SLEEP_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power sleep mode" "Idle,Power-down" bitfld.long 0x00 13. " RUN_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power run mode" "Idle,Power-down" bitfld.long 0x00 12. " DCRST ,Data cache reset" "Not reset,Reset" rbitfld.long 0x00 11. " ICRST ,Instruction cache reset" "Not reset,Reset" textline " " bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LATENCY ,These bits represent the ratio of the SYSCLK (System clock) period to the flash access time" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,?..." elif ((((per.l(ad:0x40022000))&0x400)==0x400)&&(((per.l(ad:0x40022000))&0x200)==0x00)) group.long 0x00++0x03 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 14. " SLEEP_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power sleep mode" "Idle,Power-down" bitfld.long 0x00 13. " RUN_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power run mode" "Idle,Power-down" rbitfld.long 0x00 12. " DCRST ,Data cache reset" "Not reset,Reset" bitfld.long 0x00 11. " ICRST ,Instruction cache reset" "Not reset,Reset" textline " " bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LATENCY ,These bits represent the ratio of the SYSCLK (System clock) period to the flash access time" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,?..." elif ((((per.l(ad:0x40022000))&0x400)==0x400)&&(((per.l(ad:0x40022000))&0x200)==0x200)) group.long 0x00++0x03 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 14. " SLEEP_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power sleep mode" "Idle,Power-down" bitfld.long 0x00 13. " RUN_PD ,Determines whether the flash memory is in Power-down mode or idle mode when the device is in Low-power run mode" "Idle,Power-down" rbitfld.long 0x00 12. " DCRST ,Data cache reset" "Not reset,Reset" rbitfld.long 0x00 11. " ICRST ,Instruction cache reset" "Not reset,Reset" textline " " bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LATENCY ,These bits represent the ratio of the SYSCLK (System clock) period to the flash access time" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,?..." endif wgroup.long 0x04++0x0B line.long 0x00 "FLASH_PDKEYR,Flash Power-down Key Register" line.long 0x04 "FLASH_KEYR,Flash Key Register" line.long 0x08 "FLASH_OPTKEYR,Flash Option Key Register" group.long 0x10++0x0B line.long 0x00 "FLASH_SR,Flash Status Register" sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 17. " PEMPTY ,Program EMPTY" "Toggling,No effect" textline " " endif rbitfld.long 0x00 16. " BSY ,Busy" "Idle,Busy" eventfld.long 0x00 15. " OPTVERR ,Option validity error" "No error,Error" eventfld.long 0x00 14. " RDERR ,PCROP read error" "No error,Error" eventfld.long 0x00 9. " FASTERR ,Fast programming error" "No error,Error" textline " " eventfld.long 0x00 8. " MISERR ,Fast programming data miss error" "No error,Error" eventfld.long 0x00 7. " PGSERR ,Programming sequence error" "No error,Error" eventfld.long 0x00 6. " SIZERR ,Size error" "No error,Error" eventfld.long 0x00 5. " PGAERR ,Programming alignment error" "No error,Error" textline " " eventfld.long 0x00 4. " WRPERR ,Write protection error" "No error,Error" eventfld.long 0x00 3. " PROGERR ,Programming error" "No error,Error" eventfld.long 0x00 1. " OPERR ,Operation error" "No error,Error" eventfld.long 0x00 0. " EOP ,End of operation" "No EOP,EOP" line.long 0x04 "FLASH_CR,Flash Control Register" bitfld.long 0x04 31. " LOCK ,FLASH_CR lock" "Unlocked,Locked" bitfld.long 0x04 30. " OPTLOCK ,Options lock" "Unlocked,Locked" eventfld.long 0x04 27. " OBL_LAUNCH ,Force the option byte loading" "Completed,Requested" bitfld.long 0x04 26. " RDERRIE ,PCROP read error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled" bitfld.long 0x04 18. " FSTPG ,Fast programming" "Disabled,Enabled" bitfld.long 0x04 17. " OPTSTRT ,Options modification start" "Stopped,Started" textline " " bitfld.long 0x04 16. " START ,This bit triggers an erase operation when set" "Not erased,Erased" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x04 15. " MER2 ,Bank 2 mass erase" "No erase,Erase" bitfld.long 0x04 11. " BKER ,Page number MSB (Bank selection)" "Bank1,Bank2" endif hexmask.long.byte 0x04 3.--10. 1. " PNB ,Page number selection. Bank1 - 255:0 / bank2 - 511:256" textline " " bitfld.long 0x04 2. " MER1 ,Mass erase" "No erase,Erase" bitfld.long 0x04 1. " PER ,Page erase enable" "Disabled,Enabled" bitfld.long 0x04 0. " PG ,Programming" "Disabled,Enabled" line.long 0x08 "FLASH_ECCR,Flash ECC Register" eventfld.long 0x08 31. " ECCD ,ECC detection. Two ECC errors have been detected" "No effect,Errors detected" eventfld.long 0x08 30. " ECCC ,ECC correction. One ECC error has been detected and corrected" "No effect,Detected&fixed" bitfld.long 0x08 24. " ECCIE ,ECC correction interrupt enable" "Disabled,Enabled" rbitfld.long 0x08 20. " SYSF_ECC ,System flash ECC fail" "Not failed,Failed" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) rbitfld.long 0x08 19. " BK_ECC ,ECC fail bank" "Bank1,Bank2" textline " " endif hexmask.long.tbyte 0x08 0.--18. 1. " ADDR_ECC ,ECC fail address" group.long 0x20++0x13 line.long 0x00 "FLASH_OPTR,Flash Option Register" sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 27. " NBOOT0 ,NBOOT0 option bit" "0,1" bitfld.long 0x00 26. " NSWBOOT0 ,Software BOOT0" "NBOOT0,PH3/BOOT0" textline " " endif bitfld.long 0x00 25. " SRAM2_RST ,SRAM2 erase when system reset" "Erased,Not erased" bitfld.long 0x00 24. " SRAM2_PE ,SRAM2 parity check enable" "Enabled,Disabled" textline " " bitfld.long 0x00 23. " NBOOT1 ,Boot configuration" "0,1" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 21. " DUALBANK ,Dual-Bank on 512 KB or 256 KB flash memory devices" "Single-bank,Dual-bank" bitfld.long 0x00 20. " BFB2 ,Dual-bank boot" "Disabled,Enabled" endif textline " " bitfld.long 0x00 19. " WWDG_SW ,Window watchdog selection" "Hardware,Software" bitfld.long 0x00 18. " IWDG_STDBY ,Independent watchdog counter freeze in standby mode" "Frozen,Running" bitfld.long 0x00 17. " IWDG_STOP ,Independent watchdog counter freeze in stop mode" "Frozen,Running" textline " " bitfld.long 0x00 16. " IDWG_SW ,Independent watchdog selection" "Hardware,Software" bitfld.long 0x00 14. " NRST_SHDW ,Reset generated when entering the shutdown mode" "Reset,No reset" bitfld.long 0x00 13. " NRST_STDBY ,Reset generated when entering the standby mode" "Reset,No reset" bitfld.long 0x00 12. " NRST_STOP ,Reset generated when entering the stop mode" "Reset,No reset" textline " " bitfld.long 0x00 8.--10. " BOR_LEV ,BOR reset level" "Lvl0/1.7v,Lvl1/2.0v,Lvl2/2.2v,Lvl3/2.5v,Lvl4/2.8v,?..." hexmask.long.byte 0x00 0.--7. 1. " RDP ,Read protection level" line.long 0x04 "FLASH_PCROP1SR,Flash Bank 1 PCROP Start Address Register" hexmask.long.word 0x04 0.--15. 1. " PCROP1_STRT ,Bank 1 PCROP area start offset" line.long 0x08 "FLASH_PCROP1ER,Flash Bank 1 PCROP End Address Register" bitfld.long 0x08 31. " PCROP_RDP ,PCROP area preserved when RDP level decreased" "Not erased,Erased" hexmask.long.word 0x08 0.--15. 1. " PCROP1_END ,Bank 1 PCROP area end offset" line.long 0x0C "FLASH_WRP1AR,Flash Bank 1 WRP Area A Address Register" hexmask.long.byte 0x0C 16.--23. 0x01 " WRP1A_END ,Bank 1 WRP first area A end offset" hexmask.long.byte 0x0C 0.--7. 1. " WRP1A_STRT ,Bank 1 WRP first area A start offset" line.long 0x10 "FLASH_WRP1BR,Flash Bank 1 WRP Area B Address Register" hexmask.long.byte 0x10 16.--23. 0x01 " WRP1B_END ,Bank 1 WRP first area B end offset" hexmask.long.byte 0x10 0.--7. 1. " WRP1B_STRT ,Bank 1 WRP first area B start offset" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) group.long 0x44++0x0F line.long 0x00 "FLASH_PCROP2SR,Flash Bank 2 PCROP Start Address Register" hexmask.long.word 0x00 0.--15. 1. " PCROP2_STRT ,Bank 2 PCROP area start offset" line.long 0x04 "FLASH_PCROP2ER,Flash Bank 2 PCROP End Address Register" hexmask.long.word 0x04 0.--15. 1. " PCROP2_END ,Bank 2 PCROP area end offset" line.long 0x08 "FLASH_WRP2AR,Flash Bank 2 WRP Area A Address Register" hexmask.long.byte 0x08 16.--23. 0x01 " WRP2A_END ,Bank 1 WRP first area A end offset" hexmask.long.byte 0x08 0.--7. 1. " WRP2A_STRT ,Bank 1 WRP first area A start offset" line.long 0x0C "FLASH_WRP2BR,Flash Bank 2 WRP Area B Address Register" hexmask.long.byte 0x0C 16.--23. 0x01 " WRP2B_END ,Bank 1 WRP first area B end offset" hexmask.long.byte 0x0C 0.--7. 1. " WRP2B_STRT ,Bank 1 WRP first area B start offset" endif width 0x0B tree.end tree "FW (Firewall)" base ad:0x40011C00 width 11. group.long 0x00++0x17 line.long 0x00 "FW_CSSA,Code Segment Start Address Register" hexmask.long.word 0x00 8.--23. 0x01 " ADD ,Code segment start address" line.long 0x04 "FW_CSL,Code Segment Length Register" hexmask.long.word 0x04 8.--21. 1. " LENG ,Code segment length" line.long 0x08 "FW_NVDSSA,Non-volatile Data Segment Start Address Register" hexmask.long.word 0x08 8.--23. 0x01 " ADD ,Non-volatile data segment start address" line.long 0x0C "FW_NVDSL,Non-volatile Data Segment Length Register" hexmask.long.word 0x0C 8.--21. 1. " LENG ,Non-volatile data segment length" line.long 0x10 "FW_VDSSA,Volatile Data Segment Start Address Register" sif (cpu()=="STM32L496*")||(cpu()=="STM32L4A6*") hexmask.long.tbyte 0x10 6.--17. 0x40 " ADD ,Volatile data segment start address" else hexmask.long.tbyte 0x10 6.--16. 0x40 " ADD ,Volatile data segment start address" endif line.long 0x14 "FW_VDSL,Volatile Data Segment Length Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) hexmask.long.word 0x14 6.--17. 1. " LENG ,Volatile data segment length" else hexmask.long.word 0x14 6.--16. 1. " LENG ,Volatile data segment length" endif group.long 0x20++0x03 line.long 0x00 "FW_CR,Configuration Register" bitfld.long 0x00 2. " VDE ,Volatile data execution" "Not executed,Executed" bitfld.long 0x00 1. " VDS ,Volatile data shared" "Not shared,Shared" bitfld.long 0x00 0. " FPA ,Firewall prearm" "SysRes generated,Firewall closed" width 0x0B tree.end tree "PWR (Power control)" base ad:0x40007000 width 11. if (((per.l(ad:0x40007000))&0x4000)==0x0) group.long 0x00++0x03 line.long 0x00 "PWR_CR1,Power control register 1" bitfld.long 0x00 14. " LPR ,Low-power run" "MR,LPR" bitfld.long 0x00 9.--10. " VOS ,Voltage scaling range selection" ",Range1,Range2,?..." bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LPMS ,Low-power mode selection" "Stop 0,Stop 1,Stop 2,Standby,Shutdown,Shutdown,Shutdown,Shutdown" else group.long 0x00++0x03 line.long 0x00 "PWR_CR1,Power control register 1" bitfld.long 0x00 14. " LPR ,Low-power run" "MR,LPR" bitfld.long 0x00 9.--10. " VOS ,Voltage scaling range selection" ",Range1,Range2,?..." bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LPMS ,Low-power mode selection" "Stop 0,Stop 1,,Standby,Shutdown,Shutdown,Shutdown,Shutdown" endif sif (cpuis("STM32L4?5*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) if (((per.l(ad:0x40010000+0x1C))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 10. " USV ,VDDUSB USB supply valid" "Not valid,Valid" bitfld.long 0x00 9. " IOSV ,VDDIO2 Independent I/Os supply valid" "Not valid,Valid" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PVME2 ,Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" "Disabled,Enabled" bitfld.long 0x00 4. " PVME1 ,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "Disabled,Enabled" rbitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" rbitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 10. " USV ,VDDUSB USB supply valid" "Not valid,Valid" bitfld.long 0x00 9. " IOSV ,VDDIO2 Independent I/Os supply valid" "Not valid,Valid" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PVME2 ,Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" "Disabled,Enabled" bitfld.long 0x00 4. " PVME1 ,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "Disabled,Enabled" bitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" bitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" endif elif (cpuis("STM32L4?3*"))||(cpuis("STM32L4?2*")) if (((per.l(ad:0x40010000+0x1C))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 10. " USV ,VDDUSB USB supply valid" "Not valid,Valid" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" bitfld.long 0x00 4. " PVME1 ,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "Disabled,Enabled" textline " " rbitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" rbitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 10. " USV ,VDDUSB USB supply valid" "Not valid,Valid" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" bitfld.long 0x00 4. " PVME1 ,Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" bitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" endif elif (cpuis("STM32L431*"))||(cpuis("STM32L451*")) if (((per.l(ad:0x40010000+0x1C))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" rbitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" rbitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" bitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" bitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" endif elif (cpuis("STM32L471*")) if (((per.l(ad:0x40010000+0x1C))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 9. " IOSV ,VDDIO2 Independent I/Os supply valid" "Not valid,Valid" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PVME2 ,Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" "Disabled,Enabled" rbitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" rbitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "PWR_CR2,Power control register 2" bitfld.long 0x00 9. " IOSV ,VDDIO2 Independent I/Os supply valid" "Not valid,Valid" bitfld.long 0x00 7. " PVME4 ,Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V" "Disabled,Enabled" bitfld.long 0x00 6. " PVME3 ,Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PVME2 ,Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V" "Disabled,Enabled" bitfld.long 0x00 1.--3. " PLS ,Power voltage detector level selection" "2.0V,2.2V,2.4V,2.5V,2.6V,2.8V,2.9V,PVD_IN" bitfld.long 0x00 0. " PVDE ,Power voltage detector enable" "Disabled,Enabled" endif endif group.long 0x08++0x07 line.long 0x00 "PWR_CR3,Power control register 3" bitfld.long 0x00 15. " EIWUL ,Enable internal wakeup line" "Disabled,Enabled" bitfld.long 0x00 10. " APC ,Apply pull-up and pull-down configuration" "Not applied,Applied" bitfld.long 0x00 8. " RRS ,SRAM2 retention in Standby mode" "Off,Pow by LPR" bitfld.long 0x00 4. " EWUP5 ,Enable Wakeup pin WKUP5" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EWUP4 ,Enable Wakeup pin WKUP4" "Disabled,Enabled" bitfld.long 0x00 2. " EWUP3 ,Enable Wakeup pin WKUP3" "Disabled,Enabled" bitfld.long 0x00 1. " EWUP2 ,Enable Wakeup pin WKUP2" "Disabled,Enabled" bitfld.long 0x00 0. " EWUP1 ,Enable Wakeup pin WKUP1" "Disabled,Enabled" line.long 0x04 "PWR_CR4,Power control register 4" bitfld.long 0x04 9. " VBRS ,VBAT battery charging resistor selection" "5 kOhms,1.5 kOhms" bitfld.long 0x04 8. " VBE ,VBAT battery charging enable" "Disabled,Enabled" bitfld.long 0x04 4. " WP5 ,Wakeup pin WKUP5 polarity" "High,Low" bitfld.long 0x04 3. " WP4 ,Wakeup pin WKUP4 polarity" "High,Low" textline " " bitfld.long 0x04 2. " WP3 ,Wakeup pin WKUP3 polarity" "High,Low" bitfld.long 0x04 1. " WP2 ,Wakeup pin WKUP2 polarity" "High,Low" bitfld.long 0x04 0. " WP1 ,Wakeup pin WKUP1 polarity" "High,Low" rgroup.long 0x10++0x07 line.long 0x00 "PWR_SR1,Power status register 1" bitfld.long 0x00 15. " WUFI ,Wakeup flag internal" "No wakeup,Wakeup" bitfld.long 0x00 8. " SBF ,Standby flag" "No standby,Standby" bitfld.long 0x00 4. " WUF5 ,Wakeup flag 5" "No wakeup,Wakeup" bitfld.long 0x00 3. " WUF4 ,Wakeup flag 4" "No wakeup,Wakeup" textline " " bitfld.long 0x00 2. " WUF3 ,Wakeup flag 3" "No wakeup,Wakeup" bitfld.long 0x00 1. " WUF2 ,Wakeup flag 2" "No wakeup,Wakeup" bitfld.long 0x00 0. " WUF1 ,Wakeup flag 1" "No wakeup,Wakeup" sif (cpuis("STM32L4?5*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) rgroup.long 0x14++0x03 line.long 0x00 "PWR_SR2,Power status register 2" bitfld.long 0x00 15. " PVMO4 ,Peripheral voltage monitoring output: VDDA vs. 2.2 V" "Above PVM4,Below PVM4" bitfld.long 0x00 14. " PVMO3 ,Peripheral voltage monitoring output: VDDA vs. 1.62 V" "Above PVM3,Below PVM4" bitfld.long 0x00 13. " PVMO2 ,Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" "Above PVM2,Below PVM4" bitfld.long 0x00 12. " PVMO1 ,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "Above PVM1,Below PVM4" textline " " bitfld.long 0x00 11. " PVDO ,Power voltage detector output" "Above PVD,Below PVD" bitfld.long 0x00 10. " VOSF ,Voltage scaling flag" "Ready,Changing" bitfld.long 0x00 9. " REGLPF ,Low-power regulator flag" "MR,LPR" bitfld.long 0x00 8. " REGLPS ,Low-power regulator started" "Not ready,Ready" elif (cpuis("STM32L4?3*"))||(cpuis("STM32L432KC"))||(cpuis("STM32L442KC"))||(cpuis("STM32L451*")) rgroup.long 0x14++0x03 line.long 0x00 "PWR_SR2,Power status register 2" bitfld.long 0x00 15. " PVMO4 ,Peripheral voltage monitoring output: VDDA vs. 2.2 V" "Above PVM4,Below PVM4" bitfld.long 0x00 14. " PVMO3 ,Peripheral voltage monitoring output: VDDA vs. 1.62 V" "Above PVM3,Below PVM4" bitfld.long 0x00 12. " PVMO1 ,Peripheral voltage monitoring output: VDDUSB vs. 1.2 V" "Above PVM1,Below PVM4" bitfld.long 0x00 11. " PVDO ,Power voltage detector output" "Above PVD,Below PVD" textline " " bitfld.long 0x00 10. " VOSF ,Voltage scaling flag" "Ready,Changing" bitfld.long 0x00 9. " REGLPF ,Low-power regulator flag" "MR,LPR" bitfld.long 0x00 8. " REGLPS ,Low-power regulator started" "Not ready,Ready" elif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*")) rgroup.long 0x14++0x03 line.long 0x00 "PWR_SR2,Power status register 2" bitfld.long 0x00 15. " PVMO4 ,Peripheral voltage monitoring output: VDDA vs. 2.2 V" "Above PVM4,Below PVM4" bitfld.long 0x00 14. " PVMO3 ,Peripheral voltage monitoring output: VDDA vs. 1.62 V" "Above PVM3,Below PVM4" bitfld.long 0x00 11. " PVDO ,Power voltage detector output" "Above PVD,Below PVD" bitfld.long 0x00 10. " VOSF ,Voltage scaling flag" "Ready,Changing" textline " " bitfld.long 0x00 9. " REGLPF ,Low-power regulator flag" "MR,LPR" bitfld.long 0x00 8. " REGLPS ,Low-power regulator started" "Not ready,Ready" elif (cpuis("STM32L471*")) rgroup.long 0x14++0x03 line.long 0x00 "PWR_SR2,Power status register 2" bitfld.long 0x00 15. " PVMO4 ,Peripheral voltage monitoring output: VDDA vs. 2.2 V" "Above PVM4,Below PVM4" bitfld.long 0x00 14. " PVMO3 ,Peripheral voltage monitoring output: VDDA vs. 1.62 V" "Above PVM3,Below PVM4" bitfld.long 0x00 13. " PVMO2 ,Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V" "Above PVM2,Below PVM4" bitfld.long 0x00 11. " PVDO ,Power voltage detector output" "Above PVD,Below PVD" textline " " bitfld.long 0x00 10. " VOSF ,Voltage scaling flag" "Ready,Changing" bitfld.long 0x00 9. " REGLPF ,Low-power regulator flag" "MR,LPR" bitfld.long 0x00 8. " REGLPS ,Low-power regulator started" "Not ready,Ready" endif wgroup.long 0x18++0x03 line.long 0x00 "PWR_SCR,Power status clear register" bitfld.long 0x00 8. " CSBF ,Clear standby flag" "No effect,Clear" bitfld.long 0x00 4. " CWUF5 ,Clear wakeup flag 5" "No effect,Clear" bitfld.long 0x00 3. " CWUF4 ,Clear wakeup flag 4" "No effect,Clear" bitfld.long 0x00 2. " CWUF3 ,Clear wakeup flag 3" "No effect,Clear" textline " " bitfld.long 0x00 1. " CWUF2 ,Clear wakeup flag 2" "No effect,Clear" bitfld.long 0x00 0. " CWUF1 ,Clear wakeup flag 1" "No effect,Clear" sif (cpuis("STM32L431*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*"))||(cpuis("STM32L451*")) group.long 0x20++0x07 line.long 0x00 "PWR_PUCRA,Power Port A pull-up control register" bitfld.long 0x00 15. " PU[15] ,Port A pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x00 13. " PU[13] ,Port A pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x00 12. " PU[12] ,Port A pull-up bit 12" "No pull-up,Pull-up" bitfld.long 0x00 11. " PU[11] ,Port A pull-up bit 11" "No pull-up,Pull-up" textline " " bitfld.long 0x00 10. " PU[10] ,Port A pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port A pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port A pull-up bit 8" "No pull-up,Pull-up" bitfld.long 0x00 7. " PU[7] ,Port A pull-up bit 7" "No pull-up,Pull-up" textline " " bitfld.long 0x00 6. " PU[6] ,Port A pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port A pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port A pull-up bit 4" "No pull-up,Pull-up" bitfld.long 0x00 3. " PU[3] ,Port A pull-up bit 3" "No pull-up,Pull-up" textline " " bitfld.long 0x00 2. " PU[2] ,Port A pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port A pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port A pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRA,Power Port A pull-down control register" bitfld.long 0x04 14. " PD[14] ,Port A pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x04 12. " PD[12] ,Port A pull-down bit 12" "No pull-down,Pull-down" bitfld.long 0x04 11. " PD[11] ,Port A pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x04 10. " PD[10] ,Port A pull-down bit 10" "No pull-down,Pull-down" textline " " bitfld.long 0x04 9. " PD[9] ,Port A pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x04 8. " PD[8] ,Port A pull-down bit 8" "No pull-down,Pull-down" bitfld.long 0x04 7. " PD[7] ,Port A pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x04 6. " PD[6] ,Port A pull-down bit 6" "No pull-down,Pull-down" textline " " bitfld.long 0x04 5. " PD[5] ,Port A pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x04 4. " PD[4] ,Port A pull-down bit 4" "No pull-down,Pull-down" bitfld.long 0x04 3. " PD[3] ,Port A pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 2. " PD[2] ,Port A pull-down bit 2" "No pull-down,Pull-down" textline " " bitfld.long 0x04 1. " PD[1] ,Port A pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port A pull-down bit 0" "No pull-down,Pull-down" else group.long 0x20++0x07 line.long 0x00 "PWR_PUCRA,Power Port A pull-up control register" bitfld.long 0x00 15. " PU[15] ,Port A pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x00 14. " PU[14] ,Port A pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x00 13. " PU[13] ,Port A pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x00 12. " PU[12] ,Port A pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x00 11. " PU[11] ,Port A pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x00 10. " PU[10] ,Port A pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port A pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port A pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x00 7. " PU[7] ,Port A pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x00 6. " PU[6] ,Port A pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port A pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port A pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x00 3. " PU[3] ,Port A pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 2. " PU[2] ,Port A pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port A pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port A pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRA,Power Port A pull-down control register" bitfld.long 0x04 15. " PD[15] ,Port A pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x04 14. " PD[14] ,Port A pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x04 13. " PD[13] ,Port A pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x04 12. " PD[12] ,Port A pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x04 11. " PD[11] ,Port A pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x04 10. " PD[10] ,Port A pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x04 9. " PD[9] ,Port A pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x04 8. " PD[8] ,Port A pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x04 7. " PD[7] ,Port A pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x04 6. " PD[6] ,Port A pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x04 5. " PD[5] ,Port A pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x04 4. " PD[4] ,Port A pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x04 3. " PD[3] ,Port A pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 2. " PD[2] ,Port A pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x04 1. " PD[1] ,Port A pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port A pull-down bit 0" "No pull-down,Pull-down" endif group.long 0x28++0x03 line.long 0x00 "PWR_PUCRB,Power Port B pull-up control register" bitfld.long 0x00 15. " PU[15] ,Port B pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x00 14. " PU[14] ,Port B pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x00 13. " PU[13] ,Port B pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x00 12. " PU[12] ,Port B pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x00 11. " PU[11] ,Port B pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x00 10. " PU[10] ,Port B pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port B pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port B pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x00 7. " PU[7] ,Port B pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x00 6. " PU[6] ,Port B pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port B pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port B pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x00 3. " PU[3] ,Port B pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 2. " PU[2] ,Port B pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port B pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port B pull-up bit 0" "No pull-up,Pull-up" sif (cpuis("STM32L431*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*"))||(cpuis("STM32L451*")) group.long 0x2C++0x03 line.long 0x00 "PWR_PDCRB,Power Port B pull-down control register" bitfld.long 0x00 15. " PD[15] ,Port B pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x00 14. " PD[14] ,Port B pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x00 13. " PD[13] ,Port B pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x00 12. " PD[12] ,Port B pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x00 11. " PD[11] ,Port B pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x00 10. " PD[10] ,Port B pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x00 9. " PD[9] ,Port B pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x00 8. " PD[8] ,Port B pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x00 7. " PD[7] ,Port B pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x00 6. " PD[6] ,Port B pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x00 5. " PD[5] ,Port B pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x00 3. " PD[3] ,Port B pull-down bit 3" "No pull-down,Pull-down" textline " " bitfld.long 0x00 2. " PD[2] ,Port B pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x00 1. " PD[1] ,Port B pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x00 0. " PD[0] ,Port B pull-down bit 0" "No pull-down,Pull-down" else group.long 0x2C++0x03 line.long 0x00 "PWR_PDCRB,Power Port B pull-down control register" bitfld.long 0x00 15. " PD[15] ,Port B pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x00 14. " PD[14] ,Port B pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x00 13. " PD[13] ,Port B pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x00 12. " PD[12] ,Port B pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x00 11. " PD[11] ,Port B pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x00 10. " PD[10] ,Port B pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x00 9. " PD[9] ,Port B pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x00 8. " PD[8] ,Port B pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x00 7. " PD[7] ,Port B pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x00 6. " PD[6] ,Port B pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x00 5. " PD[5] ,Port B pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x00 4. " PD[4] ,Port B pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x00 3. " PD[3] ,Port B pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x00 2. " PD[2] ,Port B pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x00 1. " PD[1] ,Port B pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x00 0. " PD[0] ,Port B pull-down bit 0" "No pull-down,Pull-down" endif group.long 0x30++0x17 line.long 0x00 "PWR_PUCRC,Power Port C pull-up control register" bitfld.long 0x00 15. " PU[15] ,Port C pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x00 14. " PU[14] ,Port C pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x00 13. " PU[13] ,Port C pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x00 12. " PU[12] ,Port C pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x00 11. " PU[11] ,Port C pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x00 10. " PU[10] ,Port C pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port C pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port C pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x00 7. " PU[7] ,Port C pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x00 6. " PU[6] ,Port C pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port C pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port C pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x00 3. " PU[3] ,Port C pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 2. " PU[2] ,Port C pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port C pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port C pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRC,Power Port C pull-down control register" bitfld.long 0x04 15. " PD[15] ,Port C pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x04 14. " PD[14] ,Port C pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x04 13. " PD[13] ,Port C pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x04 12. " PD[12] ,Port C pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x04 11. " PD[11] ,Port C pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x04 10. " PD[10] ,Port C pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x04 9. " PD[9] ,Port C pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x04 8. " PD[8] ,Port C pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x04 7. " PD[7] ,Port C pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x04 6. " PD[6] ,Port C pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x04 5. " PD[5] ,Port C pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x04 4. " PD[4] ,Port C pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x04 3. " PD[3] ,Port C pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 2. " PD[2] ,Port C pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x04 1. " PD[1] ,Port C pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port C pull-down bit 0" "No pull-down,Pull-down" line.long 0x08 "PWR_PUCRD,Power Port D pull-up control register" bitfld.long 0x08 15. " PU[15] ,Port D pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x08 14. " PU[14] ,Port D pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x08 13. " PU[13] ,Port D pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x08 12. " PU[12] ,Port D pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x08 11. " PU[11] ,Port D pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x08 10. " PU[10] ,Port D pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x08 9. " PU[9] ,Port D pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x08 8. " PU[8] ,Port D pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x08 7. " PU[7] ,Port D pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x08 6. " PU[6] ,Port D pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x08 5. " PU[5] ,Port D pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x08 4. " PU[4] ,Port D pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x08 3. " PU[3] ,Port D pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x08 2. " PU[2] ,Port D pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x08 1. " PU[1] ,Port D pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x08 0. " PU[0] ,Port D pull-up bit 0" "No pull-up,Pull-up" line.long 0x0C "PWR_PDCRD,Power Port D pull-down control register" bitfld.long 0x0C 15. " PD[15] ,Port D pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x0C 14. " PD[14] ,Port D pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x0C 13. " PD[13] ,Port D pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x0C 12. " PD[12] ,Port D pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x0C 11. " PD[11] ,Port D pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x0C 10. " PD[10] ,Port D pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x0C 9. " PD[9] ,Port D pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x0C 8. " PD[8] ,Port D pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x0C 7. " PD[7] ,Port D pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x0C 6. " PD[6] ,Port D pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x0C 5. " PD[5] ,Port D pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x0C 4. " PD[4] ,Port D pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x0C 3. " PD[3] ,Port D pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x0C 2. " PD[2] ,Port D pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x0C 1. " PD[1] ,Port D pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x0C 0. " PD[0] ,Port D pull-down bit 0" "No pull-down,Pull-down" line.long 0x10 "PWR_PUCRE,Power Port E pull-up control register" bitfld.long 0x10 15. " PU[15] ,Port E pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x10 14. " PU[14] ,Port E pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x10 13. " PU[13] ,Port E pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x10 12. " PU[12] ,Port E pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x10 11. " PU[11] ,Port E pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x10 10. " PU[10] ,Port E pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x10 9. " PU[9] ,Port E pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x10 8. " PU[8] ,Port E pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x10 7. " PU[7] ,Port E pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x10 6. " PU[6] ,Port E pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x10 5. " PU[5] ,Port E pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x10 4. " PU[4] ,Port E pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x10 3. " PU[3] ,Port E pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x10 2. " PU[2] ,Port E pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x10 1. " PU[1] ,Port E pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x10 0. " PU[0] ,Port E pull-up bit 0" "No pull-up,Pull-up" line.long 0x14 "PWR_PDCRE,Power Port E pull-down control register" bitfld.long 0x14 15. " PD[15] ,Port E pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x14 14. " PD[14] ,Port E pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x14 13. " PD[13] ,Port E pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x14 12. " PD[12] ,Port E pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x14 11. " PD[11] ,Port E pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x14 10. " PD[10] ,Port E pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x14 9. " PD[9] ,Port E pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x14 8. " PD[8] ,Port E pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x14 7. " PD[7] ,Port E pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x14 6. " PD[6] ,Port E pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x14 5. " PD[5] ,Port E pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x14 4. " PD[4] ,Port E pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x14 3. " PD[3] ,Port E pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x14 2. " PD[2] ,Port E pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x14 1. " PD[1] ,Port E pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x14 0. " PD[0] ,Port E pull-down bit 0" "No pull-down,Pull-down" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) group.long 0x48++0x0F line.long 0x00 "PWR_PUCRF,Power Port F pull-up control register" bitfld.long 0x00 15. " PU[15] ,Port F pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x00 14. " PU[14] ,Port F pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x00 13. " PU[13] ,Port F pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x00 12. " PU[12] ,Port F pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x00 11. " PU[11] ,Port F pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x00 10. " PU[10] ,Port F pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port F pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port F pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x00 7. " PU[7] ,Port F pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x00 6. " PU[6] ,Port F pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port F pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port F pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x00 3. " PU[3] ,Port F pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 2. " PU[2] ,Port F pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port F pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port F pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRF,Power Port F pull-down control register" bitfld.long 0x04 15. " PD[15] ,Port F pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x04 14. " PD[14] ,Port F pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x04 13. " PD[13] ,Port F pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x04 12. " PD[12] ,Port F pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x04 11. " PD[11] ,Port F pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x04 10. " PD[10] ,Port F pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x04 9. " PD[9] ,Port F pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x04 8. " PD[8] ,Port F pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x04 7. " PD[7] ,Port F pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x04 6. " PD[6] ,Port F pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x04 5. " PD[5] ,Port F pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x04 4. " PD[4] ,Port F pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x04 3. " PD[3] ,Port F pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 2. " PD[2] ,Port F pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x04 1. " PD[1] ,Port F pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port F pull-down bit 0" "No pull-down,Pull-down" line.long 0x08 "PWR_PUCRG,Power Port G pull-up control register" bitfld.long 0x08 15. " PU[15] ,Port G pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x08 14. " PU[14] ,Port G pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x08 13. " PU[13] ,Port G pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x08 12. " PU[12] ,Port G pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x08 11. " PU[11] ,Port G pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x08 10. " PU[10] ,Port G pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x08 9. " PU[9] ,Port G pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x08 8. " PU[8] ,Port G pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x08 7. " PU[7] ,Port G pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x08 6. " PU[6] ,Port G pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x08 5. " PU[5] ,Port G pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x08 4. " PU[4] ,Port G pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x08 3. " PU[3] ,Port G pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x08 2. " PU[2] ,Port G pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x08 1. " PU[1] ,Port G pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x08 0. " PU[0] ,Port G pull-up bit 0" "No pull-up,Pull-up" line.long 0x0C "PWR_PDCRG,Power Port G pull-down control register" bitfld.long 0x0C 15. " PD[15] ,Port G pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x0C 14. " PD[14] ,Port G pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x0C 13. " PD[13] ,Port G pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x0C 12. " PD[12] ,Port G pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x0C 11. " PD[11] ,Port G pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x0C 10. " PD[10] ,Port G pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x0C 9. " PD[9] ,Port G pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x0C 8. " PD[8] ,Port G pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x0C 7. " PD[7] ,Port G pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x0C 6. " PD[6] ,Port G pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x0C 5. " PD[5] ,Port G pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x0C 4. " PD[4] ,Port G pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x0C 3. " PD[3] ,Port G pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x0C 2. " PD[2] ,Port G pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x0C 1. " PD[1] ,Port G pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x0C 0. " PD[0] ,Port G pull-down bit 0" "No pull-down,Pull-down" endif group.long 0x58++0x07 line.long 0x00 "PWR_PUCRH,Power Port H pull-up control register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 15. " PU[15] ,Port H pull-up bit 15" "No pull-up,Pull-up" bitfld.long 0x00 14. " PU[14] ,Port H pull-up bit 14" "No pull-up,Pull-up" bitfld.long 0x00 13. " PU[13] ,Port H pull-up bit 13" "No pull-up,Pull-up" bitfld.long 0x00 12. " PU[12] ,Port H pull-up bit 12" "No pull-up,Pull-up" textline " " bitfld.long 0x00 11. " PU[11] ,Port H pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x00 10. " PU[10] ,Port H pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port H pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port H pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x00 7. " PU[7] ,Port H pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x00 6. " PU[6] ,Port H pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port H pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port H pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x00 3. " PU[3] ,Port H pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 2. " PU[2] ,Port H pull-up bit 2" "No pull-up,Pull-up" textline " " endif bitfld.long 0x00 1. " PU[1] ,Port H pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port H pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRH,Power Port H pull-down control register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x04 15. " PD[15] ,Port H pull-down bit 15" "No pull-down,Pull-down" bitfld.long 0x04 14. " PD[14] ,Port H pull-down bit 14" "No pull-down,Pull-down" bitfld.long 0x04 13. " PD[13] ,Port H pull-down bit 13" "No pull-down,Pull-down" bitfld.long 0x04 12. " PD[12] ,Port H pull-down bit 12" "No pull-down,Pull-down" textline " " bitfld.long 0x04 11. " PD[11] ,Port H pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x04 10. " PD[10] ,Port H pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x04 9. " PD[9] ,Port H pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x04 8. " PD[8] ,Port H pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x04 7. " PD[7] ,Port H pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x04 6. " PD[6] ,Port H pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x04 5. " PD[5] ,Port H pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x04 4. " PD[4] ,Port H pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x04 3. " PD[3] ,Port H pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 2. " PD[2] ,Port H pull-down bit 2" "No pull-down,Pull-down" textline " " endif bitfld.long 0x04 1. " PD[1] ,Port H pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port H pull-down bit 0" "No pull-down,Pull-down" else group.long 0x58++0x07 line.long 0x00 "PWR_PUCRH,Power Port H pull-up control register" bitfld.long 0x00 3. " PU[3] ,Port H pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port H pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port H pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRH,Power Port H pull-down control register" bitfld.long 0x04 3. " PD[3] ,Port H pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 1. " PD[1] ,Port H pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port H pull-down bit 0" "No pull-down,Pull-down" endif sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) group.long 0x60++0x07 line.long 0x00 "PWR_PUCRI,Power Port I pull-up control register" bitfld.long 0x00 11. " PU[11] ,Port I pull-up bit 11" "No pull-up,Pull-up" bitfld.long 0x00 10. " PU[10] ,Port I pull-up bit 10" "No pull-up,Pull-up" bitfld.long 0x00 9. " PU[9] ,Port I pull-up bit 9" "No pull-up,Pull-up" bitfld.long 0x00 8. " PU[8] ,Port I pull-up bit 8" "No pull-up,Pull-up" textline " " bitfld.long 0x00 7. " PU[7] ,Port I pull-up bit 7" "No pull-up,Pull-up" bitfld.long 0x00 6. " PU[6] ,Port I pull-up bit 6" "No pull-up,Pull-up" bitfld.long 0x00 5. " PU[5] ,Port I pull-up bit 5" "No pull-up,Pull-up" bitfld.long 0x00 4. " PU[4] ,Port I pull-up bit 4" "No pull-up,Pull-up" textline " " bitfld.long 0x00 3. " PU[3] ,Port I pull-up bit 3" "No pull-up,Pull-up" bitfld.long 0x00 2. " PU[2] ,Port I pull-up bit 2" "No pull-up,Pull-up" bitfld.long 0x00 1. " PU[1] ,Port I pull-up bit 1" "No pull-up,Pull-up" bitfld.long 0x00 0. " PU[0] ,Port I pull-up bit 0" "No pull-up,Pull-up" line.long 0x04 "PWR_PDCRI,Power Port I pull-down control register" bitfld.long 0x04 11. " PD[11] ,Port I pull-down bit 11" "No pull-down,Pull-down" bitfld.long 0x04 10. " PD[10] ,Port I pull-down bit 10" "No pull-down,Pull-down" bitfld.long 0x04 9. " PD[9] ,Port I pull-down bit 9" "No pull-down,Pull-down" bitfld.long 0x04 8. " PD[8] ,Port I pull-down bit 8" "No pull-down,Pull-down" textline " " bitfld.long 0x04 7. " PD[7] ,Port I pull-down bit 7" "No pull-down,Pull-down" bitfld.long 0x04 6. " PD[6] ,Port I pull-down bit 6" "No pull-down,Pull-down" bitfld.long 0x04 5. " PD[5] ,Port I pull-down bit 5" "No pull-down,Pull-down" bitfld.long 0x04 4. " PD[4] ,Port I pull-down bit 4" "No pull-down,Pull-down" textline " " bitfld.long 0x04 3. " PD[3] ,Port I pull-down bit 3" "No pull-down,Pull-down" bitfld.long 0x04 2. " PD[2] ,Port I pull-down bit 2" "No pull-down,Pull-down" bitfld.long 0x04 1. " PD[1] ,Port I pull-down bit 1" "No pull-down,Pull-down" bitfld.long 0x04 0. " PD[0] ,Port I pull-down bit 0" "No pull-down,Pull-down" endif width 0x0B tree.end tree "RCC (Reset and clock control)" base ad:0x40021000 width 17. sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) if (((per.l(ad:0x40021000))&0x10000)==0x0) group.long 0x00++0x03 line.long 0x00 "RCC_CR,Clock control register" rbitfld.long 0x00 29. " PLLSAI2RDY ,SAI2 PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 28. " PLLSAI2ON ,SAI2 PLL enable" "Disabled,Enabled" rbitfld.long 0x00 27. " PLLSAI1RDY ,SAI1 PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 26. " PLLSAI1ON ,SAI1 PLL enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 25. " PLLRDY ,Main PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 24. " PLLON ,Main PLL enable" "Disabled,Enabled" bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled" bitfld.long 0x00 18. " HSEBYP ,HSE crystal oscillator bypass" "Not bypassed,Bypassed" textline " " rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready" bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSIASFS ,HSI automatic start from Stop" "Not enabled,Enabled" rbitfld.long 0x00 10. " HSIRDY ,HSI clock ready flag" "Not ready,Ready" textline " " bitfld.long 0x00 9. " HSIKERON ,HSI always enable for peripheral kernels" "No effect,Forced ON" bitfld.long 0x00 8. " HSION ,HSI clock enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " MSIRANGE ,MSI clock ranges. Range/Freq" "0/100kHz,1/200kHz,2/400kHz,3/800kHz,4/1MHz,5/2MHz,6/4MHz,7/8MHz,8/16MHz,9/24MHz,10/32MHz,11/48MHz,?..." bitfld.long 0x00 3. " MSIRGSEL ,MSI clock range selection" "MSISRANGE,MSIRANGE" textline " " bitfld.long 0x00 2. " MSIPLLEN ,MSI clock PLL enable" "Disabled,Enabled" rbitfld.long 0x00 1. " MSIRDY ,MSI clock ready flag" "Not ready,Ready" bitfld.long 0x00 0. " MSION ,MSI clock enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "RCC_CR,Clock control register" rbitfld.long 0x00 29. " PLLSAI2RDY ,SAI2 PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 28. " PLLSAI2ON ,SAI2 PLL enable" "Disabled,Enabled" rbitfld.long 0x00 27. " PLLSAI1RDY ,SAI1 PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 26. " PLLSAI1ON ,SAI1 PLL enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 25. " PLLRDY ,Main PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 24. " PLLON ,Main PLL enable" "Disabled,Enabled" bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled" rbitfld.long 0x00 18. " HSEBYP ,HSE crystal oscillator bypass" "Not bypassed,Bypassed" textline " " rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready" bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " HSIASFS ,HSI automatic start from Stop" "Not enabled,Enabled" rbitfld.long 0x00 10. " HSIRDY ,HSI clock ready flag" "Not ready,Ready" textline " " bitfld.long 0x00 9. " HSIKERON ,HSI always enable for peripheral kernels" "No effect,Forced ON" bitfld.long 0x00 8. " HSION ,HSI clock enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " MSIRANGE ,MSI clock ranges. Range/Freq" "0/100kHz,1/200kHz,2/400kHz,3/800kHz,4/1MHz,5/2MHz,6/4MHz,7/8MHz,8/16MHz,9/24MHz,10/32MHz,11/48MHz,?..." bitfld.long 0x00 3. " MSIRGSEL ,MSI clock range selection" "MSISRANGE,MSIRANGE" textline " " bitfld.long 0x00 2. " MSIPLLEN ,MSI clock PLL enable" "Disabled,Enabled" rbitfld.long 0x00 1. " MSIRDY ,MSI clock ready flag" "Not ready,Ready" bitfld.long 0x00 0. " MSION ,MSI clock enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40021000))&0x10000)==0x0) group.long 0x00++0x03 line.long 0x00 "RCC_CR,Clock control register" rbitfld.long 0x00 27. " PLLSAI1RDY ,SAI1 PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 26. " PLLSAI1ON ,SAI1 PLL enable" "Disabled,Enabled" rbitfld.long 0x00 25. " PLLRDY ,Main PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 24. " PLLON ,Main PLL enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled" bitfld.long 0x00 18. " HSEBYP ,HSE crystal oscillator bypass" "Not bypassed,Bypassed" rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready" bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HSIASFS ,HSI automatic start from Stop" "Not enabled,Enabled" rbitfld.long 0x00 10. " HSIRDY ,HSI clock ready flag" "Not ready,Ready" bitfld.long 0x00 9. " HSIKERON ,HSI always enable for peripheral kernels" "No effect,Forced ON" bitfld.long 0x00 8. " HSION ,HSI clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " MSIRANGE ,MSI clock ranges. Range/Freq" "0/100kHz,1/200kHz,2/400kHz,3/800kHz,4/1MHz,5/2MHz,6/4MHz,7/8MHz,8/16MHz,9/24MHz,10/32MHz,11/48MHz,?..." bitfld.long 0x00 3. " MSIRGSEL ,MSI clock range selection" "MSISRANGE,MSIRANGE" bitfld.long 0x00 2. " MSIPLLEN ,MSI clock PLL enable" "Disabled,Enabled" rbitfld.long 0x00 1. " MSIRDY ,MSI clock ready flag" "Not ready,Ready" textline " " bitfld.long 0x00 0. " MSION ,MSI clock enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "RCC_CR,Clock control register" rbitfld.long 0x00 27. " PLLSAI1RDY ,SAI1 PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 26. " PLLSAI1ON ,SAI1 PLL enable" "Disabled,Enabled" rbitfld.long 0x00 25. " PLLRDY ,Main PLL clock ready flag" "Unlocked,Locked" bitfld.long 0x00 24. " PLLON ,Main PLL enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled" rbitfld.long 0x00 18. " HSEBYP ,HSE crystal oscillator bypass" "Not bypassed,Bypassed" rbitfld.long 0x00 17. " HSERDY ,HSE clock ready flag" "Not ready,Ready" bitfld.long 0x00 16. " HSEON ,HSE clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HSIASFS ,HSI automatic start from Stop" "Not enabled,Enabled" rbitfld.long 0x00 10. " HSIRDY ,HSI clock ready flag" "Not ready,Ready" bitfld.long 0x00 9. " HSIKERON ,HSI always enable for peripheral kernels" "No effect,Forced ON" bitfld.long 0x00 8. " HSION ,HSI clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--7. " MSIRANGE ,MSI clock ranges. Range/Freq" "0/100kHz,1/200kHz,2/400kHz,3/800kHz,4/1MHz,5/2MHz,6/4MHz,7/8MHz,8/16MHz,9/24MHz,10/32MHz,11/48MHz,?..." bitfld.long 0x00 3. " MSIRGSEL ,MSI clock range selection" "MSISRANGE,MSIRANGE" bitfld.long 0x00 2. " MSIPLLEN ,MSI clock PLL enable" "Disabled,Enabled" rbitfld.long 0x00 1. " MSIRDY ,MSI clock ready flag" "Not ready,Ready" textline " " bitfld.long 0x00 0. " MSION ,MSI clock enable" "Disabled,Enabled" endif endif group.long 0x04++0x03 line.long 0x00 "RCC_ICSCR,Internal clock sources calibration register" sif (!cpuis("STM32L496*"))&&(!cpuis("STM32L4A6*")) bitfld.long 0x00 24.--28. " HSITRIM ,HSI clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " endif hexmask.long.byte 0x00 16.--23. 1. " HSICAL ,HSI clock calibration" hexmask.long.byte 0x00 8.--15. 1. " MSITRIM ,MSI clock trimming" hexmask.long.byte 0x00 0.--7. 1. " MSICAL ,MSI clock calibration" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) if (((per.l(ad:0x40021000))&0x90000)==0x90000)&&(((per.l(ad:0x40021000+0x08))&0x0F)==(0x08||0x02)) group.long 0x08++0x03 line.long 0x00 "RCC_CFGR,Clock configuration register" bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "/1,/2,/4,/8,/16,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 24.--27. " MCOSEL ,Microcontroller clock output" "Disabled,SYSCLK,MSI,HSI16,HSE,Main PLL,LSI,LSE,HSI48,?..." else bitfld.long 0x00 24.--26. " MCOSEL ,Microcontroller clock output" "Disabled,SYSCLK,MSI,HSI,HSE,Main PLL,LSI,LSE" endif textline " " bitfld.long 0x00 15. " STOPWUCK ,Wakeup from Stop and CSS backup clock selection" "MSI,HSI" bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" bitfld.long 0x00 8.--10. " PPRE1 ,APB low-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "/1,/1,/1,/1,/1,/1,/1,/1,/2,/4,/8,/16,/64,/128,/256,/512" textline " " rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "MSI,HSI,HSE,PLL" bitfld.long 0x00 0.--1. " SW ,System clock switch" "MSI,HSI,HSE,PLL" else group.long 0x08++0x03 line.long 0x00 "RCC_CFGR,Clock configuration register" bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "/1,/2,/4,/8,/16,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 24.--27. " MCOSEL ,Microcontroller clock output" "Disabled,SYSCLK,MSI,HSI16,HSE,Main PLL,LSI,LSE,HSI48,?..." else bitfld.long 0x00 24.--26. " MCOSEL ,Microcontroller clock output" "Disabled,SYSCLK,MSI,HSI,HSE,Main PLL,LSI,LSE" endif textline " " rbitfld.long 0x00 15. " STOPWUCK ,Wakeup from Stop and CSS backup clock selection" "MSI,HSI" bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" bitfld.long 0x00 8.--10. " PPRE1 ,APB low-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "/1,/1,/1,/1,/1,/1,/1,/1,/2,/4,/8,/16,/64,/128,/256,/512" textline " " rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "MSI,HSI,HSE,PLL" bitfld.long 0x00 0.--1. " SW ,System clock switch" "MSI,HSI,HSE,PLL" endif else if (((per.l(ad:0x40021000))&0x90000)==0x90000)&&(((per.l(ad:0x40021000+0x08))&0x0F)==(0x08||0x02)) group.long 0x08++0x03 line.long 0x00 "RCC_CFGR,Clock configuration register" bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "/1,/2,/4,/8,/16,?..." bitfld.long 0x00 24.--27. " MCOSEL ,Microcontroller clock output" "Disabled,SYSCLK,MSI,HSI,HSE,Main PLL,LSI,LSE,Internal HSI48,?..." rbitfld.long 0x00 15. " STOPWUCK ,Wakeup from Stop and CSS backup clock selection" "MSI,HSI" bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" textline " " bitfld.long 0x00 8.--10. " PPRE1 ,APB low-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "/1,/1,/1,/1,/1,/1,/1,/1,/2,/4,/8,/16,/64,/128,/256,/512" textline " " rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "MSI,HSI16,HSE,PLL" bitfld.long 0x00 0.--1. " SW ,System clock switch" "MSI,HSI16,HSE,PLL" else group.long 0x08++0x03 line.long 0x00 "RCC_CFGR,Clock configuration register" bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "/1,/2,/4,/8,/16,?..." bitfld.long 0x00 24.--27. " MCOSEL ,Microcontroller clock output" "Disabled,SYSCLK,MSI,HSI,HSE,Main PLL,LSI,LSE,Internal HSI48,?..." bitfld.long 0x00 15. " STOPWUCK ,Wakeup from Stop and CSS backup clock selection" "MSI,HSI" bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" textline " " bitfld.long 0x00 8.--10. " PPRE1 ,APB low-speed prescaler" "/1,/1,/1,/1,/2,/4,/8,/16" bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "/1,/1,/1,/1,/1,/1,/1,/1,/2,/4,/8,/16,/64,/128,/256,/512" textline " " rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "MSI,HSI16,HSE,PLL" bitfld.long 0x00 0.--1. " SW ,System clock switch" "MSI,HSI16,HSE,PLL" endif endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) if (((per.l(ad:0x40021000))&0x15000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "RCC_PLLCFGR,PLL configuration register" bitfld.long 0x00 25.--26. " PLLR ,Main PLL division factor for PLLCLK (system clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLREN ,Main PLL PLLCLK output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " PLLQ ,Main PLL division factor for PLLUSB1CLK(48 MHz clock)" "/2,/4,/6,/8" bitfld.long 0x00 20. " PLLQEN ,Main PLL PLLUSB1CLK output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PLLP ,Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLPEN ,Main PLL PLLSAI3CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLN ,Main PLL multiplication factor for VCO" bitfld.long 0x00 4.--6. " PLLM ,Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " bitfld.long 0x00 0.--1. " PLLSRC ,Main PLL, PLLSAI1 and PLLSAI2 entry clock source" "No clock,MSI,HSI,HSE" elif (((per.l(ad:0x40021000))&0x1000000)==0x0000000) group.long 0x0C++0x03 line.long 0x00 "RCC_PLLCFGR,PLL configuration register" bitfld.long 0x00 25.--26. " PLLR ,Main PLL division factor for PLLCLK (system clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLREN ,Main PLL PLLCLK output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " PLLQ ,Main PLL division factor for PLLUSB1CLK(48 MHz clock)" "/2,/4,/6,/8" bitfld.long 0x00 20. " PLLQEN ,Main PLL PLLUSB1CLK output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PLLP ,Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLPEN ,Main PLL PLLSAI3CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLN ,Main PLL multiplication factor for VCO" bitfld.long 0x00 4.--6. " PLLM ,Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " rbitfld.long 0x00 0.--1. " PLLSRC ,Main PLL, PLLSAI1 and PLLSAI2 entry clock source" "No clock,MSI,HSI,HSE" else group.long 0x0C++0x03 line.long 0x00 "RCC_PLLCFGR,PLL configuration register" rbitfld.long 0x00 25.--26. " PLLR ,Main PLL division factor for PLLCLK (system clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLREN ,Main PLL PLLCLK output enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " PLLQ ,Main PLL division factor for PLLUSB1CLK(48 MHz clock)" "/2,/4,/6,/8" bitfld.long 0x00 20. " PLLQEN ,Main PLL PLLUSB1CLK output enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 17. " PLLP ,Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLPEN ,Main PLL PLLSAI3CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLN ,Main PLL multiplication factor for VCO" rbitfld.long 0x00 4.--6. " PLLM ,Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " rbitfld.long 0x00 0.--1. " PLLSRC ,Main PLL, PLLSAI1 and PLLSAI2 entry clock source" "No clock,MSI,HSI,HSE" endif else if (((per.l(ad:0x40021000))&0x5000000)==0x0000000) group.long 0x0C++0x03 line.long 0x00 "RCC_PLLCFGR,PLL configuration register" bitfld.long 0x00 27.--31. " PLLPDIV ,Main PLL division factor for PLLSAI2CLK" "PLLP,,VCO/2,VCO/3,VCO/4,VCO/5,VCO/6,VCO/7,VCO/8,VCO/9,VCO/10,VCO/11,VCO/12,VCO/13,VCO/14,VCO/15,VCO/16,VCO/17,VCO/18,VCO/19,VCO/20,VCO/21,VCO/22,VCO/23,VCO/24,VCO/25,VCO/26,VCO/27,VCO/28,VCO/29,VCO/30,VCO/31" bitfld.long 0x00 25.--26. " PLLR ,Main PLL division factor for PLLCLK (system clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLREN ,Main PLL PLLCLK output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " PLLQ ,Main PLL division factor for PLL48M1CLK(48 MHz clock)" "/2,/4,/6,/8" textline " " bitfld.long 0x00 20. " PLLQEN ,Main PLL PLL48M1CLK output enable" "Disabled,Enabled" bitfld.long 0x00 17. " PLLP ,Main PLL division factor for PLLSAI2CLK (SAI1 clock)" "/7,/17" bitfld.long 0x00 16. " PLLPEN ,Main PLL PLLSAI2CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLN ,Main PLL multiplication factor for VCO" textline " " bitfld.long 0x00 4.--6. " PLLM ,Division factor for the main PLL and audio PLL (PLLSAI1) input clock" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--1. " PLLSRC ,Main PLL and PLLSAI1 entry clock source" "No clock,MSI,HSI16,HSE" elif (((per.l(ad:0x40021000))&0x1000000)==0x0000000) group.long 0x0C++0x03 line.long 0x00 "RCC_PLLCFGR,PLL configuration register" bitfld.long 0x00 27.--31. " PLLPDIV ,Main PLL division factor for PLLSAI2CLK" "PLLP,,VCO/2,VCO/3,VCO/4,VCO/5,VCO/6,VCO/7,VCO/8,VCO/9,VCO/10,VCO/11,VCO/12,VCO/13,VCO/14,VCO/15,VCO/16,VCO/17,VCO/18,VCO/19,VCO/20,VCO/21,VCO/22,VCO/23,VCO/24,VCO/25,VCO/26,VCO/27,VCO/28,VCO/29,VCO/30,VCO/31" bitfld.long 0x00 25.--26. " PLLR ,Main PLL division factor for PLLCLK (system clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLREN ,Main PLL PLLCLK output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " PLLQ ,Main PLL division factor for PLL48M1CLK(48 MHz clock)" "/2,/4,/6,/8" textline " " bitfld.long 0x00 20. " PLLQEN ,Main PLL PLL48M1CLK output enable" "Disabled,Enabled" bitfld.long 0x00 17. " PLLP ,Main PLL division factor for PLLSAI2CLK (SAI1 clock)" "/7,/17" bitfld.long 0x00 16. " PLLPEN ,Main PLL PLLSAI2CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLN ,Main PLL multiplication factor for VCO" textline " " bitfld.long 0x00 4.--6. " PLLM ,Division factor for the main PLL and audio PLL (PLLSAI1) input clock" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 0.--1. " PLLSRC ,Main PLL and PLLSAI1 entry clock source" "No clock,MSI,HSI16,HSE" else group.long 0x0C++0x03 line.long 0x00 "RCC_PLLCFGR,PLL configuration register" bitfld.long 0x00 27.--31. " PLLPDIV ,Main PLL division factor for PLLSAI2CLK" "PLLP,,VCO/2,VCO/3,VCO/4,VCO/5,VCO/6,VCO/7,VCO/8,VCO/9,VCO/10,VCO/11,VCO/12,VCO/13,VCO/14,VCO/15,VCO/16,VCO/17,VCO/18,VCO/19,VCO/20,VCO/21,VCO/22,VCO/23,VCO/24,VCO/25,VCO/26,VCO/27,VCO/28,VCO/29,VCO/30,VCO/31" rbitfld.long 0x00 25.--26. " PLLR ,Main PLL division factor for PLLCLK (system clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLREN ,Main PLL PLLCLK output enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " PLLQ ,Main PLL division factor for PLL48M1CLK(48 MHz clock)" "/2,/4,/6,/8" textline " " bitfld.long 0x00 20. " PLLQEN ,Main PLL PLL48M1CLK output enable" "Disabled,Enabled" rbitfld.long 0x00 17. " PLLP ,Main PLL division factor for PLLSAI2CLK (SAI1 clock)" "/7,/17" bitfld.long 0x00 16. " PLLPEN ,Main PLL PLLSAI2CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLN ,Main PLL multiplication factor for VCO" textline " " rbitfld.long 0x00 4.--6. " PLLM ,Division factor for the main PLL and audio PLL (PLLSAI1) input clock" "/1,/2,/3,/4,/5,/6,/7,/8" rbitfld.long 0x00 0.--1. " PLLSRC ,Main PLL and PLLSAI1 entry clock source" "No clock,MSI,HSI16,HSE" endif endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) if (((per.l(ad:0x40021000))&0x4000000)==0x4000000) group.long 0x10++0x03 line.long 0x00 "RCC_PLLSAI1CFGR,PLLSAI1 configuration register" rbitfld.long 0x00 25.--26. " PLLSAI1R ,PLLSAI1 division factor for PLLADC1CLK (ADC clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLSAI1REN ,PLLSAI1 PLLADC1CLK output enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " PLLSAI1Q ,SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)" "/2,/4,/6,/8" bitfld.long 0x00 20. " PLLSAI1QEN ,SAI1PLL PLLUSB2CLK output enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 17. " PLLSAI1P ,SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLSAI1PEN ,SAI1PLL PLLSAI1CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLSAI1N ,SAI1PLL multiplication factor for VCO" else group.long 0x10++0x03 line.long 0x00 "RCC_PLLSAI1CFGR,PLLSAI1 configuration register" bitfld.long 0x00 25.--26. " PLLSAI1R ,PLLSAI1 division factor for PLLADC1CLK (ADC clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLSAI1REN ,PLLSAI1 PLLADC1CLK output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " PLLSAI1Q ,SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)" "/2,/4,/6,/8" bitfld.long 0x00 20. " PLLSAI1QEN ,SAI1PLL PLLUSB2CLK output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PLLSAI1P ,SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLSAI1PEN ,SAI1PLL PLLSAI1CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLSAI1N ,SAI1PLL multiplication factor for VCO" endif else if (((per.l(ad:0x40021000))&0x4000000)==0x4000000) group.long 0x10++0x03 line.long 0x00 "RCC_PLLSAI1CFGR,PLLSAI1 configuration register" bitfld.long 0x00 27.--31. " PLLSAI1PDIV ,PLLSAI1 division factor for PLLSAI1CLK" "PLLP,,VCOSAI1/2,VCOSAI1/3,VCOSAI1/4,VCOSAI1/5,VCOSAI1/6,VCOSAI1/7,VCOSAI1/8,VCOSAI1/9,VCOSAI1/10,VCOSAI1/11,VCOSAI1/12,VCOSAI1/13,VCOSAI1/14,VCOSAI1/15,VCOSAI1/16,VCOSAI1/17,VCOSAI1/18,VCOSAI1/19,VCOSAI1/20,VCOSAI1/21,VCOSAI1/22,VCOSAI1/23,VCOSAI1/24,VCOSAI1/25,VCOSAI1/26,VCOSAI1/27,VCOSAI1/28,VCOSAI1/29,VCOSAI1/30,VCOSAI1/31" rbitfld.long 0x00 25.--26. " PLLSAI1R ,PLLSAI1 division factor for PLLADC1CLK (ADC clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLSAI1REN ,PLLSAI1 PLLADC1CLK output enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " PLLSAI1Q ,SAI1PLL division factor for PLL48M2CLK (48 MHz clock)" "/2,/4,/6,/8" textline " " bitfld.long 0x00 20. " PLLSAI1QEN ,SAI1PLL PLL48M2CLK output enable" "Disabled,Enabled" rbitfld.long 0x00 17. " PLLSAI1P ,SAI1PLL division factor for PLLSAI1CLK (SAI1 clock)" "/7,/17" bitfld.long 0x00 16. " PLLSAI1PEN ,SAI1PLL PLLSAI1CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLSAI1N ,SAI1PLL multiplication factor for VCO" else group.long 0x10++0x03 line.long 0x00 "RCC_PLLSAI1CFGR,PLLSAI1 configuration register" bitfld.long 0x00 27.--31. " PLLSAI1PDIV ,PLLSAI1 division factor for PLLSAI1CLK" "PLLP,,VCOSAI1/2,VCOSAI1/3,VCOSAI1/4,VCOSAI1/5,VCOSAI1/6,VCOSAI1/7,VCOSAI1/8,VCOSAI1/9,VCOSAI1/10,VCOSAI1/11,VCOSAI1/12,VCOSAI1/13,VCOSAI1/14,VCOSAI1/15,VCOSAI1/16,VCOSAI1/17,VCOSAI1/18,VCOSAI1/19,VCOSAI1/20,VCOSAI1/21,VCOSAI1/22,VCOSAI1/23,VCOSAI1/24,VCOSAI1/25,VCOSAI1/26,VCOSAI1/27,VCOSAI1/28,VCOSAI1/29,VCOSAI1/30,VCOSAI1/31" bitfld.long 0x00 25.--26. " PLLSAI1R ,PLLSAI1 division factor for PLLADC1CLK (ADC clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLSAI1REN ,PLLSAI1 PLLADC1CLK output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " PLLSAI1Q ,SAI1PLL division factor for PLL48M2CLK (48 MHz clock)" "/2,/4,/6,/8" textline " " bitfld.long 0x00 20. " PLLSAI1QEN ,SAI1PLL PLL48M2CLK output enable" "Disabled,Enabled" bitfld.long 0x00 17. " PLLSAI1P ,SAI1PLL division factor for PLLSAI1CLK (SAI1 clock)" "/7,/17" bitfld.long 0x00 16. " PLLSAI1PEN ,SAI1PLL PLLSAI1CLK output enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " PLLSAI1N ,SAI1PLL multiplication factor for VCO" endif endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) if (((per.l(ad:0x40021000))&0x10000000)==0x10000000) group.long 0x014++0x03 line.long 0x00 "RCC_PLLSAI2CFGR,PLLSAI2 configuration register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 27.--31. " PLLSAI2PDIV ,PLLSAI2 division factor for PLLSAI2CLK" "PLLSAI2P,,VCOSAI2/2,VCOSAI2/3,VCOSAI2/4,VCOSAI2/5,VCOSAI2/6,VCOSAI2/7,VCOSAI2/8,VCOSAI2/9,VCOSAI2/10,VCOSAI2/11,VCOSAI2/12,VCOSAI2/13,VCOSAI2/14,VCOSAI2/15,VCOSAI2/16,VCOSAI2/17,VCOSAI2/18,VCOSAI2/19,VCOSAI2/20,VCOSAI2/21,VCOSAI2/22,VCOSAI2/23,VCOSAI2/24,VCOSAI2/25,VCOSAI2/26,VCOSAI2/27,VCOSAI2/28,VCOSAI2/29,VCOSAI2/30,VCOSAI2/31" textline " " endif rbitfld.long 0x00 25.--26. " PLLSAI2R ,PLLSAI2 division factor for PLLADC2CLK (ADC clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLSAI2REN ,PLLSAI2 PLLADC2CLK output enable" "Disabled,Enabled" rbitfld.long 0x00 17. " PLLSAI2P ,SAI2PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLSAI2PEN ,SAI2PLL PLLSAI2CLK output enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 8.--14. 1. " PLLSAI2N ,SAI2PLL multiplication factor for VCO" else group.long 0x014++0x03 line.long 0x00 "RCC_PLLSAI2CFGR,PLLSAI2 configuration register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 27.--31. " PLLSAI2PDIV ,PLLSAI2 division factor for PLLSAI2CLK" "PLLSAI2P,,VCOSAI2/2,VCOSAI2/3,VCOSAI2/4,VCOSAI2/5,VCOSAI2/6,VCOSAI2/7,VCOSAI2/8,VCOSAI2/9,VCOSAI2/10,VCOSAI2/11,VCOSAI2/12,VCOSAI2/13,VCOSAI2/14,VCOSAI2/15,VCOSAI2/16,VCOSAI2/17,VCOSAI2/18,VCOSAI2/19,VCOSAI2/20,VCOSAI2/21,VCOSAI2/22,VCOSAI2/23,VCOSAI2/24,VCOSAI2/25,VCOSAI2/26,VCOSAI2/27,VCOSAI2/28,VCOSAI2/29,VCOSAI2/30,VCOSAI2/31" textline " " endif bitfld.long 0x00 25.--26. " PLLSAI2R ,PLLSAI2 division factor for PLLADC2CLK (ADC clock)" "/2,/4,/6,/8" bitfld.long 0x00 24. " PLLSAI2REN ,PLLSAI2 PLLADC2CLK output enable" "Disabled,Enabled" bitfld.long 0x00 17. " PLLSAI2P ,SAI2PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)" "/7,/17" bitfld.long 0x00 16. " PLLSAI2PEN ,SAI2PLL PLLSAI2CLK output enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 8.--14. 1. " PLLSAI2N ,SAI2PLL multiplication factor for VCO" endif endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) group.long 0x18++0x03 line.long 0x00 "RCC_CIER,Clock interrupt enable register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 10. " HSI48RDYIE ,HSI48 ready interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " LSECSSIE ,LSE clock security system interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " PLLSAI2RDYIE ,PLLSAI2 ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLLSAI1RDYIE ,PLLSAI1 ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " PLLRDYIE ,PLL ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " HSERDYIE ,HSE ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " HSIRDYIE ,HSI ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " MSIRDYIE ,MSI ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " LSERDYIE ,LSE ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LSIRDYIE ,LSI ready interrupt enable" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "RCC_CIER,Clock interrupt enable register" bitfld.long 0x00 10. " HSI48RDYIE ,HSI48 ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " LSECSSIE ,LSE clock security system interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " PLLSAI1RDYIE ,PLLSAI1 ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " PLLRDYIE ,PLL ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " HSERDYIE ,HSE ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " HSIRDYIE ,HSI ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " MSIRDYIE ,MSI ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " LSERDYIE ,LSE ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LSIRDYIE ,LSI ready interrupt enable" "Disabled,Enabled" endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) rgroup.long 0x1C++0x03 line.long 0x00 "RCC_CIFR,Clock interrupt flag register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 10. " HSI48RDYF ,HSI48 ready interrupt flag" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 9. " LSECSSF ,LSE clock security system interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " CSSF ,Clock security system interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 7. " PLLSAI2RDYF ,PLLSAI2 ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 6. " PLLSAI1RDYF ,PLLSAI1 ready interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " PLLRDYF ,PLL ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " HSERDYF ,HSE ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " HSIRDYF ,HSI ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " MSIRDYF ,MSI ready interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " LSERDYF ,LSE ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " LSIRDYF ,LSI ready interrupt flag" "No interrupt,Interrupt" else rgroup.long 0x1C++0x03 line.long 0x00 "RCC_CIFR,Clock interrupt flag register" bitfld.long 0x00 10. " HSI48RDYF ,HSI48 ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 9. " LSECSSF ,LSE clock security system interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " CSSF ,Clock security system interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 6. " PLLSAI1RDYF ,PLLSAI1 ready interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " PLLRDYF ,PLL ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " HSERDYF ,HSE ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " HSIRDYF ,HSI ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " MSIRDYF ,MSI ready interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " LSERDYF ,LSE ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " LSIRDYF ,LSI ready interrupt flag" "No interrupt,Interrupt" endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) wgroup.long 0x20++0x03 line.long 0x00 "RCC_CICR,Clock interrupt clear register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 10. " HSI48RDYC ,HSI48 oscillator ready interrupt clear" "No effect,Clear" textline " " endif bitfld.long 0x00 9. " LSECSSC ,LSE clock security system interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " CSSC ,Clock security system interrupt clear" "No effect,Clear" bitfld.long 0x00 7. " PLLSAI2RDYC ,PLLSAI2 ready interrupt clear" "No effect,Clear" bitfld.long 0x00 6. " PLLSAI1RDYC ,PLLSAI1 ready interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 5. " PLLRDYC ,PLL ready interrupt clear" "No effect,Clear" bitfld.long 0x00 4. " HSERDYC ,HSE ready interrupt clear" "No effect,Clear" bitfld.long 0x00 3. " HSIRDYC ,HSI ready interrupt clear" "No effect,Clear" bitfld.long 0x00 2. " MSIRDYC ,MSI ready interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " LSERDYC ,LSE ready interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " LSIRDYC ,LSI ready interrupt clear" "No effect,Clear" else wgroup.long 0x20++0x03 line.long 0x00 "RCC_CICR,Clock interrupt clear register" bitfld.long 0x00 10. " HSI48RDYC ,HSI48 oscillator ready interrupt clear" "No effect,Clear" bitfld.long 0x00 9. " LSECSSC ,LSE clock security system interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " CSSC ,Clock security system interrupt clear" "No effect,Clear" bitfld.long 0x00 6. " PLLSAI1RDYC ,PLLSAI1 ready interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 5. " PLLRDYC ,PLL ready interrupt clear" "No effect,Clear" bitfld.long 0x00 4. " HSERDYC ,HSE ready interrupt clear" "No effect,Clear" bitfld.long 0x00 3. " HSIRDYC ,HSI ready interrupt clear" "No effect,Clear" bitfld.long 0x00 2. " MSIRDYC ,MSI ready interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " LSERDYC ,LSE ready interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " LSIRDYC ,LSI ready interrupt clear" "No effect,Clear" endif group.long 0x28++0x03 line.long 0x00 "RCC_AHB1RSTR,AHB1 peripheral reset register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 17. " DMA2DRST ,HSI48 oscillator ready interrupt clear" "No effect,Reset" textline " " endif bitfld.long 0x00 16. " TSCRST ,Touch Sensing Controller reset" "No effect,Reset" bitfld.long 0x00 12. " CRCRST ,CRC reset" "No effect,Reset" bitfld.long 0x00 8. " FLASHRST ,Flash memory interface reset" "No effect,Reset" bitfld.long 0x00 1. " DMA2RST ,DMA2 reset" "No effect,Reset" textline " " bitfld.long 0x00 0. " DMA1RST ,DMA1 reset" "No effect,Reset" sif ((cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))) group.long 0x2C++0x03 line.long 0x00 "RCC_AHB2RSTR,AHB2 peripheral reset register" bitfld.long 0x00 18. " RNGRST ,Random number generator reset" "No effect,Reset" bitfld.long 0x00 17. " HASHRST ,Hash reset" "No effect,Reset" bitfld.long 0x00 16. " AESRST ,AES hardware accelerator reset" "No effect,Reset" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 14. " DCMIRST ,Digital Camera Interface reset" "No effect,Reset" textline " " endif bitfld.long 0x00 13. " ADCRST ,ADC reset" "No effect,Reset" bitfld.long 0x00 12. " OTGFSRST ,USB OTG FS reset" "No effect,Reset" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 8. " GPIOIRST ,IO port I reset" "No effect,Reset" textline " " endif bitfld.long 0x00 7. " GPIOHRST ,IO port H reset" "No effect,Reset" bitfld.long 0x00 6. " GPIOGRST ,IO port G reset" "No effect,Reset" bitfld.long 0x00 5. " GPIOFRST ,IO port F reset" "No effect,Reset" bitfld.long 0x00 4. " GPIOERST ,IO port E reset" "No effect,Reset" textline " " bitfld.long 0x00 3. " GPIODRST ,IO port D reset" "No effect,Reset" bitfld.long 0x00 2. " GPIOCRST ,IO port C reset" "No effect,Reset" bitfld.long 0x00 1. " GPIOBRST ,IO port B reset" "No effect,Reset" bitfld.long 0x00 0. " GPIOARST ,IO port A reset" "No effect,Reset" elif (cpuis("STM32L4?5*")) group.long 0x2C++0x03 line.long 0x00 "RCC_AHB2RSTR,AHB2 peripheral reset register" bitfld.long 0x00 18. " RNGRST ,Random number generator reset" "No effect,Reset" bitfld.long 0x00 16. " AESRST ,AES hardware accelerator reset" "No effect,Reset" bitfld.long 0x00 13. " ADCRST ,ADC reset" "No effect,Reset" bitfld.long 0x00 12. " OTGFSRST ,USB OTG FS reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " GPIOHRST ,IO port H reset" "No effect,Reset" bitfld.long 0x00 6. " GPIOGRST ,IO port G reset" "No effect,Reset" bitfld.long 0x00 5. " GPIOFRST ,IO port F reset" "No effect,Reset" bitfld.long 0x00 4. " GPIOERST ,IO port E reset" "No effect,Reset" textline " " bitfld.long 0x00 3. " GPIODRST ,IO port D reset" "No effect,Reset" bitfld.long 0x00 2. " GPIOCRST ,IO port C reset" "No effect,Reset" bitfld.long 0x00 1. " GPIOBRST ,IO port B reset" "No effect,Reset" bitfld.long 0x00 0. " GPIOARST ,IO port A reset" "No effect,Reset" elif (cpuis("STM32L471*")) group.long 0x2C++0x03 line.long 0x00 "RCC_AHB2RSTR,AHB2 peripheral reset register" bitfld.long 0x00 18. " RNGRST ,Random number generator reset" "No effect,Reset" bitfld.long 0x00 13. " ADCRST ,ADC reset" "No effect,Reset" bitfld.long 0x00 7. " GPIOHRST ,IO port H reset" "No effect,Reset" textline " " bitfld.long 0x00 6. " GPIOGRST ,IO port G reset" "No effect,Reset" bitfld.long 0x00 5. " GPIOFRST ,IO port F reset" "No effect,Reset" bitfld.long 0x00 4. " GPIOERST ,IO port E reset" "No effect,Reset" bitfld.long 0x00 3. " GPIODRST ,IO port D reset" "No effect,Reset" textline " " bitfld.long 0x00 2. " GPIOCRST ,IO port C reset" "No effect,Reset" bitfld.long 0x00 1. " GPIOBRST ,IO port B reset" "No effect,Reset" bitfld.long 0x00 0. " GPIOARST ,IO port A reset" "No effect,Reset" elif (cpuis("STM32L4?2*"))||(cpuis("STM32L451*")) group.long 0x2C++0x03 line.long 0x00 "RCC_AHB2RSTR,AHB2 peripheral reset register" bitfld.long 0x00 18. " RNGRST ,Random number generator reset" "No effect,Reset" textline " " sif (!cpuis("STM32L432KC"))||(cpuis("STM32L451*")) bitfld.long 0x00 16. " AESRST ,AES hardware accelerator reset" "No effect,Reset" textline " " endif bitfld.long 0x00 13. " ADCRST ,ADC reset" "No effect,Reset" bitfld.long 0x00 7. " GPIOHRST ,IO port H reset" "No effect,Reset" textline " " sif (!cpuis("STM32L432*"))&&(!cpuis("STM32L442*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4. " GPIOERST ,IO port E reset" "No effect,Reset" bitfld.long 0x00 3. " GPIODRST ,IO port D reset" "No effect,Reset" textline " " endif bitfld.long 0x00 2. " GPIOCRST ,IO port C reset" "No effect,Reset" bitfld.long 0x00 1. " GPIOBRST ,IO port B reset" "No effect,Reset" bitfld.long 0x00 0. " GPIOARST ,IO port A reset" "No effect,Reset" elif (cpuis("STM32L443*")) group.long 0x2C++0x03 line.long 0x00 "RCC_AHB2RSTR,AHB2 peripheral reset register" bitfld.long 0x00 18. " RNGRST ,Random number generator reset" "No effect,Reset" bitfld.long 0x00 16. " AESRST ,AES hardware accelerator reset" "No effect,Reset" bitfld.long 0x00 13. " ADCRST ,ADC reset" "No effect,Reset" bitfld.long 0x00 7. " GPIOHRST ,IO port H reset" "No effect,Reset" textline " " bitfld.long 0x00 4. " GPIOERST ,IO port E reset" "No effect,Reset" bitfld.long 0x00 3. " GPIODRST ,IO port D reset" "No effect,Reset" bitfld.long 0x00 2. " GPIOCRST ,IO port C reset" "No effect,Reset" bitfld.long 0x00 1. " GPIOBRST ,IO port B reset" "No effect,Reset" textline " " bitfld.long 0x00 0. " GPIOARST ,IO port A reset" "No effect,Reset" elif (cpuis("STM32L431*"))||(cpuis("STM32L433*")) group.long 0x2C++0x03 line.long 0x00 "RCC_AHB2RSTR,AHB2 peripheral reset register" bitfld.long 0x00 18. " RNGRST ,Random number generator reset" "No effect,Reset" bitfld.long 0x00 13. " ADCRST ,ADC reset" "No effect,Reset" bitfld.long 0x00 7. " GPIOHRST ,IO port H reset" "No effect,Reset" bitfld.long 0x00 4. " GPIOERST ,IO port E reset" "No effect,Reset" textline " " bitfld.long 0x00 3. " GPIODRST ,IO port D reset" "No effect,Reset" bitfld.long 0x00 2. " GPIOCRST ,IO port C reset" "No effect,Reset" bitfld.long 0x00 1. " GPIOBRST ,IO port B reset" "No effect,Reset" bitfld.long 0x00 0. " GPIOARST ,IO port A reset" "No effect,Reset" endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) group.long 0x30++0x03 line.long 0x00 "RCC_AHB3RSTR,AHB3 peripheral reset register" bitfld.long 0x00 8. " QSPIRST ,Quad SPI memory interface reset" "No effect,Reset" bitfld.long 0x00 0. " FMCRST ,Flexible memory controller reset" "No effect,Reset" else group.long 0x30++0x03 line.long 0x00 "RCC_AHB3RSTR,AHB3 peripheral reset register" bitfld.long 0x00 8. " QSPIRST ,Quad SPI memory interface reset" "No effect,Reset" endif sif ((cpuis("STM32L496*"))||(cpuis("STM32L4A6*")))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x38++0x03 line.long 0x00 "RCC_APB1RSTR1,APB1 peripheral reset register 1" bitfld.long 0x00 31. " LPTIM1RST ,Low Power Timer 1 reset" "No effect,Reset" bitfld.long 0x00 30. " OPAMPRST ,OPAMP interface reset" "No effect,Reset" bitfld.long 0x00 29. " DAC1RST ,DAC1 interface reset" "No effect,Reset" bitfld.long 0x00 28. " PWRRST ,Power interface reset" "No effect,Reset" textline " " sif (!cpuis("STM32L476*"))||(!cpuis("STM32L486*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 26. " CAN2RST ,CAN2 reset" "No effect,Reset" textline " " endif bitfld.long 0x00 25. " CAN1RST ,CAN1 reset" "No effect,Reset" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 24. " CRSRST ,CRS reset" "No effect,Reset" textline " " endif bitfld.long 0x00 23. " I2C3RST ,I2C3 reset" "No effect,Reset" bitfld.long 0x00 22. " I2C2RST ,I2C2 reset" "No effect,Reset" bitfld.long 0x00 21. " I2C1RST ,I2C1 reset" "No effect,Reset" textline " " bitfld.long 0x00 20. " UART5RST ,UART5 reset" "No effect,Reset" bitfld.long 0x00 19. " UART4RST ,UART4 reset" "No effect,Reset" bitfld.long 0x00 18. " UART3RST ,UART3 reset" "No effect,Reset" bitfld.long 0x00 17. " UART2RST ,UART2 reset" "No effect,Reset" textline " " bitfld.long 0x00 15. " SPI3RST ,SPI3 reset" "No effect,Reset" bitfld.long 0x00 14. " SPI2RST ,SPI2 reset" "No effect,Reset" bitfld.long 0x00 9. " LCDRST ,LCD interface reset" "No effect,Reset" bitfld.long 0x00 5. " TIM7RST ,TIM7 timer reset" "No effect,Reset" textline " " bitfld.long 0x00 4. " TIM6RST ,TIM6 timer reset" "No effect,Reset" bitfld.long 0x00 3. " TIM5RST ,TIM5 timer reset" "No effect,Reset" bitfld.long 0x00 2. " TIM4RST ,TIM4 timer reset" "No effect,Reset" bitfld.long 0x00 1. " TIM3RST ,TIM3 timer reset" "No effect,Reset" textline " " bitfld.long 0x00 0. " TIM2RST ,TIM2 timer reset" "No effect,Reset" elif (cpuis("STM32L4?5*"))||(cpuis("STM32L471*")) group.long 0x38++0x03 line.long 0x00 "RCC_APB1RSTR1,APB1 peripheral reset register 1" bitfld.long 0x00 31. " LPTIM1RST ,Low Power Timer 1 reset" "No effect,Reset" bitfld.long 0x00 30. " OPAMPRST ,OPAMP interface reset" "No effect,Reset" bitfld.long 0x00 29. " DAC1RST ,DAC1 interface reset" "No effect,Reset" bitfld.long 0x00 28. " PWRRST ,Power interface reset" "No effect,Reset" textline " " bitfld.long 0x00 25. " CAN1RST ,CAN1 reset" "No effect,Reset" bitfld.long 0x00 23. " I2C3RST ,I2C3 reset" "No effect,Reset" bitfld.long 0x00 22. " I2C2RST ,I2C2 reset" "No effect,Reset" bitfld.long 0x00 21. " I2C1RST ,I2C1 reset" "No effect,Reset" textline " " bitfld.long 0x00 20. " UART5RST ,UART5 reset" "No effect,Reset" bitfld.long 0x00 19. " UART4RST ,UART4 reset" "No effect,Reset" bitfld.long 0x00 18. " UART3RST ,UART3 reset" "No effect,Reset" bitfld.long 0x00 17. " UART2RST ,UART2 reset" "No effect,Reset" textline " " bitfld.long 0x00 15. " SPI3RST ,SPI3 reset" "No effect,Reset" bitfld.long 0x00 14. " SPI2RST ,SPI2 reset" "No effect,Reset" textline " " sif (cpuis("STM32L4?5*")) bitfld.long 0x00 9. " LCDRST ,LCD interface reset" "No effect,Reset" textline " " endif bitfld.long 0x00 5. " TIM7RST ,TIM7 timer reset" "No effect,Reset" bitfld.long 0x00 4. " TIM6RST ,TIM6 timer reset" "No effect,Reset" bitfld.long 0x00 3. " TIM5RST ,TIM5 timer reset" "No effect,Reset" bitfld.long 0x00 2. " TIM4RST ,TIM4 timer reset" "No effect,Reset" textline " " bitfld.long 0x00 1. " TIM3RST ,TIM3 timer reset" "No effect,Reset" bitfld.long 0x00 0. " TIM2RST ,TIM2 timer reset" "No effect,Reset" elif (cpuis("STM32L4?2*")) group.long 0x38++0x03 line.long 0x00 "RCC_APB1RSTR1,APB1 peripheral reset register 1" bitfld.long 0x00 31. " LPTIM1RST ,Low Power Timer 1 reset" "No effect,Reset" bitfld.long 0x00 30. " OPAMPRST ,OPAMP interface reset" "No effect,Reset" bitfld.long 0x00 29. " DAC1RST ,DAC1 interface reset" "No effect,Reset" bitfld.long 0x00 28. " PWRRST ,Power interface reset" "No effect,Reset" textline " " bitfld.long 0x00 26. " USBFSRST ,USB FS reset" "No effect,Reset" bitfld.long 0x00 25. " CAN1RST ,CAN1 reset" "No effect,Reset" bitfld.long 0x00 24. " CRSRST ,CRS reset" "No effect,Reset" bitfld.long 0x00 23. " I2C3RST ,I2C3 reset" "No effect,Reset" textline " " bitfld.long 0x00 21. " I2C1RST ,I2C1 reset" "No effect,Reset" bitfld.long 0x00 17. " USART2RST ,USART2 reset" "No effect,Reset" bitfld.long 0x00 15. " SPI3RST ,SPI3 reset" "No effect,Reset" bitfld.long 0x00 5. " TIM7RST ,TIM7 timer reset" "No effect,Reset" textline " " bitfld.long 0x00 4. " TIM6RST ,TIM6 timer reset" "No effect,Reset" bitfld.long 0x00 0. " TIM2RST ,TIM2 timer reset" "No effect,Reset" elif (cpuis("STM32L4?3*")) group.long 0x38++0x03 line.long 0x00 "RCC_APB1RSTR1,APB1 peripheral reset register 1" bitfld.long 0x00 31. " LPTIM1RST ,Low Power Timer 1 reset" "No effect,Reset" bitfld.long 0x00 30. " OPAMPRST ,OPAMP interface reset" "No effect,Reset" bitfld.long 0x00 29. " DAC1RST ,DAC1 interface reset" "No effect,Reset" bitfld.long 0x00 28. " PWRRST ,Power interface reset" "No effect,Reset" textline " " bitfld.long 0x00 26. " USBFSRST ,USB FS reset" "No effect,Reset" bitfld.long 0x00 25. " CAN1RST ,CAN1 reset" "No effect,Reset" bitfld.long 0x00 24. " CRSRST ,CRS reset" "No effect,Reset" bitfld.long 0x00 23. " I2C3RST ,I2C3 reset" "No effect,Reset" textline " " bitfld.long 0x00 22. " I2C2RST ,I2C2 reset" "No effect,Reset" bitfld.long 0x00 21. " I2C1RST ,I2C1 reset" "No effect,Reset" bitfld.long 0x00 18. " USART3RST ,USART3 reset" "No effect,Reset" bitfld.long 0x00 17. " USART2RST ,USART2 reset" "No effect,Reset" textline " " bitfld.long 0x00 15. " SPI3RST ,SPI3 reset" "No effect,Reset" bitfld.long 0x00 14. " SPI2RST ,SPI2 reset" "No effect,Reset" bitfld.long 0x00 9. " LCDRST ,LCD interface reset" "No effect,Reset" bitfld.long 0x00 5. " TIM7RST ,TIM7 timer reset" "No effect,Reset" textline " " bitfld.long 0x00 4. " TIM6RST ,TIM6 timer reset" "No effect,Reset" bitfld.long 0x00 0. " TIM2RST ,TIM2 timer reset" "No effect,Reset" elif (cpuis("STM32L431*")) group.long 0x38++0x03 line.long 0x00 "RCC_APB1RSTR1,APB1 peripheral reset register 1" bitfld.long 0x00 31. " LPTIM1RST ,Low Power Timer 1 reset" "No effect,Reset" bitfld.long 0x00 30. " OPAMPRST ,OPAMP interface reset" "No effect,Reset" bitfld.long 0x00 29. " DAC1RST ,DAC1 interface reset" "No effect,Reset" bitfld.long 0x00 28. " PWRRST ,Power interface reset" "No effect,Reset" textline " " bitfld.long 0x00 25. " CAN1RST ,CAN1 reset" "No effect,Reset" bitfld.long 0x00 24. " CRSRST ,CRS reset" "No effect,Reset" bitfld.long 0x00 23. " I2C3RST ,I2C3 reset" "No effect,Reset" bitfld.long 0x00 22. " I2C2RST ,I2C2 reset" "No effect,Reset" textline " " bitfld.long 0x00 21. " I2C1RST ,I2C1 reset" "No effect,Reset" bitfld.long 0x00 18. " USART3RST ,UART3 reset" "No effect,Reset" bitfld.long 0x00 17. " USART2RST ,UART2 reset" "No effect,Reset" bitfld.long 0x00 15. " SPI3RST ,SPI3 reset" "No effect,Reset" textline " " bitfld.long 0x00 14. " SPI2RST ,SPI2 reset" "No effect,Reset" bitfld.long 0x00 5. " TIM7RST ,TIM7 timer reset" "No effect,Reset" bitfld.long 0x00 4. " TIM6RST ,TIM6 timer reset" "No effect,Reset" bitfld.long 0x00 0. " TIM2RST ,TIM2 timer reset" "No effect,Reset" endif group.long 0x3C++0x03 line.long 0x00 "RCC_APB1RSTR2,APB1 peripheral reset register 2" bitfld.long 0x00 5. " LPTIM2RST ,Low-power timer 2 reset" "No effect,Reset" bitfld.long 0x00 2. " SWPMI1RST ,Single wire protocol reset" "No effect,Reset" textline " " sif (cpuis("STM32L45*")||cpuis("STM32L46*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")) bitfld.long 0x00 1. " I2C4RST ,I2C4 reset" "No effect,Reset" textline " " endif bitfld.long 0x00 0. " LPUART1RST ,Low-power UART 1 reset" "No effect,Reset" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) group.long 0x40++0x03 line.long 0x00 "RCC_APB2RSTR,APB2 peripheral reset register" bitfld.long 0x00 24. " DFSDMRST ,Digital filters for sigma-delta modulators (DFSDM) reset" "No effect,Reset" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 22. " SAI2RST ,Serial audio interface 2 (SAI2) reset" "No effect,Reset" textline " " endif bitfld.long 0x00 21. " SAI1RST ,Serial audio interface 1 (SAI1) reset" "No effect,Reset" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 18. " TIM17RST ,TIM17 timer reset" "No effect,Reset" textline " " endif bitfld.long 0x00 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset" bitfld.long 0x00 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset" bitfld.long 0x00 14. " USART1RST ,USART1 reset" "No effect,Reset" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 13. " TIM8RST ,TIM8 timer reset" "No effect,Reset" textline " " endif bitfld.long 0x00 12. " SPI1RST ,SPI1 reset" "No effect,Reset" bitfld.long 0x00 11. " TIM1RST ,TIM1 timer reset" "No effect,Reset" bitfld.long 0x00 10. " SDMMCRST ,SDMMC reset" "No effect,Reset" bitfld.long 0x00 0. " SYSCFGRST ,System configuration (SYSCFG) reset" "No effect,Reset" elif (cpuis("STM32L4?2*")) group.long 0x40++0x03 line.long 0x00 "RCC_APB2RSTR,APB2 peripheral reset register" bitfld.long 0x00 21. " SAI1RST ,Serial audio interface 1 (SAI1) reset" "No effect,Reset" bitfld.long 0x00 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset" bitfld.long 0x00 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset" bitfld.long 0x00 14. " USART1RST ,USART1 reset" "No effect,Reset" textline " " bitfld.long 0x00 12. " SPI1RST ,SPI1 reset" "No effect,Reset" bitfld.long 0x00 11. " TIM1RST ,TIM1 timer reset" "No effect,Reset" bitfld.long 0x00 0. " SYSCFGRST ,System configuration (SYSCFG) reset" "No effect,Reset" else group.long 0x40++0x03 line.long 0x00 "RCC_APB2RSTR,APB2 peripheral reset register" bitfld.long 0x00 21. " SAI1RST ,Serial audio interface 1 (SAI1) reset" "No effect,Reset" bitfld.long 0x00 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset" bitfld.long 0x00 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset" bitfld.long 0x00 14. " USART1RST ,USART1 reset" "No effect,Reset" textline " " bitfld.long 0x00 12. " SPI1RST ,SPI1 reset" "No effect,Reset" bitfld.long 0x00 11. " TIM1RST ,TIM1 timer reset" "No effect,Reset" bitfld.long 0x00 10. " SDMMCRST ,SDMMC reset" "No effect,Reset" bitfld.long 0x00 0. " SYSCFGRST ,System configuration (SYSCFG) reset" "No effect,Reset" endif group.long 0x48++0x03 line.long 0x00 "RCC_AHB1ENR,AHB1 peripheral clock enable register" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) bitfld.long 0x00 17. " DMA2DEN ,DMA2D clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 16. " TSCEN ,Touch Sensing Controller clock enable" "Disabled,Enabled" bitfld.long 0x00 12. " CRCEN ,CRC clock enable" "Disabled,Enabled" bitfld.long 0x00 8. " FLASHEN ,Flash memory interface clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled" sif ((cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))) group.long 0x4C++0x03 line.long 0x00 "RCC_AHB2ENR,AHB2 peripheral clock enable register" bitfld.long 0x00 18. " RNGEN ,Random Number Generator clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 17. " HASHEN ,HASH clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 16. " AESEN ,AES accelerator clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 14. " DCMIEN ,DCMI clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " ADCEN ,ADC clock enable" "Disabled,Enabled" bitfld.long 0x00 12. " OTGFSEN ,OTG full speed clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 8. " GPIOIEN ,IO port I clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled" bitfld.long 0x00 6. " GPIOGEN ,IO port G clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " GPIOFEN ,IO port F clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled" elif (cpuis("STM32L4?5*")) group.long 0x4C++0x03 line.long 0x00 "RCC_AHB2ENR,AHB2 peripheral clock enable register" bitfld.long 0x00 18. " RNGEN ,Random Number Generator clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " AESEN ,AES accelerator clock enable" "Disabled,Enabled" bitfld.long 0x00 13. " ADCEN ,ADC clock enable" "Disabled,Enabled" bitfld.long 0x00 12. " OTGFSEN ,OTG full speed clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled" bitfld.long 0x00 6. " GPIOGEN ,IO port G clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " GPIOFEN ,IO port F clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled" elif (cpuis("STM32L471*")) group.long 0x4C++0x03 line.long 0x00 "RCC_AHB2ENR,AHB2 peripheral clock enable register" bitfld.long 0x00 18. " RNGEN ,Random Number Generator clock enable" "Disabled,Enabled" bitfld.long 0x00 13. " ADCEN ,ADC clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled" bitfld.long 0x00 6. " GPIOGEN ,IO port G clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GPIOFEN ,IO port F clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled" bitfld.long 0x00 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled" elif (cpuis("STM32L4?2*")) group.long 0x4C++0x03 line.long 0x00 "RCC_AHB2ENR,AHB2 peripheral clock enable register" bitfld.long 0x00 18. " RNGEN ,Random Number Generator clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L432KC")) bitfld.long 0x00 16. " AESEN ,AES accelerator clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " ADCEN ,ADC clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled" elif (cpuis("STM32L443*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x4C++0x03 line.long 0x00 "RCC_AHB2ENR,AHB2 peripheral clock enable register" bitfld.long 0x00 18. " RNGEN ,Random Number Generator clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*")) bitfld.long 0x00 16. " AESEN ,AES accelerator clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " ADCEN ,ADC clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled" bitfld.long 0x00 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled" elif (cpuis("STM32L431*"))||(cpuis("STM32L433*")) group.long 0x4C++0x03 line.long 0x00 "RCC_AHB2ENR,AHB2 peripheral clock enable register" bitfld.long 0x00 18. " RNGEN ,Random Number Generator clock enable" "Disabled,Enabled" bitfld.long 0x00 13. " ADCEN ,ADC clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHEN ,IO port H clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOEEN ,IO port E clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GPIODEN ,IO port D clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCEN ,IO port C clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBEN ,IO port B clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOAEN ,IO port A clock enable" "Disabled,Enabled" endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) group.long 0x50++0x03 line.long 0x00 "RCC_AHB3ENR,AHB3 peripheral clock enable register" bitfld.long 0x00 8. " QSPIEN ,Quad SPI memory interface clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " FMCEN ,Flexible memory controller clock enable" "Disabled,Enabled" else group.long 0x50++0x03 line.long 0x00 "RCC_AHB3ENR,AHB3 peripheral clock enable register" bitfld.long 0x00 8. " QSPIEN ,Quad SPI memory interface clock enable" "Disabled,Enabled" endif sif ((cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))) group.long 0x58++0x03 line.long 0x00 "RCC_APB1ENR1,APB1 peripheral clock enable register 1" bitfld.long 0x00 31. " LPTIM1EN ,Low power timer 1 clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPEN ,OPAMP interface clock enable" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1EN ,DAC1 interface clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " PWREN ,Power interface clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 26. " CAN2EN ,CAN2 clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 24. " CRSEN ,Clock Recovery System clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2EN ,I2C2 clock enable" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1EN ,I2C1 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " UART5EN ,UART5 clock enable" "Disabled,Enabled" bitfld.long 0x00 19. " UART4EN ,UART4 clock enable" "Disabled,Enabled" bitfld.long 0x00 18. " UART3EN ,UART3 clock enable" "Disabled,Enabled" bitfld.long 0x00 17. " UART2EN ,UART2 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPI3EN ,SPI3 clock enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 10. " RTCAPBEN , RTC APB clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " LCDEN ,LCD clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " TIM7EN ,TIM7 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6EN ,TIM6 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 3. " TIM5EN ,TIM5 timer clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TIM4EN ,TIM4 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " TIM3EN ,TIM3 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2EN ,TIM2 timer clock enable" "Disabled,Enabled" elif (cpuis("STM32L4?5*"))||(cpuis("STM32L471*")) group.long 0x58++0x03 line.long 0x00 "RCC_APB1ENR1,APB1 peripheral clock enable register 1" bitfld.long 0x00 31. " LPTIM1EN ,Low power timer 1 clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPEN ,OPAMP interface clock enable" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1EN ,DAC1 interface clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " PWREN ,Power interface clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2EN ,I2C2 clock enable" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1EN ,I2C1 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " UART5EN ,UART5 clock enable" "Disabled,Enabled" bitfld.long 0x00 19. " UART4EN ,UART4 clock enable" "Disabled,Enabled" bitfld.long 0x00 18. " UART3EN ,UART3 clock enable" "Disabled,Enabled" bitfld.long 0x00 17. " UART2EN ,UART2 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPI3EN ,SPI3 clock enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L475*")) bitfld.long 0x00 9. " LCDEN ,LCD clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 5. " TIM7EN ,TIM7 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6EN ,TIM6 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 2. " TIM4EN ,TIM4 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 1. " TIM3EN ,TIM3 timer clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TIM2EN ,TIM2 timer clock enable" "Disabled,Enabled" elif (cpuis("STM32L4?2*"))||(cpuis("STM32L451*")) group.long 0x58++0x03 line.long 0x00 "RCC_APB1ENR1,APB1 peripheral clock enable register 1" bitfld.long 0x00 31. " LPTIM1EN ,Low power timer 1 clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPEN ,OPAMP interface clock enable" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1EN ,DAC1 interface clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " PWREN ,Power interface clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " USBFSEN ,USB FS clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " CRSEN ,CRS clock enable" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 22. " I2C2EN ,I2C2 clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " I2C1EN ,I2C1 clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 19. " UART4EN ,UART4 clock enable" "Disabled,Enabled" bitfld.long 0x00 18. " UART3EN ,UART3 clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " UART2EN ,UART2 clock enable" "Disabled,Enabled" bitfld.long 0x00 15. " SPI3EN ,SPI3 clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " RTCAPBEN ,RTC APB clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 9. " LCDEN ,LCD clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 5. " TIM7EN ,TIM7 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6EN ,TIM6 timer clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 1. " TIM3EN ,TIM3 timer clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 0. " TIM2EN ,TIM2 timer clock enable" "Disabled,Enabled" elif (cpuis("STM32L4?3*")) group.long 0x58++0x03 line.long 0x00 "RCC_APB1ENR1,APB1 peripheral clock enable register 1" bitfld.long 0x00 31. " LPTIM1EN ,Low power timer 1 clock enable" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPEN ,OPAMP interface clock enable" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1EN ,DAC1 interface clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " PWREN ,Power interface clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " USBFSEN ,USB FS clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " CRSEN ,CRS clock enable" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " I2C2EN ,I2C2 clock enable" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1EN ,I2C1 clock enable" "Disabled,Enabled" bitfld.long 0x00 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled" bitfld.long 0x00 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPI3EN ,SPI3 clock enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " RTCAPBEN ,RTC APB clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " LCDEN ,LCD clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " TIM7EN ,TIM7 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6EN ,TIM6 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2EN ,TIM2 timer clock enable" "Disabled,Enabled" elif (cpuis("STM32L431*")) group.long 0x58++0x03 line.long 0x00 "RCC_APB1ENR1,APB1 peripheral clock enable register 1" bitfld.long 0x00 31. " LPTIM1EN ,Low power timer 1 cloc k enable" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPEN ,OPAMP interface clock enable" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1EN ,DAC1 interface clock enable" "Disabled,Enabled" bitfld.long 0x00 28. " PWREN ,Power interface clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled" bitfld.long 0x00 24. " CRSEN ,CRS clock enable" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2EN ,I2C2 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " I2C1EN ,I2C1 clock enable" "Disabled,Enabled" bitfld.long 0x00 18. " UART3EN ,USART3 clock enable" "Disabled,Enabled" bitfld.long 0x00 17. " UART2EN ,USART2 clock enable" "Disabled,Enabled" bitfld.long 0x00 15. " SPI3EN ,SPI3 clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " RTCAPBEN ,RTC APB clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " TIM7EN ,TIM7 timer clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TIM6EN ,TIM6 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2EN ,TIM2 timer clock enable" "Disabled,Enabled" endif group.long 0x5C++0x03 line.long 0x00 "RCC_APB1ENR2,APB1 peripheral clock enable register 2" bitfld.long 0x00 5. " LPTIM2EN ,Low power timer 2 clock enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 2. " SWPMI1EN ,Single wire protocol clock enable" "Disabled,Enabled" textline " " endif sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 1. " I2C4EN ,I2C4 clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 0. " LPUART1EN ,Low power UART 1 clock enable" "Disabled,Enabled" sif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*")) group.long 0x60++0x03 line.long 0x00 "RCC_APB2ENR,APB2 peripheral clock enable register" bitfld.long 0x00 21. " SAI1EN ,SAI1 clock enable" "Disabled,Enabled" bitfld.long 0x00 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 14. " USART1EN ,USART1clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SPI1EN ,SPI1 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " TIM1EN ,TIM1 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " SDMMC1EN ,SDMMC clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " FWEN ,Firewall clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled" elif (cpuis("STM32L4?2*")) group.long 0x60++0x03 line.long 0x00 "RCC_APB2ENR,APB2 peripheral clock enable register" bitfld.long 0x00 21. " SAI1EN ,SAI1 clock enable" "Disabled,Enabled" bitfld.long 0x00 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 14. " USART1EN ,USART1clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SPI1EN ,SPI1 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " TIM1EN ,TIM1 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " FWEN ,Firewall clock enable" "Disabled,Enabled" bitfld.long 0x00 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "RCC_APB2ENR,APB2 peripheral clock enable register" bitfld.long 0x00 24. " DFSDMEN ,DFSDM timer clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 22. " SAI2EN ,SAI2 clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " SAI1EN ,SAI1 clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 14. " USART1EN ,USART1clock enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 13. " TIM8EN ,TIM8 timer clock enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 12. " SPI1EN ,SPI1 clock enable" "Disabled,Enabled" bitfld.long 0x00 11. " TIM1EN ,TIM1 timer clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " SDMMCEN ,SDMMC clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " FWEN ,Firewall clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled" endif group.long 0x68++0x03 line.long 0x00 "RCC_AHB1SMENR,AHB1 peripheral clocks enable in Sleep and Stop modes register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 17. " DMA2DSMEN ,DMA2D clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 16. " TSCSMEN ,Touch Sensing Controller clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 12. " CRCSMEN ,CRC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 9. " SRAM1SMEN ,SRAM1 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 8. " FLASHSMEN ,Flash memory interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DMA2SMEN ,DMA2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " DMA1SMEN ,DMA1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" sif ((cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))) group.long 0x6C++0x03 line.long 0x00 "RCC_AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 18. " RNGSMEN ,Random Number Generator clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 17. " HASHSMEN ,HASH clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 16. " AESSMEN ,AES accelerator clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 14. " DCMISMEN ,DCMI clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " ADCSMEN ,ADC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 12. " OTGFSSMEN ,OTG full speed clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 9. " SRAM2SMEN ,SRAM2 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 8. " GPIOISMEN ,IO port I clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 7. " GPIOHSMEN ,IO port H clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 6. " GPIOGSMEN ,IO port G clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 5. " GPIOFSMEN ,IO port F clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOESMEN ,IO port E clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GPIODSMEN ,IO port D clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCSMEN ,IO port C clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBSMEN ,IO port B clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOASMEN ,IO port A clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L4?5*")) group.long 0x6C++0x03 line.long 0x00 "RCC_AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 18. " RNGSMEN ,Random Number Generator clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 16. " AESSMEN ,AES accelerator clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 13. " ADCSMEN ,ADC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 12. " OTGFSSMEN ,OTG full speed clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " SRAM2SMEN ,SRAM2 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHSMEN ,IO port H clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 6. " GPIOGSMEN ,IO port G clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 5. " GPIOFSMEN ,IO port F clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " GPIOESMEN ,IO port E clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 3. " GPIODSMEN ,IO port D clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCSMEN ,IO port C clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBSMEN ,IO port B clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GPIOASMEN ,IO port A clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L471*")) group.long 0x6C++0x03 line.long 0x00 "RCC_AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 18. " RNGSMEN ,Random Number Generator clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 13. " ADCSMEN ,ADC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 9. " SRAM2SMEN ,SRAM2 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHSMEN ,IO port H clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " GPIOGSMEN ,IO port G clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 5. " GPIOFSMEN ,IO port F clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 4. " GPIOESMEN ,IO port E clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 3. " GPIODSMEN ,IO port D clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " GPIOCSMEN ,IO port C clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBSMEN ,IO port B clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOASMEN ,IO port A clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L431*"))||(cpuis("STM32L433*")) group.long 0x6C++0x03 line.long 0x00 "RCC_AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 18. " RNGSMEN ,Random Number Generator clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 13. " ADCSMEN ,ADC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 9. " SRAM2SMEN ,SRAM2 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHSMEN ,IO port H clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " GPIOESMEN ,IO port E clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 3. " GPIODSMEN ,IO port D clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 2. " GPIOCSMEN ,IO port C clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBSMEN ,IO port B clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GPIOASMEN ,IO port A clocks enable during Sleep and Stop modes" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "RCC_AHB2SMENR,AHB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 18. " RNGSMEN ,Random Number Generator clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L432KC")) bitfld.long 0x00 16. " AESSMEN ,AES accelerator clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " ADCSMEN ,ADC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 9. " SRAM2SMEN ,SRAM2 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 7. " GPIOHSMEN ,IO port H clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L432KC"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 4. " GPIOESMEN ,IO port E clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 3. " GPIODSMEN ,IO port D clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " GPIOCSMEN ,IO port C clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 1. " GPIOBSMEN ,IO port B clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " GPIOASMEN ,IO port A clocks enable during Sleep and Stop modes" "Disabled,Enabled" endif sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) group.long 0x70++0x03 line.long 0x00 "RCC_AHB3SMENR,AHB3 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 8. " QSPISMEN ,Quad SPI memory interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " FMCSMEN ,Flexible memory controller clocks enable during Sleep and Stop modes" "Disabled,Enabled" else group.long 0x70++0x03 line.long 0x00 "RCC_AHB3SMENR,AHB3 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 8. " QSPISMEN ,Quad SPI memory interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" endif sif ((cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))) group.long 0x78++0x03 line.long 0x00 "RCC_APB1SMENR1,APB1 peripheral clocks enable in Sleep and Stop modes register 1" bitfld.long 0x00 31. " LPTIM1SMEN ,Low power timer 1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPSMEN ,OPAMP interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1SMEN ,DAC1 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 28. " PWRSMEN ,Power interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 26. " CAN2SMEN ,CAN2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 25. " CAN1SMEN ,CAN1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 24. " CRSSMEN ,CRS clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " I2C3SMEN ,I2C3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2SMEN ,I2C2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1SMEN ,I2C1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 20. " UART5SMEN ,UART5 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 19. " UART4SMEN ,UART4 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 18. " USART3SMEN ,USART3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 17. " USART2SMEN ,USART2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPI3SMEN ,SPI3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 14. " SPI2SMEN ,SPI2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGSMEN ,Window watchdog clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L476*"))&&(!cpuis("STM32L486*")) bitfld.long 0x00 10. " RTCAPBSMEN ,RTC APB clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " LCDSMEN ,LCD clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 5. " TIM7SMEN ,TIM7 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6SMEN ,TIM6 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.long 0x00 3. " TIM5SMEN ,TIM5 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 2. " TIM4SMEN ,TIM4 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " TIM3SMEN ,TIM3 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2SMEN ,TIM2 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L4?5*"))||(cpuis("STM32L471*")) group.long 0x78++0x03 line.long 0x00 "RCC_APB1SMENR1,APB1 peripheral clocks enable in Sleep and Stop modes register 1" bitfld.long 0x00 31. " LPTIM1SMEN ,Low power timer 1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPSMEN ,OPAMP interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1SMEN ,DAC1 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 28. " PWRSMEN ,Power interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " CAN1SMEN ,CAN1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3SMEN ,I2C3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2SMEN ,I2C2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1SMEN ,I2C1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " UART5SMEN ,UART5 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 19. " UART4SMEN ,UART4 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 18. " USART3SMEN ,USART3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 17. " USART2SMEN ,USART2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPI3SMEN ,SPI3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 14. " SPI2SMEN ,SPI2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGSMEN ,Window watchdog clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (cpuis("STM32L4?5*")) bitfld.long 0x00 9. " LCDSMEN ,LCD clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 5. " TIM7SMEN ,TIM7 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6SMEN ,TIM6 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 3. " TIM5SMEN ,TIM5 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 2. " TIM4SMEN ,TIM4 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIM3SMEN ,TIM3 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2SMEN ,TIM2 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L4?2*")) group.long 0x78++0x03 line.long 0x00 "RCC_APB1SMENR1,APB1 peripheral clocks enable in Sleep and Stop modes register 1" bitfld.long 0x00 31. " LPTIM1SMEN ,Low power timer 1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPSMEN ,OPAMP interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1SMEN ,DAC1 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 28. " PWRSMEN ,Power interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " CAN1SMEN ,CAN1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 24. " CRSSMEN ,CRS clock enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3SMEN ,I2C3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1SMEN ,I2C1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " USART2SMEN ,USART2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 15. " SPI3SMEN ,SPI3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGSMEN ,Window watchdog clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 10. " RTCAPBSMEN ,RTC APB clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TIM7SMEN ,TIM7 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6SMEN ,TIM6 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2SMEN ,TIM2 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L431*")) group.long 0x78++0x03 line.long 0x00 "RCC_APB1SMENR1,APB1 peripheral clocks enable in Sleep and Stop modes register 1" bitfld.long 0x00 31. " LPTIM1SMEN ,Low power timer 1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPSMEN ,OPAMP interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1SMEN ,DAC1 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 28. " PWRSMEN ,Power interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " CAN1SMEN ,CAN1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 24. " CRSSMEN ,CRS clock enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3SMEN ,I2C3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 22. " I2C2SMEN ,I2C2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " I2C1SMEN ,I2C1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 18. " USART3SMEN ,USART3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 17. " USART2SMEN ,USART2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 15. " SPI3SMEN ,SPI3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " SPI2SMEN ,SPI2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGSMEN ,Window watchdog clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 10. " RTCAPBSMEN ,RTC APB clock enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 5. " TIM7SMEN ,TIM7 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TIM6SMEN ,TIM6 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2SMEN ,TIM2 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" else group.long 0x78++0x03 line.long 0x00 "RCC_APB1SMENR1,APB1 peripheral clocks enable in Sleep and Stop modes register 1" bitfld.long 0x00 31. " LPTIM1SMEN ,Low power timer 1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 30. " OPAMPSMEN ,OPAMP interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 29. " DAC1SMEN ,DAC1 interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 28. " PWRSMEN ,Power interface clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " USBFSSMEN ,USB FS clock enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 25. " CAN1SMEN ,CAN1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 24. " CRSSMEN ,CRS clock enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 23. " I2C3SMEN ,I2C3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " I2C2SMEN ,I2C2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 21. " I2C1SMEN ,I2C1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 18. " USART3SMEN ,USART3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 17. " USART2SMEN ,USART2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPI3SMEN ,SPI3 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 14. " SPI2SMEN ,SPI2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " WWDGSMEN ,Window watchdog clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 10. " RTCAPBSMEN ,RTC APB clock enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " LCDSMEN ,LCD clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 5. " TIM7SMEN ,TIM7 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 4. " TIM6SMEN ,TIM6 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " TIM2SMEN ,TIM2 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" endif group.long 0x7C++0x03 line.long 0x00 "RCC_APB1SMENR2,APB1 peripheral clocks enable in Sleep and Stop modes register 2" bitfld.long 0x00 5. " LPTIM2SMEN ,Low power timer 2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " sif (!cpuis("STM32L43*"))&&(!cpuis("STM32L44*")) bitfld.long 0x00 2. " SWPMI1SMEN ,Single wire protocol clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 1. " I2C4SMEN ,I2C4 clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " endif bitfld.long 0x00 0. " LPUART1SMEN ,Low power UART 1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" sif (cpuis("STM32L4?2*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x80++0x03 line.long 0x00 "RCC_APB2SMENR,APB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 21. " SAI1SMEN ,SAI1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 17. " TIM16SMEN ,TIM16 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 16. " TIM15SMEN ,TIM15 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 14. " USART1SMEN ,USART1clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SPI1SMEN ,SPI1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " TIM1SMEN ,TIM1 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 10. " SDMMC1SMEN ,SDMMC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " SYSCFGSMEN ,SYSCFG clocks enable during Sleep and Stop modes" "Disabled,Enabled" elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*")) group.long 0x80++0x03 line.long 0x00 "RCC_APB2SMENR,APB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 21. " SAI1SMEN ,SAI1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 17. " TIM16SMEN ,TIM16 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 16. " TIM15SMEN ,TIM15 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 14. " USART1SMEN ,USART1clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SPI1SMEN ,SPI1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " TIM1SMEN ,TIM1 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 10. " SDMMCSMEN ,SDMMC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " SYSCFGSMEN ,SYSCFG clocks enable during Sleep and Stop modes" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "RCC_APB2SMENR,APB2 peripheral clocks enable in Sleep and Stop modes register" bitfld.long 0x00 24. " DFSDMSMEN ,DFSDM timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 22. " SAI2SMEN ,SAI2 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 21. " SAI1SMEN ,SAI1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 18. " TIM17SMEN ,TIM17 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " TIM16SMEN ,TIM16 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 16. " TIM15SMEN ,TIM15 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 14. " USART1SMEN ,USART1clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 13. " TIM8SMEN ,TIM8 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " SPI1SMEN ,SPI1 clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 11. " TIM1SMEN ,TIM1 timer clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 10. " SDMMCSMEN ,SDMMC clocks enable during Sleep and Stop modes" "Disabled,Enabled" bitfld.long 0x00 0. " SYSCFGSMEN ,SYSCFG clocks enable during Sleep and Stop modes" "Disabled,Enabled" endif sif (cpuis("STM32L4?2*")) group.long 0x88++0x03 line.long 0x00 "RCC_CCIPR,Peripherals independent clock configuration register" bitfld.long 0x00 30. " SWPMI1SEL ,SWPMI1 clock source selection" "PCLK,HSI" bitfld.long 0x00 28.--29. " ADCSEL ,ADCs clock source selection" "No clock,PLLADC1CLK,,SYSCLK" bitfld.long 0x00 26.--27. " CLK48SEL ,48 MHz clock source selection" "HSI48,PLL48M2CLK,PLL48M1CLK,MSI" bitfld.long 0x00 22.--23. " SAI1SEL ,SAI1 clock source selection" "PLLSAI1CLK,,PLLSAI3CLK,SAI1_EXTCLK" textline " " bitfld.long 0x00 20.--21. " LPTIM2SEL ,Low power timer 2 clock source selection" "PCLK,LSI,HSI,LSE" bitfld.long 0x00 18.--19. " LPTIM1SEL ,Low power timer 1 clock source selection" "PCLK,LSI,HSI,LSE" bitfld.long 0x00 16.--17. " I2C3SEL ,I2C3 clock source selection" "PCLK,SYSCLK,HSI,?..." bitfld.long 0x00 12.--13. " I2C1SEL ,I2C1 clock source selection" "PCLK,SYSCLK,HSI,?..." textline " " bitfld.long 0x00 10.--11. " LPUART1SEL ,LPUART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 2.--3. " USART2SEL ,USART2 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 0.--1. " USART1SEL ,USART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*")) group.long 0x88++0x03 line.long 0x00 "RCC_CCIPR,Peripherals independent clock configuration register" bitfld.long 0x00 30. " SWPMI1SEL ,SWPMI1 clock source selection" "PCLK,HSI" bitfld.long 0x00 28.--29. " ADCSEL ,ADCs clock source selection" "No clock,PLLADC1CLK,,SYSCLK" bitfld.long 0x00 26.--27. " CLK48SEL ,48 MHz clock source selection" "HSI48,PLL48M2CLK,PLL48M1CLK,MSI" bitfld.long 0x00 22.--23. " SAI1SEL ,SAI1 clock source selection" "PLLSAI1CLK,,PLLSAI3CLK,SAI1_EXTCLK" textline " " bitfld.long 0x00 20.--21. " LPTIM2SEL ,Low power timer 2 clock source selection" "PCLK,LSI,HSI,LSE" bitfld.long 0x00 18.--19. " LPTIM1SEL ,Low power timer 1 clock source selection" "PCLK,LSI,HSI,LSE" bitfld.long 0x00 16.--17. " I2C3SEL ,I2C3 clock source selection" "PCLK,SYSCLK,HSI,?..." bitfld.long 0x00 14.--15. " I2C2SEL ,I2C2 clock source selection" "PCLK,SYSCLK,HSI,?..." textline " " bitfld.long 0x00 12.--13. " I2C1SEL ,I2C1 clock source selection" "PCLK,SYSCLK,HSI,?..." bitfld.long 0x00 10.--11. " LPUART1SEL ,LPUART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 4.--5. " USART3SEL ,USART3 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 2.--3. " USART2SEL ,UART2 clock source selection" "PCLK,SYSCLK,HSI,LSE" textline " " bitfld.long 0x00 0.--1. " USART1SEL ,USART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" elif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x88++0x03 line.long 0x00 "RCC_CCIPR,Peripherals independent clock configuration register" bitfld.long 0x00 28.--29. " ADCSEL ,ADCs clock source selection" "No clock,PLLADC1CLK,,SYSCLK" bitfld.long 0x00 26.--27. " CLK48SEL ,48 MHz clock source selection" "HSI48,PLL48M2CLK,PLL48M1CLK,MSI" bitfld.long 0x00 22.--23. " SAI1SEL ,SAI1 clock source selection" "PLLSAI1CLK,,PLLSAI3CLK,SAI1_EXTCLK" bitfld.long 0x00 20.--21. " LPTIM2SEL ,Low power timer 2 clock source selection" "PCLK,LSI,HSI,LSE" textline " " bitfld.long 0x00 18.--19. " LPTIM1SEL ,Low power timer 1 clock source selection" "PCLK,LSI,HSI,LSE" bitfld.long 0x00 16.--17. " I2C3SEL ,I2C3 clock source selection" "PCLK,SYSCLK,HSI,?..." bitfld.long 0x00 14.--15. " I2C2SEL ,I2C2 clock source selection" "PCLK,SYSCLK,HSI,?..." bitfld.long 0x00 12.--13. " I2C1SEL ,I2C1 clock source selection" "PCLK,SYSCLK,HSI,?..." textline " " bitfld.long 0x00 10.--11. " LPUART1SEL ,LPUART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 6.--7. " UART4SEL ,UART4 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 4.--5. " USART3SEL ,USART3 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 2.--3. " USART2SEL ,UART2 clock source selection" "PCLK,SYSCLK,HSI,LSE" textline " " bitfld.long 0x00 0.--1. " USART1SEL ,USART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" else group.long 0x88++0x03 line.long 0x00 "RCC_CCIPR,Peripherals independent clock configuration register" bitfld.long 0x00 31. " DFSDMSEL ,DFSDM clock source selection" "PCLK,SYSCLK" bitfld.long 0x00 30. " SWPMI1SEL ,SWPMI1 clock source selection" "PCLK,HSI" bitfld.long 0x00 28.--29. " ADCSEL ,ADCs clock source selection" "No clock,PLLADC1CLK,PLLADC2CLK,SYSCLK" bitfld.long 0x00 26.--27. " CLK48SEL ,48 MHz clock source selection" "No clock,PLLADC1CLK,PLLADC2CLK,ADC" textline " " bitfld.long 0x00 24.--25. " SAI2SEL ,SAI2 clock source selection" "PLLSAI1CLK,PLLSAI2CLK,PLLSAI3CLK,SAI2_EXTCLK" bitfld.long 0x00 22.--23. " SAI1SEL ,SAI1 clock source selection" "PLLSAI1CLK,PLLSAI2CLK,PLLSAI3CLK,SAI1_EXTCLK" bitfld.long 0x00 20.--21. " LPTIM2SEL ,Low power timer 2 clock source selection" "PCLK,LSI,HSI,LSE" bitfld.long 0x00 18.--19. " LPTIM1SEL ,Low power timer 1 clock source selection" "PCLK,LSI,HSI,LSE" textline " " bitfld.long 0x00 16.--17. " I2C3SEL ,I2C3 clock source selection" "PCLK,SYSCLK,HSI," bitfld.long 0x00 14.--15. " I2C2SEL ,I2C2 clock source selection" "PCLK,SYSCLK,HSI," bitfld.long 0x00 12.--13. " I2C1SEL ,I2C1 clock source selection" "PCLK,SYSCLK,HSI," bitfld.long 0x00 10.--11. " LPUART1SEL ,LPUART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" textline " " bitfld.long 0x00 8.--9. " UART5SEL ,UART5 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 6.--7. " UART4SEL ,UART4 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 4.--5. " UART3SEL ,UART3 clock source selection" "PCLK,SYSCLK,HSI,LSE" bitfld.long 0x00 2.--3. " UART2SEL ,UART2 clock source selection" "PCLK,SYSCLK,HSI,LSE" textline " " bitfld.long 0x00 0.--1. " UART1SEL ,UART1 clock source selection" "PCLK,SYSCLK,HSI,LSE" endif if (((per.l(ad:0x40007000))&0x100)==0x100) group.long 0x90++0x03 line.long 0x00 "RCC_BDCR,Backup domain control register" bitfld.long 0x00 25. " LSCOSEL ,Low speed clock output selection" "LSI,LSE" bitfld.long 0x00 24. " LSCOEN ,Low speed clock output enable" "Disabled,Enabled" bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "Not reset,Reset" bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSEdiv32" rbitfld.long 0x00 6. " LSECSSD ,CSS on LSE failure Detection" "No failure,Failure detected" bitfld.long 0x00 5. " LSECSSON ,CSS on LSE enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability. XTAL mode" "Lower,Medium low,Medium high,Higher" textline " " bitfld.long 0x00 2. " LSEBYP ,LSE oscillator bypass" "Not bypassed,Bypassed" rbitfld.long 0x00 1. " LSERDY ,LSE oscillator ready" "Not ready,Ready" bitfld.long 0x00 0. " LSEON ,LSE oscillator enable" "Disabled,Enabled" else rgroup.long 0x90++0x03 line.long 0x00 "RCC_BDCR,Backup domain control register" bitfld.long 0x00 25. " LSCOSEL ,Low speed clock output selection" "LSI,LSE" bitfld.long 0x00 24. " LSCOEN ,Low speed clock output enable" "Disabled,Enabled" bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "Not reset,Reset" bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSEdiv32" bitfld.long 0x00 6. " LSECSSD ,CSS on LSE failure Detection" "No failure,Failure detected" bitfld.long 0x00 5. " LSECSSON ,CSS on LSE enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability. XTAL mode" "Lower,Medium low,Medium high,Higher" textline " " bitfld.long 0x00 2. " LSEBYP ,LSE oscillator bypass" "Not bypassed,Bypassed" bitfld.long 0x00 1. " LSERDY ,LSE oscillator ready" "Not ready,Ready" bitfld.long 0x00 0. " LSEON ,LSE oscillator enable" "Disabled,Enabled" endif if (((per.l(ad:0x40021000))&0x08)==0x08) group.long 0x94++0x03 line.long 0x00 "RCC_CSR,Control/status register" rbitfld.long 0x00 31. " LPWRRSTF ,Low-power reset flag" "No reset,Reset" rbitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "No reset,Reset" rbitfld.long 0x00 29. " IWDGRSTF ,Independent window watchdog reset flag" "No reset,Reset" rbitfld.long 0x00 28. " SFTRSTF ,Software reset flag" "No reset,Reset" textline " " rbitfld.long 0x00 27. " BORRSTF ,BOR flag" "Not occurred,Occurred" rbitfld.long 0x00 26. " PINRSTF ,Pin reset flag" "No reset,Reset" rbitfld.long 0x00 25. " OBLRSTF ,Option byte loader reset flag" "No reset,Reset" rbitfld.long 0x00 24. " FWRSTF ,Firewall reset flag" "No reset,Reset" textline " " bitfld.long 0x00 23. " RMVF ,Remove reset flag" "No effect,All cleared" bitfld.long 0x00 8.--11. " MSISRANGE ,MSI range after Standby mode. Range / Freq" ",,,,R4/1MHz,R5/2MHz,R6/4MHz,R7/8MHz,?..." rbitfld.long 0x00 1. " LSIRDY ,LSI oscillator ready" "Not ready,Ready" bitfld.long 0x00 0. " LSION ,LSI oscillator enable" "Disabled,Enabled" else group.long 0x94++0x03 line.long 0x00 "RCC_CSR,Control/status register" rbitfld.long 0x00 31. " LPWRRSTF ,Low-power reset flag" "No reset,Reset" rbitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "No reset,Reset" rbitfld.long 0x00 29. " IWDGRSTF ,Independent window watchdog reset flag" "No reset,Reset" rbitfld.long 0x00 28. " SFTRSTF ,Software reset flag" "No reset,Reset" textline " " rbitfld.long 0x00 27. " BORRSTF ,BOR flag" "Not occurred,Occurred" rbitfld.long 0x00 26. " PINRSTF ,Pin reset flag" "No reset,Reset" rbitfld.long 0x00 25. " OBLRSTF ,Option byte loader reset flag" "No reset,Reset" rbitfld.long 0x00 24. " FWRSTF ,Firewall reset flag" "No reset,Reset" textline " " bitfld.long 0x00 23. " RMVF ,Remove reset flag" "No effect,All cleared" rbitfld.long 0x00 8.--11. " MSISRANGE ,MSI range after Standby mode. Range / Freq" ",,,,R4/1MHz,R5/2MHz,R6/4MHz,R7/8MHz,?..." rbitfld.long 0x00 1. " LSIRDY ,LSI oscillator ready" "Not ready,Ready" bitfld.long 0x00 0. " LSION ,LSI oscillator enable" "Disabled,Enabled" endif sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*")) group.long 0x98++0x03 line.long 0x00 "RCC_CRRCR,Clock recovery RC register" hexmask.long.word 0x00 7.--15. 1. " HSI48CAL ,HSI48 clock calibration" rbitfld.long 0x00 1. " HSI48RDY ,HSI48 clock ready flag" "Not ready,Ready" bitfld.long 0x00 0. " HSI48ON ,HSI48 clock enable" "OFF,ON" endif sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x9C++0x03 line.long 0x00 "RCC_CCIPR2,Peripherals independent clock configuration register" bitfld.long 0x00 0.--1. " I2C4SEL ,I2C4 clock source selection" "PCLK,SYSCLK,HSI16,?..." endif width 0x0B tree.end sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*")) tree "CRS (Clock recovery system)" base ad:0x40006000 width 10. if (((per.l(ad:0x40006000))&0x40)==0x40) group.long 0x00++0x03 line.long 0x00 "CRS_CR,CRS Control Register" rbitfld.long 0x00 8.--13. " TRIM ,HSI48 oscillator smooth trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " SWSYNC ,Generate software SYNC event" "Not generated,Generated" bitfld.long 0x00 6. " AUTOTRIMEN ,Automatic trimming enable" "Disabled,Enabled" bitfld.long 0x00 5. " CEN ,Frequency error counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ESYNCIE ,Expected SYNC interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " ERRIE ,Synchronization or trimming error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " SYNCWARNIE ,SYNC warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " SYNCOKIE ,SYNC event OK interrupt enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CRS_CR,CRS Control Register" bitfld.long 0x00 8.--13. " TRIM ,HSI48 oscillator smooth trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 7. " SWSYNC ,Generate software SYNC event" "Not generated,Generated" bitfld.long 0x00 6. " AUTOTRIMEN ,Automatic trimming enable" "Disabled,Enabled" bitfld.long 0x00 5. " CEN ,Frequency error counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ESYNCIE ,Expected SYNC interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " ERRIE ,Synchronization or trimming error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " SYNCWARNIE ,SYNC warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " SYNCOKIE ,SYNC event OK interrupt enable" "Disabled,Enabled" endif if (((per.l(ad:0x40006000))&0x20)==0x20) rgroup.long 0x04++0x03 line.long 0x00 "CRS_CFGR,CRS Configuration Register" bitfld.long 0x00 31. " SYNCPOL ,SYNC polarity selection" "Rising,Falling" textline " " sif (cpuis("STM32L431*")) bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,?..." textline " " else bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,USB SOF,?..." textline " " endif bitfld.long 0x00 24.--26. " SYNCDIV ,SYNC divider" "SYNC,SYNC/2,SYNC/4,SYNC/8,SYNC/16,SYNC/32,SYNC/64,SYNC/128" hexmask.long.byte 0x00 16.--23. 1. " FELIM ,Frequency error limit" hexmask.long.word 0x00 0.--15. 1. " RELOAD ,Counter reload value" else group.long 0x04++0x03 line.long 0x00 "CRS_CFGR,CRS Configuration Register" bitfld.long 0x00 31. " SYNCPOL ,SYNC polarity selection" "Rising,Falling" textline " " sif (cpuis("STM32L431*")) bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,?..." textline " " else bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,USB SOF,?..." textline " " endif bitfld.long 0x00 24.--26. " SYNCDIV ,SYNC divider" "SYNC,SYNC/2,SYNC/4,SYNC/8,SYNC/16,SYNC/32,SYNC/64,SYNC/128" hexmask.long.byte 0x00 16.--23. 1. " FELIM ,Frequency error limit" hexmask.long.word 0x00 0.--15. 1. " RELOAD ,Counter reload value" endif rgroup.long 0x08++0x03 line.long 0x00 "CRS_ISR,CRS Interrupt And Status Register" hexmask.long.word 0x00 16.--31. 1. " FECAP ,Frequency error capture" bitfld.long 0x00 15. " FEDIR ,Frequency error direction" "Upcounting,Downcounting" bitfld.long 0x00 10. " TRIMOVF ,Trimming overflow or underflow" "No trimming,Trimming" bitfld.long 0x00 9. " SYNCMISS ,SYNC missed" "No SYNC,SYNC" textline " " bitfld.long 0x00 8. " SYNCERR ,SYNC error" "No error,Error" bitfld.long 0x00 3. " ESYNCF ,Expected SYNC flag" "Not expected,Expected" bitfld.long 0x00 2. " ERRF ,Error flag" "No error,Error" bitfld.long 0x00 1. " SYNCWARNF ,SYNC warning flag" "No error,Error" textline " " bitfld.long 0x00 0. " SYNCOKF ,SYNC event OK flag" "No SYNC,SYNC" group.long 0x0C++0x03 line.long 0x00 "CRS_ICR,CRS Interrupt Flag Clear Register" bitfld.long 0x00 3. " ESYNCC ,Expected SYNC clear flag" "No effect,Clear" bitfld.long 0x00 2. " ERRC ,Error clear flag" "No effect,Clear" bitfld.long 0x00 1. " SYNCWARNC ,SYNC warning clear flag" "No effect,Clear" bitfld.long 0x00 0. " SYNCOKC ,SYNC event OK clear flag" "No effect,Clear" width 0x0B tree.end endif tree "GPIO (General-purpose I/Os)" tree "GPIO A" base ad:0x48000000 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOA_MODER,GPIO port mode register" bitfld.long 0x00 30.--31. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 26.--27. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 22.--23. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 20.--21. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 14.--15. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 4.--5. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 2.--3. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port A configuration bits" "Input,Gen purp output,Alt function,Analog" line.long 0x04 "GPIOA_OTYPER,GPIO port output type register" bitfld.long 0x04 15. " OT15 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 13. " OT13 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port A configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 11. " OT11 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 10. " OT10 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port A configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 7. " OT7 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port A configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 1. " OT1 ,Port A configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port A configuration bits" "Push-pull,Open-drain" line.long 0x08 "GPIOA_OSPEEDR,GPIO port output speed register" bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port A configuration bits" "Low,Medium,High,Very high" line.long 0x0C "GPIOA_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port A configuration bits" "No pulls,Pull-up,Pull-down,?..." rgroup.long 0x10++0x03 line.long 0x00 "GPIOA_IDR,GPIO port input data register" bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" textline " " bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIOA_ODR,GPIO port output data register" bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" textline " " bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" wgroup.long 0x18++0x03 line.long 0x00 "GPIOA_BSRR,GPIO port bit set/reset register" bitfld.long 0x00 31. " BR15 ,Port A reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port A reset bit 14" "No effect,Reset" bitfld.long 0x00 29. " BR13 ,Port A reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port A reset bit 12" "No effect,Reset" textline " " bitfld.long 0x00 27. " BR11 ,Port A reset bit 11" "No effect,Reset" bitfld.long 0x00 26. " BR10 ,Port A reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port A reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port A reset bit 8" "No effect,Reset" textline " " bitfld.long 0x00 23. " BR7 ,Port A reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port A reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port A reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port A reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port A reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port A reset bit 2" "No effect,Reset" bitfld.long 0x00 17. " BR1 ,Port A reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port A reset bit 0" "No effect,Reset" textline " " bitfld.long 0x00 15. " BS15 ,Port A set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port A set bit 14" "No effect,Set" bitfld.long 0x00 13. " BS13 ,Port A set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port A set bit 12" "No effect,Set" textline " " bitfld.long 0x00 11. " BS11 ,Port A set bit 11" "No effect,Set" bitfld.long 0x00 10. " BS10 ,Port A set bit 10" "No effect,Set" bitfld.long 0x00 9. " BS9 ,Port A set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port A set bit 8" "No effect,Set" textline " " bitfld.long 0x00 7. " BS7 ,Port A set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port A set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port A set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port A set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port A set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port A set bit 2" "No effect,Set" bitfld.long 0x00 1. " BS1 ,Port A set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port A set bit 0" "No effect,Set" group.long 0x1C++0x03 line.long 0x00 "GPIOA_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" bitfld.long 0x00 15. " LCK15 ,Port A lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port A lock bit 14" "Not locked,Locked" bitfld.long 0x00 13. " LCK13 ,Port A lock bit 13" "Not locked,Locked" textline " " bitfld.long 0x00 12. " LCK12 ,Port A lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port A lock bit 11" "Not locked,Locked" bitfld.long 0x00 10. " LCK10 ,Port A lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port A lock bit 9" "Not locked,Locked" textline " " bitfld.long 0x00 8. " LCK8 ,Port A lock bit 8" "Not locked,Locked" bitfld.long 0x00 7. " LCK7 ,Port A lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port A lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port A lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port A lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port A lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port A lock bit 2" "Not locked,Locked" bitfld.long 0x00 1. " LCK1 ,Port A lock bit 1" "Not locked,Locked" textline " " bitfld.long 0x00 0. " LCK0 ,Port A lock bit 0" "Not locked,Locked" textline " " width 15. sif (cpuis("STM32L433*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,,,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,LCD_SEG4,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,LCD_SEG3,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,LCD_SEG2,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,LCD_SEG1,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,,,,LCD_SEG0,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,,TSC_G3_IO1,,LCD_SEG17,SWPMI1_SUSPEND,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,SWPMI1_RX,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,USB_NOE,,SWPMI1_TX,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,USB_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USB_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,LCD_COM2,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,,USART1_TX,,,,LCD_COM1,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,,LCD_COM0,SWPMI1_IO,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L431*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,,,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,,TSC_G3_IO1,,,SWPMI1_SUSPEND,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,SWPMI1_RX,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,,,SWPMI1_TX,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,,,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,,,SWPMI1_IO,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L471*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,,,,TIM17_CH1,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,USART3_CTS,,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,TIM8_BKIN_COMP2,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,TIM8_CH1N,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,,,,,USART2_RX,,,,,,,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,,,,,USART2_TX,,,,,,SAI2_EXTCLK,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS_DE,UART4_RX,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,,,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,,,SPI1_NSS,SPI3_NSS,,UART4_RTS_DE,TSC_G3_IO1,,,,SAI2_FS_B,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS_DE,,CAN1_TX,,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,,,USART1_CTS,,,,,,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,,,,,TIM17_BKIN,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,,,,USART1_TX,,,,,,,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,,,,,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L475*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,,,,TIM17_CH1,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,USART3_CTS,,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,TIM8_BKIN_COMP2,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,TIM8_CH1N,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,,,,,USART2_RX,,,,,,,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,,,,,USART2_TX,,,,,,SAI2_EXTCLK,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,,,,USART2_RTS_DE,UART4_RX,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,,,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,,,SPI1_NSS,SPI3_NSS,,UART4_RTS_DE,TSC_G3_IO1,,,,SAI2_FS_B,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,OTG_FS_NOE,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,,,USART1_RTS_DE,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,,TIM17_BKIN,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,,,,USART1_TX,,,,,,,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,OTG_FS_SOF,,,,,,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L442KC")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,,,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,,TSC_G3_IO1,,,SWPMI1_SUSPEND,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,SWPMI1_RX,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,USB_NOE,,SWPMI1_TX,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,USB_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USB_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,,,SWPMI1_IO,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L443*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,,,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,LCD_SEG4,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,LCD_SEG3,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,LCD_SEG2,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,LCD_SEG1,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,,,,LCD_SEG0,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,,TSC_G3_IO1,,LCD_SEG17,SWPMI1_SUSPEND,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,SWPMI1_RX,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,USB_NOE,,SWPMI1_TX,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,USB_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USB_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,LCD_COM2,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,,USART1_TX,,,,LCD_COM1,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,,LCD_COM0,SWPMI1_IO,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,TIM8_CH1N,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,LCD_SEG4,,,TIM17_CH1,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,DCMI_PIXCLK,SPI1_MISO,,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,LCD_SEG3,TIM1_BKIN_COMP2,TIM8_BKIN_COMP2,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,TIM8_CH1N,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,DCMI_HSYNC,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,LCD_SEG2,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,LCD_SEG1,,SAI2_EXTCLK,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,UART4_RX,,,LCD_SEG0,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,,,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,UART4_RTS_DE,TSC_G3_IO1,,LCD_SEG17,SWPMI1_SUSPEND,SAI2_FS_B,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,I2C4_SMBA,,,,,OTG_FS_SOF,,SWPMI1_RX,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,OTG_FS_NOE,,SWPMI1_TX,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,DCMI_D1,,USART1_RX,,,OTG_FS_ID,LCD_COM2,,SAI1_SD_A,TIM17_BKIN,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,SPI2_SCK,I2C1_SCL,DCMI_D0,,USART1_TX,,,,LCD_COM1,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,OTG_FS_SOF,LCD_COM0,SWPMI1_IO,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L462*")||cpuis("STM32L452*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,,I2C3_SCL,SPI1_MOSI,DFSDM1_DATIN0,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,DFSDM1_CKOUT,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,UART4_RX,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,UART4_TX,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,UART4_RTS_DE,TSC_G3_IO1,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,I2C4_SMBA,,,,,,,,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS/SWDAT,IR_OUT,,,,,,,,,USB_NOE,,,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,USB_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USB_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,DFSDM1_DATIN1,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,DFSDM1_CKIN1,USART1_CK,,,,,,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" elif (cpuis("STM32L451*")) group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,TIM3_CH2,,I2C3_SCL,SPI1_MOSI,DFSDM1_DATIN0,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,TIM3_CH1,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,DFSDM1_CKOUT,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,UART4_RX,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,UART4_TX,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,UART4_RTS_DE,TSC_G3_IO1,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,I2C4_SMBA,,,,,,,,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS/SWDAT,IR_OUT,,,,,,,,,,,,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,,,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,DFSDM1_DATIN1,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,DFSDM1_CKIN1,USART1_CK,,,,,,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" else group.long 0x20++0x07 line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port A pin 7" ",TIM1_CH1N,,,I2C3_SCL,SPI1_MOSI,,,,,QUADSPI_BK1_IO2,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port A pin 6" ",TIM1_BKIN,,,,SPI1_MISO,COMP1_OUT,USART3_CTS,LPUART1_CTS,,QUADSPI_BK1_IO3,,TIM1_BKIN_COMP2,,TIM16_CH1,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port A pin 5" ",TIM2_CH1,TIM2_ETR,,,SPI1_SCK,,,,,,,,,LPTIM2_ETR,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port A pin 4" ",,,,,SPI1_NSS,SPI3_NSS,USART2_CK,,,,,,SAI1_FS_B,LPTIM2_OUT,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port A pin 3" ",TIM2_CH4,,,,,,USART2_RX,LPUART1_RX,,QUADSPI_CLK,,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port A pin 2" ",TIM2_CH3,,,,,,USART2_TX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port A pin 1" ",TIM2_CH2,,,I2C1_SMBA,SPI1_SCK,,USART2_RTS_DE,,,,,,,TIM15_CH1N,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port A pin 0" ",TIM2_CH1,,,,,,USART2_CTS,,,,,COMP1_OUT,SAI1_EXTCLK,TIM2_ETR,EVENTOUT" line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1,TIM2_ETR,USART2_RX,,SPI1_NSS,SPI3_NSS,USART3_RTS_DE,,TSC_G3_IO1,,,SWPMI1_SUSPEND,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port A pin 14" "JTCK-SWCLK,LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,SWPMI1_RX,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port A pin 13" "JTMS-SWDIO,IR_OUT,,,,,,,,,USB_NOE,,SWPMI1_TX,SAI1_SD_B,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port A pin 12" ",TIM1_ETR,,,,SPI1_MOSI,,USART1_RTS_DE,,CAN1_TX,USB_DP,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port A pin 11" ",TIM1_CH4,TIM1_BKIN2,,,SPI1_MISO,COMP1_OUT,USART1_CTS,,CAN1_RX,USB_DM,,TIM1_BKIN2_COMP1,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port A pin 10" ",TIM1_CH3,,,I2C1_SDA,,,USART1_RX,,,USB_CRS_SYNC,,,SAI1_SD_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port A pin 9" ",TIM1_CH2,,,I2C1_SCL,,,USART1_TX,,,,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port A pin 8" "MCO,TIM1_CH1,,,,,,USART1_CK,,,,,SWPMI1_IO,SAI1_SCK_A,LPTIM2_OUT,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOA_BRR,GPIO port bit reset register" bitfld.long 0x00 15. " BR15 ,Port A Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port A Reset bit 14" "No action,Reset" bitfld.long 0x00 13. " BR13 ,Port A Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port A Reset bit 12" "No action,Reset" textline " " bitfld.long 0x00 11. " BR11 ,Port A Reset bit 11" "No action,Reset" bitfld.long 0x00 10. " BR10 ,Port A Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port A Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port A Reset bit 8" "No action,Reset" textline " " bitfld.long 0x00 7. " BR7 ,Port A Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port A Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port A Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port A Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port A Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port A Reset bit 2" "No action,Reset" bitfld.long 0x00 1. " BR1 ,Port A Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port A Reset bit 0" "No action,Reset" sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOA_ASCR,GPIO port analog switch control register" bitfld.long 0x00 15. " ASC15 ,Port A Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port A Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port A Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port A Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port A Reset bit 11" "Disconnected,Connected" bitfld.long 0x00 10. " ASC10 ,Port A Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port A Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port A Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port A Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port A Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port A Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port A Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port A Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port A Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port A Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port A Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end tree "GPIO B" base ad:0x48000400 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOB_MODER,GPIO port mode register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 30.--31. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 26.--27. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 22.--23. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 20.--21. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " endif bitfld.long 0x00 14.--15. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 4.--5. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " endif bitfld.long 0x00 2.--3. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port B configuration bits" "Input,Gen purp output,Alt function,Analog" line.long 0x04 "GPIOB_OTYPER,GPIO port output type register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x04 15. " OT15 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 13. " OT13 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port B configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 11. " OT11 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 10. " OT10 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port B configuration bits" "Push-pull,Open-drain" textline " " endif bitfld.long 0x04 7. " OT7 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port B configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port B configuration bits" "Push-pull,Open-drain" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x04 2. " OT2 ,Port B configuration bits" "Push-pull,Open-drain" textline " " endif bitfld.long 0x04 1. " OT1 ,Port B configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port B configuration bits" "Push-pull,Open-drain" line.long 0x08 "GPIOB_OSPEEDR,GPIO port output speed register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" textline " " endif bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" textline " " endif bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port B configuration bits" "Low,Medium,High,Very high" line.long 0x0C "GPIOB_PUPDR,GPIO port pull-up/pull-down register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " endif bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " endif bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port B configuration bits" "No pulls,Pull-up,Pull-down,?..." rgroup.long 0x10++0x03 line.long 0x00 "GPIOB_IDR,GPIO port input data register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" textline " " bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " endif bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" textline " " endif bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIOB_ODR,GPIO port output data register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" textline " " bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " endif bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" textline " " endif bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" wgroup.long 0x18++0x03 line.long 0x00 "GPIOB_BSRR,GPIO port bit set/reset register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 31. " BR15 ,Port B reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port B reset bit 14" "No effect,Reset" bitfld.long 0x00 29. " BR13 ,Port B reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port B reset bit 12" "No effect,Reset" textline " " bitfld.long 0x00 27. " BR11 ,Port B reset bit 11" "No effect,Reset" bitfld.long 0x00 26. " BR10 ,Port B reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port B reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port B reset bit 8" "No effect,Reset" textline " " endif bitfld.long 0x00 23. " BR7 ,Port B reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port B reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port B reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port B reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port B reset bit 3" "No effect,Reset" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 18. " BR2 ,Port B reset bit 2" "No effect,Reset" textline " " endif bitfld.long 0x00 17. " BR1 ,Port B reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port B reset bit 0" "No effect,Reset" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 15. " BS15 ,Port B set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port B set bit 14" "No effect,Set" bitfld.long 0x00 13. " BS13 ,Port B set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port B set bit 12" "No effect,Set" textline " " bitfld.long 0x00 11. " BS11 ,Port B set bit 11" "No effect,Set" bitfld.long 0x00 10. " BS10 ,Port B set bit 10" "No effect,Set" bitfld.long 0x00 9. " BS9 ,Port B set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port B set bit 8" "No effect,Set" textline " " endif bitfld.long 0x00 7. " BS7 ,Port B set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port B set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port B set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port B set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port B set bit 3" "No effect,Set" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 2. " BS2 ,Port B set bit 2" "No effect,Set" textline " " endif bitfld.long 0x00 1. " BS1 ,Port B set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port B set bit 0" "No effect,Set" group.long 0x1C++0x03 line.long 0x00 "GPIOB_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 15. " LCK15 ,Port B lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port B lock bit 14" "Not locked,Locked" bitfld.long 0x00 13. " LCK13 ,Port B lock bit 13" "Not locked,Locked" bitfld.long 0x00 12. " LCK12 ,Port B lock bit 12" "Not locked,Locked" textline " " bitfld.long 0x00 11. " LCK11 ,Port B lock bit 11" "Not locked,Locked" bitfld.long 0x00 10. " LCK10 ,Port B lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port B lock bit 9" "Not locked,Locked" bitfld.long 0x00 8. " LCK8 ,Port B lock bit 8" "Not locked,Locked" textline " " endif bitfld.long 0x00 7. " LCK7 ,Port B lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port B lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port B lock bit 5" "Not locked,Locked" bitfld.long 0x00 4. " LCK4 ,Port B lock bit 4" "Not locked,Locked" textline " " bitfld.long 0x00 3. " LCK3 ,Port B lock bit 3" "Not locked,Locked" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 2. " LCK2 ,Port B lock bit 2" "Not locked,Locked" textline " " endif bitfld.long 0x00 1. " LCK1 ,Port B lock bit 1" "Not locked,Locked" bitfld.long 0x00 0. " LCK0 ,Port B lock bit 0" "Not locked,Locked" textline " " width 15. sif (cpuis("STM32L443*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,LCD_SEG21,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,LCD_SEG9,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,LCD_SEG8,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,LCD_SEG7,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" "RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,,,,,,LCD_VLCD,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,,,,,,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,LCD_SEG6,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,,,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,LCD_SEG5,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI,,,,TSC_G1_IO4,,LCD_SEG15,SWPMI1_SUSPEND,SAI1_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,,USART3_RTS_DE,,TSC_G1_IO3,,LCD_SEG,SWPMI1_RX,SAI1_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,LCD_SEG,SWPMI1_TX,SAI1_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,,LCD_SEG,SWPMI1_IO,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,LPUART1_TX,,QUADSPI_BK1_NCS,LCD_SEG,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK,,USART3_TX,LPUART1_RX,TSC_SYNC,QUADSPI_CLK,LCD_SEG,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,,,I2C1_SDA,SPI2_NSS,,,,CAN1_TX,,LCD_COM3,SDMMC1_D5,SAI1_FS_A,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,,,I2C1_SCL,,,,,CAN1_RX,,LCD_SEG16,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" elif (cpuis("STM32L442KC")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,,,,,,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT" textline " " bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,,,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" elif (cpuis("STM32L433R*"))||(cpuis("STM32L433C*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,LCD_SEG21,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,LCD_SEG9,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,LCD_SEG8,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDOTRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,LCD_SEG7,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" "RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,,,,,,LCD_VLCD,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,,,,,,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,LCD_SEG6,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,,,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,LCD_SEG5,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI,,,,TSC_G1_IO4,,LCD_SEG15,SWPMI1_SUSPEND,SAI1_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,,USART3_RTS_DE,,TSC_G1_IO3,,LCD_SEG14,SWPMI1_RX,SAI1_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,LCD_SEG13,SWPMI1_TX,SAI1_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,,LCD_SEG12,SWPMI1_IO,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,LPUART1_TX,,QUADSPI_BK1_NCS,LCD_SEG11,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK,,USART3_TX,LPUART1_RX,TSC_SYNC,QUADSPI_CLK,LCD_SEG10,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,,,I2C1_SDA,SPI2_NSS,,,,CAN1_TX,,LCD_COM3,SDMMC1_D5,SAI1_FS_A,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,,,I2C1_SCL,,,,,CAN1_RX,,LCD_SEG16,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" elif (cpuis("STM32L471*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,TIM4_CH2,TIM8_BKIN,I2C1_SDA,,DFSDM_CKIN5,USART1_RX,UART4_CTS,TSC_G2_IO4,,,FMC_NL,TIM8_BKIN_COMP1,TIM17_CH1N,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,TIM4_CH1,TIM8_BKIN2,I2C1_SCL,,DFSDM_DATIN5,USART1_TX,,TSC_G2_IO3,,,TIM8_BKIN2_COMP2,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,UART5_CTS,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,USART1_CTS,UART5_RTS_DE,TSC_G2_IO1,,,,SAI1_MCLK_B,TIM17_BKIN,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" "RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,DFSDM_CKIN0,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM_DATIN0,USART3_RTS_DE,,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI,DFSDM_CKIN2,,,TSC_G1_IO4,,,SWPMI1_SUSPEND,SAI2_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,I2C2_SDA,SPI2_MISO,DFSDM_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,,SWPMI1_RX,SAI2_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,,SWPMI1_TX,SAI2_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM_DATIN1,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,,,SWPMI1_IO,SAI2_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM_CKIN7,USART3_RX,LPUART1_TX,,QUADSPI_NCS,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK,DFSDM_DATIN7,USART3_TX,LPUART1_RX,,QUADSPI_CLK,,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,TIM4_CH4,,I2C1_SDA,SPI2_NSS,DFSDM_CKIN6,,,CAN1_TX,,,SDMMC1_D5,SAI1_FS_A,TIM17_CH1,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,,I2C1_SCL,,DFSDM_DATIN6,,,CAN1_RX,,,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" elif (cpuis("STM32L475*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,TIM4_CH2,TIM8_BKIN,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,UART4_CTS,TSC_G2_IO4,,,FMC_NL,TIM8_BKIN_COMP1,TIM17_CH1N,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,TIM4_CH1,TIM8_BKIN2,I2C1_SCL,,DFSDM1_DATIN5,USART1_TX,,TSC_G2_IO3,,,TIM8_BKIN2_COMP2,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,UART5_CTS,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,USART1_CTS,UART5_RTS_DE,TSC_G2_IO1,,,,SAI1_MCLK_B,TIM17_BKIN,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" "RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,DFSDM1_CKIN0,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN0,USART3_RTS_DE,,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI,DFSDM1_CKIN2,,,TSC_G1_IO4,,,SWPMI1_SUSPEND,SAI2_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,I2C2_SDA,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,,SWPMI1_RX,SAI2_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM1_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,,SWPMI1_TX,SAI2_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM1_DATIN1,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,,,SWPMI1_IO,SAI2_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,LPUART1_TX,,QUADSPI_NCS,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK,DFSDM1_DATIN7,USART3_TX,LPUART1_RX,,QUADSPI_CLK,,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,TIM4_CH4,,I2C1_SDA,SPI2_NSS,DFSDM1_CKIN6,,,CAN1_TX,,,SDMMC1_D5,SAI1_FS_A,TIM17_CH1,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,,I2C1_SCL,,DFSDM1_DATIN6,,,CAN1_RX,,,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" elif (cpuis("STM32L431K*"))||(cpuis("STM32L432*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDOTRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,,,,,,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT" textline " " bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,,,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" elif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,TIM4_CH2,TIM8_BKIN,I2C1_SDA,I2C4_SDA,DFSDM1_CKIN5,USART1_RX,UART4_CTS,TSC_G2_IO4,DCMI_VSYNC,LCD_SEG21,FMC_NL,TIM8_BKIN_COMP1,TIM17_CH1N,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,TIM4_CH1,TIM8_BKIN2,I2C1_SCL,I2C4_SCL,DFSDM1_DATIN5,USART1_TX,CAN2_TX,TSC_G2_IO3,DCMI_D5,,TIM8_BKIN2_COMP2,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,TIM3_CH2,CAN2_RX,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,UART5_CTS,TSC_G2_IO2,DCMI_D10,LCD_SEG9,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,UART5_RTS_DE,TSC_G2_IO1,DCMI_D12,LCD_SEG8,,SAI1_MCLK_B,TIM17_BKIN,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,OTG_FS_CRS_SYNC,LCD_SEG7,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" ",TIM2_CH3,TIM5_CH3,,,,,USART2_TX,,,,LCD_VLCD,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN0,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,LCD_SEG6,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,LCD_SEG5,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI,DFSDM1_CKIN2,,,TSC_G1_IO4,,,SWPMI1_SUSPEND,SAI2_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,TIM8_CH2N,I2C2_SDA,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,,SWPMI1_RX,SAI2_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM1_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,,SWPMI1_TX,SAI2_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM1_DATIN1,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,,,SWPMI1_IO,SAI2_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,LPUART1_TX,,QUADSPI_NCS,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK,DFSDM1_DATIN7,USART3_TX,LPUART1_RX,,QUADSPI_CLK,,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,TIM4_CH4,,I2C1_SDA,SPI2_NSS,DFSDM1_CKIN6,,,CAN1_TX,,,SDMMC1_D5,SAI1_FS_A,TIM17_CH1,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,TIM4_CH3,,I2C1_SCL,,DFSDM1_DATIN6,,,CAN1_RX,,,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" elif (cpuis("STM32L462*")||cpuis("STM32L452*")||cpuis("STM32L451*")) group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,,,I2C1_SDA,I2C4_SDA,,USART1_RX,UART4_CTS,TSC_G2_IO4,,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,,,I2C1_SCL,I2C4_SCL,,USART1_TX,CAN1_TX,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,TIM3_CH2,CAN1_RX,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,TIM3_CH1,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" "RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,DFSDM1_CKIN0,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,TIM3_CH4,,,,DFSDM1_DATIN0,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,TIM3_CH3,,,SPI1_NSS,DFSDM1_CKIN0,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI,DFSDM1_CKIN2,,,TSC_G1_IO4,,,,SAI1_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,DFSDM1_DATIN2,USART3_RTS_DE,,TSC_G1_IO3,,,,SAI1_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,DFSDM1_CKIN1,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,CAN1_TX,,,SAI1_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,DFSDM1_DATIN1,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,CAN1_RX,,,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,I2C4_SDA,I2C2_SDA,,,USART3_RX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,I2C4_SCL,I2C2_SCL,SPI2_SCK,,USART3_TX,LPUART1_RX,TSC_SYNC,QUADSPI_CLK,,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,,,I2C1_SDA,SPI2_NSS,,,,CAN1_TX,,,SDMMC1_D5,SAI1_FS_A,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,,,I2C1_SCL,,,,,CAN1_RX,,,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" else group.long 0x20++0x07 line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port B pin 7" ",LPTIM1_IN2,,,I2C1_SDA,,,USART1_RX,,TSC_G2_IO4,,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port B pin 6" ",LPTIM1_ETR,,,I2C1_SCL,,,USART1_TX,,TSC_G2_IO3,,,,SAI1_FS_B,TIM16_CH1N,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port B pin 5" ",LPTIM1_IN1,,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI,USART1_CK,,TSC_G2_IO2,,,COMP2_OUT,SAI1_SD_B,TIM16_BKIN,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port B pin 4" "NJTRST,,,,I2C3_SDA,SPI1_MISO,SPI3_MISO,USART1_CTS,,TSC_G2_IO1,,,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port B pin 3" "JTDOTRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK,USART1_RTS_DE,,,,,,SAI1_SCK_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port B pin 2" "RTC_OUT,LPTIM1_OUT,,,I2C3_SMBA,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port B pin 1" ",TIM1_CH3N,,,,,,USART3_RTS_DE,LPUART1_RTS_DE,,QUADSPI_BK1_IO0,,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port B pin 0" ",TIM1_CH2N,,,,SPI1_NSS,,USART3_CK,,,QUADSPI_BK1_IO1,,COMP1_OUT,SAI1_EXTCLK,,EVENTOUT" line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI,,,,TSC_G1_IO4,,,SWPMI1_SUSPEND,SAI1_SD_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port B pin 14" ",TIM1_CH2N,,,I2C2_SDA,SPI2_MISO,,USART3_RTS_DE,,TSC_G1_IO3,,,SWPMI1_RX,SAI1_MCLK_A,TIM15_CH1,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port B pin 13" ",TIM1_CH1N,,,I2C2_SCL,SPI2_SCK,,USART3_CTS,LPUART1_CTS,TSC_G1_IO2,,,SWPMI1_TX,SAI1_SCK_A,TIM15_CH1N,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port B pin 12" ",TIM1_BKIN,,TIM1_BKIN_COMP2,I2C2_SMBA,SPI2_NSS,,USART3_CK,LPUART1_RTS_DE,TSC_G1_IO1,,,SWPMI1_IO,SAI1_FS_A,TIM15_BKIN,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port B pin 11" ",TIM2_CH4,,,I2C2_SDA,,,USART3_RX,LPUART1_TX,,QUADSPI_BK1_NCS,,COMP2_OUT,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port B pin 10" ",TIM2_CH3,,,I2C2_SCL,SPI2_SCK,,USART3_TX,LPUART1_RX,TSC_SYNC,QUADSPI_CLK,,COMP1_OUT,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port B pin 9" ",IR_OUT,,,I2C1_SDA,SPI2_NSS,,,,CAN1_TX,,,SDMMC1_D5,SAI1_FS_A,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port B pin 8" ",,,,I2C1_SCL,,,,,CAN1_RX,,,SDMMC1_D4,SAI1_MCLK_A,TIM16_CH1,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOB_BRR,GPIO port bit reset register" sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 15. " BR15 ,Port B Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port B Reset bit 14" "No action,Reset" bitfld.long 0x00 13. " BR13 ,Port B Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port B Reset bit 12" "No action,Reset" textline " " bitfld.long 0x00 11. " BR11 ,Port B Reset bit 11" "No action,Reset" bitfld.long 0x00 10. " BR10 ,Port B Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port B Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port B Reset bit 8" "No action,Reset" textline " " endif bitfld.long 0x00 7. " BR7 ,Port B Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port B Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port B Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port B Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port B Reset bit 3" "No action,Reset" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 2. " BR2 ,Port B Reset bit 2" "No action,Reset" textline " " endif bitfld.long 0x00 1. " BR1 ,Port B Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port B Reset bit 0" "No action,Reset" sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOB_ASCR,GPIO port analog switch control register" bitfld.long 0x00 15. " ASC15 ,Port B Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port B Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port B Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port B Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port B Reset bit 11" "Disconnected,Connected" bitfld.long 0x00 10. " ASC10 ,Port B Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port B Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port B Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port B Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port B Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port B Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port B Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port B Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port B Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port B Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port B Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end tree "GPIO C" base ad:0x48000800 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOC_MODER,GPIO port mode register" bitfld.long 0x00 30.--31. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 26.--27. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 24.--25. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 22.--23. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 20.--21. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 16.--17. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 14.--15. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 8.--9. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 6.--7. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 4.--5. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 2.--3. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 0.--1. " MODE[1:0] ,Port C configuration bits" "Input,Gen purp output,Alt function,Analog" endif line.long 0x04 "GPIOC_OTYPER,GPIO port output type register" bitfld.long 0x04 15. " OT15 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port C configuration bits" "Push-pull,Open-drain" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x04 13. " OT13 ,Port C configuration bits" "Push-pull,Open-drain" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x04 12. " OT12 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 11. " OT11 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 10. " OT10 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port C configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 8. " OT8 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 7. " OT7 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port C configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 4. " OT4 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 3. " OT3 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port C configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 1. " OT1 ,Port C configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 0. " OT0 ,Port C configuration bits" "Push-pull,Open-drain" endif line.long 0x08 "GPIOC_OSPEEDR,GPIO port output speed register" bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port C configuration bits" "Low,Medium,High,Very high" endif line.long 0x0C "GPIOC_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port C configuration bits" "No pulls,Pull-up,Pull-down,?..." endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_IDR,GPIO port input data register" bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" textline " " bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" textline " " bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" textline " " bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" endif group.long 0x14++0x03 line.long 0x00 "GPIOC_ODR,GPIO port output data register" bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" textline " " bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" textline " " bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" textline " " bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" endif wgroup.long 0x18++0x03 line.long 0x00 "GPIOC_BSRR,GPIO port bit set/reset register" bitfld.long 0x00 31. " BR15 ,Port C reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port C reset bit 14" "No effect,Reset" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 29. " BR13 ,Port C reset bit 13" "No effect,Reset" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 28. " BR12 ,Port C reset bit 12" "No effect,Reset" bitfld.long 0x00 27. " BR11 ,Port C reset bit 11" "No effect,Reset" bitfld.long 0x00 26. " BR10 ,Port C reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port C reset bit 9" "No effect,Reset" textline " " bitfld.long 0x00 24. " BR8 ,Port C reset bit 8" "No effect,Reset" bitfld.long 0x00 23. " BR7 ,Port C reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port C reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port C reset bit 5" "No effect,Reset" textline " " bitfld.long 0x00 20. " BR4 ,Port C reset bit 4" "No effect,Reset" bitfld.long 0x00 19. " BR3 ,Port C reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port C reset bit 2" "No effect,Reset" bitfld.long 0x00 17. " BR1 ,Port C reset bit 1" "No effect,Reset" textline " " bitfld.long 0x00 16. " BR0 ,Port C reset bit 0" "No effect,Reset" textline " " endif bitfld.long 0x00 15. " BS15 ,Port C set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port C set bit 14" "No effect,Set" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 13. " BS13 ,Port C set bit 13" "No effect,Set" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 12. " BS12 ,Port C set bit 12" "No effect,Set" bitfld.long 0x00 11. " BS11 ,Port C set bit 11" "No effect,Set" bitfld.long 0x00 10. " BS10 ,Port C set bit 10" "No effect,Set" bitfld.long 0x00 9. " BS9 ,Port C set bit 9" "No effect,Set" textline " " bitfld.long 0x00 8. " BS8 ,Port C set bit 8" "No effect,Set" bitfld.long 0x00 7. " BS7 ,Port C set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port C set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port C set bit 5" "No effect,Set" textline " " bitfld.long 0x00 4. " BS4 ,Port C set bit 4" "No effect,Set" bitfld.long 0x00 3. " BS3 ,Port C set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port C set bit 2" "No effect,Set" bitfld.long 0x00 1. " BS1 ,Port C set bit 1" "No effect,Set" textline " " bitfld.long 0x00 0. " BS0 ,Port C set bit 0" "No effect,Set" endif group.long 0x1C++0x03 line.long 0x00 "GPIOC_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" bitfld.long 0x00 15. " LCK15 ,Port C lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port C lock bit 14" "Not locked,Locked" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 13. " LCK13 ,Port C lock bit 13" "Not locked,Locked" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 12. " LCK12 ,Port C lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port C lock bit 11" "Not locked,Locked" bitfld.long 0x00 10. " LCK10 ,Port C lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port C lock bit 9" "Not locked,Locked" textline " " bitfld.long 0x00 8. " LCK8 ,Port C lock bit 8" "Not locked,Locked" bitfld.long 0x00 7. " LCK7 ,Port C lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port C lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port C lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port C lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port C lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port C lock bit 2" "Not locked,Locked" bitfld.long 0x00 1. " LCK1 ,Port C lock bit 1" "Not locked,Locked" textline " " bitfld.long 0x00 0. " LCK0 ,Port C lock bit 0" "Not locked,Locked" endif textline " " width 15. sif (cpuis("STM32L433R*"))||(cpuis("STM32L443*")) group.long 0x20++0x07 line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port C pin 7" ",,,,,,,,,TSC_G4_IO2,,LCD_SEG25,SDMMC1_D7,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port C pin 6" ",,,,,,,,,TSC_G4_IO1,,LCD_SEG24,SDMMC1_D6,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port C pin 5" ",,,,,,,USART3_RX,,,,LCD_SEG23,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port C pin 4" ",,,,,,,USART3_TX,,,,LCD_SEG22,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port C pin 3" ",LPTIM1_ETR,,,,SPI2_MOSI,,,,,,LCD_VLCD,,SAI1_SD_A,LPTIM2_ETR,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port C pin 2" ",LPTIM1_IN2,,,,SPI2_MISO,,,,,,LCD_SEG20,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port C pin 1" ",LPTIM1_OUT,,,I2C3_SDA,,,,LPUART1_TX,,,LCD_SEG19,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port C pin 0" ",LPTIM1_IN1,,,I2C3_SCL,,,,LPUART1_RX,,,LCD_SEG18,,,LPTIM2_IN1,EVENTOUT" line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port C pin 12" ",,,,,,SPI3_MOSI,USART3_CK,,TSC_G3_IO4,,LCD_COM6/LCD_SEG30/LCD_SEG42,SDMMC1_CK,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,,TSC_G3_IO3,,LCD_COM5/LCD_SEG29/LCD_SEG41,SDMMC1_D3,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK,USART3_TX,,TSC_G3_IO2,,LCD_COM4/LCD_SEG28/LCD_SEG40,SDMMC1_D2,,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",,,,,,,,,TSC_G4_IO4,USB_NOE,LCD_SEG27,SDMMC1_D1,,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port C pin 8" ",,,,,,,,,TSC_G4_IO3,,LCD_SEG26,SDMMC1_D0,,,EVENTOUT" elif (cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long 0x20++0x07 line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,DFSDM_DATIN3,,,TSC_G4_IO2,,,SDMMC1_D7,SAI2_MCLK_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,TIM8_CH1,,,DFSDM_CKIN3,,,TSC_G4_IO1,,,SDMMC1_D6,SAI2_MCLK_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port C pin 5" ",,,,,,,USART3_RX,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port C pin 4" ",,,,,,,USART3_TX,,,,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port C pin 3" ",LPTIM1_ETR,,,,SPI2_MOSI,,,,,,,,SAI1_SD_A,LPTIM2_ETR,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port C pin 2" ",LPTIM1_IN2,,,,SPI2_MISO,DFSDM_CKOUT,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port C pin 1" ",LPTIM1_OUT,,,I2C3_SDA,,DFSDM_CKIN4,,LPUART1_TX,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port C pin 0" ",LPTIM1_IN1,,,I2C3_SCL,,DFSDM_DATIN4,,LPUART1_RX,,,,,,LPTIM2_IN1,EVENTOUT" line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port C pin 12" ",,,,,,SPI3_MOSI,USART3_CK,UART5_TX,TSC_G3_IO4,,,SDMMC1_CK,SAI2_SD_B,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,TSC_G3_IO3,,,SDMMC1_D3,SAI2_MCLK_B,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK,USART3_TX,UART4_TX,TSC_G3_IO2,,,SDMMC1_D2,SAI2_SCK_B,,EVENTOUT" textline " " sif (cpuis("STM32L471*")) bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",TIM8_BKIN2,TIM3_CH4,TIM8_CH4,,,,,,TSC_G4_IO4,,,SDMMC1_D1,SAI2_EXTCLK,TIM8_BKIN2_COMP1,EVENTOUT" else bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",TIM8_BKIN2,TIM3_CH4,TIM8_CH4,,,,,,TSC_G4_IO4,OTG_FS_NOE,,SDMMC1_D1,SAI2_EXTCLK,TIM8_BKIN2_COMP1,EVENTOUT" endif bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port C pin 8" ",,TIM3_CH3,TIM8_CH3,,,,,,TSC_G4_IO3,,,SDMMC1_D0,,,EVENTOUT" elif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*"))||cpuis("STM32L462C*")||cpuis("STM32L452C*")||cpuis("STM32L451C*") group.long 0x24++0x03 line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x00 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL13[3:0] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT" elif (cpuis("STM32L432*"))||(cpuis("STM32L431K*"))||(cpuis("STM32L442KC")) group.long 0x24++0x03 line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x00 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" elif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,TIM8_CH2,,,DFSDM1_DATIN3,,,TSC_G4_IO2,DCMI_D1,LCD_SEG25,SDMMC1_D7,SAI2_MCLK_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port C pin 6" ",TIM1_BKIN,TIM3_CH1,TIM8_BKIN,DCMI_PIXCLK,SPI1_MISO,,USART3_CTS,,TSC_G4_IO1,DCMI_D0,LCD_SEG24,SDMMC1_D6,SAI2_MCLK_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port C pin 5" ",TIM2_CH1,TIM2_ETR,TIM8_CH1N,,SPI1_SCK,,,,,,LCD_SEG23,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port C pin 4" ",,,,,,,USART3_TX,,,QUADSPI_BK2_IO3,LCD_SEG22,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port C pin 3" ",LPTIM1_ETR,,,,SPI2_MOSI,,,LPUART1_RX,,QUADSPI_CLK,LCD_SEG2,,SAI1_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port C pin 2" ",LPTIM1_IN2,,,,SPI2_MISO,,,,,QUADSPI_BK2_IO1,LCD_SEG20,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port C pin 1" "TRACED0,LPTIM1_OUT,I2C4_SDA,SPI2_MOSI,I2C3_SDA,,DFSDM1_CKIN4,,LPUART1_TX,,QUADSPI_BK2_IO0,LCD_SEG19,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port C pin 0" ",LPTIM1_IN1,I2C4_SCL,,I2C3_SCL,,DFSDM1_DATIN4,,LPUART1_RX,,,LCD_SEG18,,,LPTIM2_IN1,EVENTOUT" line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI,USART3_CK,UART5_TX,TSC_G3_IO4,DCMI_D9,LCD_COM6/L-CD_SEG30/L-CD_SEG42,SDMMC1_CK,SAI2_SD_B,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port C pin 11" ",,,,,QUADSPI_BK2_NCS,SPI3_MISO,USART3_RX,UART4_RX,TSC_G3_IO3,DCMI_D4,LCD_COM5/L-CD_SEG29/L-CD_SEG41,SDMMC1_D3,SAI2_MCLK_B,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port C pin 10" "TRACED1,,,,,,SPI3_SCK,USART3_TX,UART4_TX,TSC_G3_IO2,DCMI_D8,LCD_COM4/L-CD_SEG28/L-CD_SEG40,SDMMC1_D2,SAI2_SCK_B,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",TIM8_BKIN2,TIM3_CH4,TIM8_CH4,DCMI_D3,,I2C3_SDA,,,TSC_G4_IO4,OTG_FS_NOE,LCD_SEG27,SDMMC1_D1,SAI2_EXTCLK,TIM8_BKIN2_COMP1,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port C pin 8" ",,TIM3_CH3,TIM8_CH3,,,,,,TSC_G4_IO3,DCMI_D2,LCD_SEG26,SDMMC1_D0,,,EVENTOUT" elif (cpuis("STM32L462V*")||cpuis("STM32L462R*")||cpuis("STM32L452V*")||cpuis("STM32L452R*")||cpuis("STM32L451V*")||cpuis("STM32L451R*")) group.long 0x20++0x07 line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port C pin 7" ",,TIM3_CH2,,,,DFSDM1_DATIN3,,,TSC_G4_IO2,,,SDMMC1_D7,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port C pin 6" ",,TIM3_CH1,,,,DFSDM1_CKIN3,,,TSC_G4_IO1,,,SDMMC1_D6,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port C pin 5" ",,,,,,,USART3_RX,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port C pin 4" ",,,,,,,USART3_TX,,,,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port C pin 3" ",LPTIM1_ETR,,,,SPI2_MOSI,,,,,,,,SAI1_SD_A,LPTIM2_ETR,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port C pin 2" ",LPTIM1_IN2,,,,SPI2_MISO,DFSDM1_CKOUT,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port C pin 1" "TRACED0,LPTIM1_OUT,I2C4_SDA,,I2C3_SDA,,,,LPUART1_TX,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port C pin 0" ",LPTIM1_IN1,I2C4_SCL,,I2C3_SCL,,,,LPUART1_RX,,,,,,LPTIM2_IN1,EVENTOUT" line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port C pin 12" "TRACED3,,,,,,SPI3_MOSI,USART3_CK,,,,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,UART4_RX,TSC_G3_IO3,,,SDMMC1_D3,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port C pin 10" "TRACED1,,,,,,SPI3_SCK,USART3_TX,UART4_TX,TSC_G3_IO2,,,SDMMC1_D2,,,EVENTOUT" textline " " sif (cpuis("STM32L451*")) bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",,TIM3_CH4,,,,,,,TSC_G4_IO4,,,SDMMC1_D1,,,EVENTOUT" else bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",,TIM3_CH4,,,,,,,TSC_G4_IO4,USB_NOE,,SDMMC1_D1,,,EVENTOUT" endif textline " " bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port C pin 8" ",,TIM3_CH3,,,,,,,TSC_G4_IO3,,,SDMMC1_D0,,,EVENTOUT" else group.long 0x20++0x07 line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port C pin 7" ",,,,,,,,,TSC_G4_IO2,,,SDMMC1_D7,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port C pin 6" ",,,,,,,,,TSC_G4_IO1,,,SDMMC1_D6,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port C pin 5" ",,,,,,,USART3_RX,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port C pin 4" ",,,,,,,USART3_TX,,,,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port C pin 3" ",LPTIM1_ETR,,,,SPI2_MOSI,,,,,,,,SAI1_SD_A,LPTIM2_ETR,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port C pin 2" ",LPTIM1_IN2,,,,SPI2_MISO,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port C pin 1" ",LPTIM1_OUT,,,I2C3_SDA,,,,LPUART1_TX,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port C pin 0" ",LPTIM1_IN1,,,I2C3_SCL,,,,LPUART1_RX,,,,,,LPTIM2_IN1,EVENTOUT" line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port C pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port C pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port C pin 13" ",,,,,,,,,,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port C pin 12" ",,,,,,SPI3_MOSI,USART3_CK,,TSC_G3_IO4,,,SDMMC1_CK,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port C pin 11" ",,,,,,SPI3_MISO,USART3_RX,,TSC_G3_IO3,,,SDMMC1_D3,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port C pin 10" ",,,,,,SPI3_SCK,USART3_TX,,TSC_G3_IO2,,,SDMMC1_D2,,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port C pin 9" ",,,,,,,,,TSC_G4_IO4,,,SDMMC1_D1,,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port C pin 8" ",,,,,,,,,TSC_G4_IO3,,,SDMMC1_D0,,,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOC_BRR,GPIO port bit reset register" bitfld.long 0x00 15. " BR15 ,Port C Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port C Reset bit 14" "No action,Reset" textline " " sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L471QG")) bitfld.long 0x00 13. " BR13 ,Port C Reset bit 13" "No action,Reset" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L433C*"))&&(!cpuis("STM32L443VC"))&&(!cpuis("STM32L471QG"))&&(!cpuis("STM32L451C*"))&&(!cpuis("STM32L452C*"))&&(!cpuis("STM32L462C*")) bitfld.long 0x00 12. " BR12 ,Port C Reset bit 12" "No action,Reset" bitfld.long 0x00 11. " BR11 ,Port C Reset bit 11" "No action,Reset" bitfld.long 0x00 10. " BR10 ,Port C Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port C Reset bit 9" "No action,Reset" textline " " bitfld.long 0x00 8. " BR8 ,Port C Reset bit 8" "No action,Reset" bitfld.long 0x00 7. " BR7 ,Port C Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port C Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port C Reset bit 5" "No action,Reset" textline " " bitfld.long 0x00 4. " BR4 ,Port C Reset bit 4" "No action,Reset" bitfld.long 0x00 3. " BR3 ,Port C Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port C Reset bit 2" "No action,Reset" bitfld.long 0x00 1. " BR1 ,Port C Reset bit 1" "No action,Reset" textline " " bitfld.long 0x00 0. " BR0 ,Port C Reset bit 0" "No action,Reset" endif sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOC_ASCR,GPIO port analog switch control register" bitfld.long 0x00 15. " ASC15 ,Port C Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port C Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port C Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port C Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port C Reset bit 11" "Disconnected,Connected" bitfld.long 0x00 10. " ASC10 ,Port C Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port C Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port C Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port C Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port C Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port C Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port C Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port C Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port C Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port C Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port C Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end sif (cpuis("STM32L471VG"))||(cpuis("STM32L431V*"))||(cpuis("STM32L431R*"))||(cpuis("STM32L433R*"))&&(!cpuis("STM32L443VC"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451V*"))||(cpuis("STM32L452V*"))||(cpuis("STM32L462V*"))||(cpuis("STM32L451R*"))||(cpuis("STM32L452R*"))||(cpuis("STM32L462R*")) tree "GPIO D" base ad:0x48000C00 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOD_MODER,GPIO port mode register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 30.--31. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 26.--27. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 22.--23. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 20.--21. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 14.--15. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " endif bitfld.long 0x00 4.--5. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 2.--3. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port D configuration bits" "Input,Gen purp output,Alt function,Analog" endif line.long 0x04 "GPIOD_OTYPER,GPIO port output type register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x04 15. " OT15 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port D configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 13. " OT13 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 11. " OT11 ,Port D configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 10. " OT10 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port D configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 7. " OT7 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port D configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port D configuration bits" "Push-pull,Open-drain" textline " " endif bitfld.long 0x04 2. " OT2 ,Port D configuration bits" "Push-pull,Open-drain" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x04 1. " OT1 ,Port D configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port D configuration bits" "Push-pull,Open-drain" endif line.long 0x08 "GPIOD_OSPEEDR,GPIO port output speed register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" textline " " endif bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port D configuration bits" "Low,Medium,High,Very high" endif line.long 0x0C "GPIOD_PUPDR,GPIO port pull-up/pull-down register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " endif bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port D configuration bits" "No pulls,Pull-up,Pull-down,?..." endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOD_IDR,GPIO port input data register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" textline " " bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" textline " " bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" textline " " endif bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" endif group.long 0x14++0x03 line.long 0x00 "GPIOD_ODR,GPIO port output data register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" textline " " bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" textline " " bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" textline " " endif bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" endif wgroup.long 0x18++0x03 line.long 0x00 "GPIOD_BSRR,GPIO port bit set/reset register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 31. " BR15 ,Port D reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port D reset bit 14" "No effect,Reset" textline " " bitfld.long 0x00 29. " BR13 ,Port D reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port D reset bit 12" "No effect,Reset" bitfld.long 0x00 27. " BR11 ,Port D reset bit 11" "No effect,Reset" textline " " bitfld.long 0x00 26. " BR10 ,Port D reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port D reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port D reset bit 8" "No effect,Reset" textline " " bitfld.long 0x00 23. " BR7 ,Port D reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port D reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port D reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port D reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port D reset bit 3" "No effect,Reset" textline " " endif bitfld.long 0x00 18. " BR2 ,Port D reset bit 2" "No effect,Reset" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 17. " BR1 ,Port D reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port D reset bit 0" "No effect,Reset" bitfld.long 0x00 15. " BS15 ,Port D set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port D set bit 14" "No effect,Set" textline " " bitfld.long 0x00 13. " BS13 ,Port D set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port D set bit 12" "No effect,Set" bitfld.long 0x00 11. " BS11 ,Port D set bit 11" "No effect,Set" textline " " bitfld.long 0x00 10. " BS10 ,Port D set bit 10" "No effect,Set" textline " " bitfld.long 0x00 9. " BS9 ,Port D set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port D set bit 8" "No effect,Set" bitfld.long 0x00 7. " BS7 ,Port D set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port D set bit 6" "No effect,Set" textline " " bitfld.long 0x00 5. " BS5 ,Port D set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port D set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port D set bit 3" "No effect,Set" endif bitfld.long 0x00 2. " BS2 ,Port D set bit 2" "No effect,Set" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 1. " BS1 ,Port D set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port D set bit 0" "No effect,Set" endif group.long 0x1C++0x03 line.long 0x00 "GPIOD_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 15. " LCK15 ,Port D lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port D lock bit 14" "Not locked,Locked" textline " " bitfld.long 0x00 13. " LCK13 ,Port D lock bit 13" "Not locked,Locked" bitfld.long 0x00 12. " LCK12 ,Port D lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port D lock bit 11" "Not locked,Locked" textline " " bitfld.long 0x00 10. " LCK10 ,Port D lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port D lock bit 9" "Not locked,Locked" bitfld.long 0x00 8. " LCK8 ,Port D lock bit 8" "Not locked,Locked" textline " " bitfld.long 0x00 7. " LCK7 ,Port D lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port D lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port D lock bit 5" "Not locked,Locked" bitfld.long 0x00 4. " LCK4 ,Port D lock bit 4" "Not locked,Locked" textline " " bitfld.long 0x00 3. " LCK3 ,Port D lock bit 3" "Not locked,Locked" textline " " endif bitfld.long 0x00 2. " LCK2 ,Port D lock bit 2" "Not locked,Locked" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 1. " LCK1 ,Port D lock bit 1" "Not locked,Locked" bitfld.long 0x00 0. " LCK0 ,Port D lock bit 0" "Not locked,Locked" endif textline " " width 15. sif (cpuis("STM32L431V*")) group.long 0x20++0x07 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port D pin 7" ",,,,,,,USART2_CK,,,QUADSPI_BK2_IO3,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port D pin 6" ",,,,,,,USART2_RX,,,QUADSPI_BK2_IO2,,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,QUADSPI_BK2_IO1,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port D pin 4" ",,,,,SPI2_MOSI,,USART2_RTS_DE,,,QUADSPI_BK2_IO0,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port D pin 3" ",,,,,SPI2_MISO,,USART2_CTS,,,QUADSPI_BK2_NCS,,,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" ",,,,,,,USART3_RTS_DE,,TSC_SYNC,,,SDMMC1_CMD,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port D pin 1" ",,,,,SPI2_SCK,,,,CAN1_TX,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port D pin 0" ",,,,,SPI2_NSS,,,,CAN1_RX,,,,,,EVENTOUT" line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port D pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port D pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port D pin 13" ",,,,,,,,,TSC_G6_IO4,,,,,LPTIM2_OUT,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port D pin 12" ",,,,,,,USART3_RTS_DE,,TSC_G6_IO3,,,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port D pin 11" ",,,,,,,USART3_CTS,,TSC_G6_IO2,,,,,LPTIM2_ETR,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,TSC_G6_IO1,,,,,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,,,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,,,,,,EVENTOUT" elif (cpuis("STM32L443*")) group.long 0x20++0x07 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port D pin 7" ",,,,,,,USART2_CK,,,QUADSPI_BK2_IO3,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port D pin 6" ",,,,,,,USART2_RX,,,QUADSPI_BK2_IO2,,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,QUADSPI_BK2_IO1,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port D pin 4" ",,,,,SPI2_MOSI,,USART2_RTS_DE,,,QUADSPI_BK2_IO0,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port D pin 3" ",,,,,SPI2_MISO,,USART2_CTS,,,QUADSPI_BK2_NCS,,,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" ",,,,,,,USART3_RTS_DE,,TSC_SYNC,,LCD_COM7/LCD_SEG31/LCD_SEG43,SDMMC1_CMD,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port D pin 1" ",,,,,SPI2_SCK,,,,CAN1_TX,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port D pin 0" ",,,,,SPI2_NSS,,,,CAN1_RX,,,,,,EVENTOUT" line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port D pin 15" ",,,,,,,,,,,LCD_SEG35,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port D pin 14" ",,,,,,,,,,,LCD_SEG34,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port D pin 13" ",,,,,,,,,TSC_G6_IO4,,LCD_SEG,,,LPTIM2_OUT,EVENTOUT" bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port D pin 12" ",,,,,,,USART3_RTS_DE,,TSC_G6_IO3,,LCD_SEG32,,,LPTIM2_IN1,EVENTOUT" textline " " bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port D pin 11" ",,,,,,,USART3_CTS,,TSC_G6_IO2,,LCD_SEG31,,,LPTIM2_ETR,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,TSC_G6_IO1,,LCD_SEG30,,,,EVENTOUT" bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,LCD_SEG29,,,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,,LCD_SEG28,,,,EVENTOUT" elif (cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long 0x20++0x07 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port D pin 7" ",,,,,,DFSDM_CKIN1,USART2_CK,,,,,FMC_NE1,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port D pin 6" ",,,,,,DFSDM_DATIN1,USART2_RX,,,,,FMC_NWAIT,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port D pin 4" ",,,,,SPI2_MOSI,DFSDM_CKIN0,USART2_RTS_DE,,,,,FMC_NOE,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port D pin 3" ",,,,,SPI2_MISO,DFSDM_DATIN0,USART2_CTS,,,,,FMC_CLK,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" ",,TIM3_ETR,,,,,USART3_RTS_DE,UART5_RX,TSC_SYNC,,,SDMMC1_CMD,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port D pin 1" ",,,,,SPI2_SCK,DFSDM_CKIN7,,,CAN1_TX,,,FMC_D3,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port D pin 0" ",,,,,SPI2_NSS,DFSDM_DATIN7,,,CAN1_RX,,,FMC_D2,,,EVENTOUT" line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,,,,,FMC_D1,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,,,,,FMC_D0,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,,,,,,,TSC_G6_IO4,,,FMC_A18,,LPTIM2_OUT,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,,,,,USART3_RTS_DE,,TSC_G6_IO3,,,FMC_A17,SAI2_FS_A,LPTIM2_IN1,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port D pin 11" ",,,,,,,USART3_CTS,,TSC_G6_IO2,,,FMC_A16,SAI2_SD_A,LPTIM2_ETR,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,TSC_G6_IO1,,,FMC_D15,SAI2_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,FMC_D,SAI2_MCLK_A,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,,,FMC_D,,,EVENTOUT" elif (cpuis("STM32L431R*")) group.long 0x20++0x03 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" ",,,,,,,USART3_RTS_DE,,TSC_SYNC,,,SDMMC1_CMD,,,EVENTOUT" elif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" sif (!cpuis("STM32L4?6R*")) bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port D pin 7" ",,,,,,DFSDM1_CKIN1,USART2_CK,,,QUADSPI_BK2_IO3,,FMC_NE1,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port D pin 6" ",,,,DCMI_D10,QUADSPI_BK2_IO1,DFSDM1_DATIN1,USART2_RX,,,QUADSPI_BK2_IO2,,FMC_NWAIT,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,QUADSPI_BK2_IO1,,FMC_NWE,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port D pin 4" ",,,,,SPI2_MOSI,DFSDM1_CKIN0,USART2_RTS_DE,,,QUADSPI_BK2_IO0,,FMC_NOE,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port D pin 3" ",,,SPI2_SCK,DCMI_D5,SPI2_MISO,DFSDM1_DATIN0,USART2_CTS,,,QUADSPI_BK2_NCS,,FMC_CLK,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,USART3_RTS_DE,UART5_RX,TSC_SYNC,DCMI_D11,LCD_COM7/LCD_SEG31/LCD_SEG43,SDMMC1_CMD,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port D pin 1" ",,,,,SPI2_SCK,DFSDM1_CKIN7,,,CAN1_TX,,,FMC_D3,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port D pin 0" ",,,,,SPI2_NSS,DFSDM1_DATIN7,,,CAN1_RX,,,FMC_D2,,,EVENTOUT" else bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,USART3_RTS_DE,UART5_RX,TSC_SYNC,DCMI_D11,LCD_COM7/LCD_SEG31/LCD_SEG43,SDMMC1_CMD,,,EVENTOUT" endif sif (!cpuis("STM32L4?6R*")) line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port D pin 15" ",,TIM4_CH4,,,,,,,,,LCD_SEG35,FMC_D1,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port D pin 14" ",,TIM4_CH3,,,,,,,,,LCD_SEG34,FMC_D0,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port D pin 13" ",,TIM4_CH2,,,,,,,TSC_G6_IO4,,LCD_SEG33,FMC_A18,,LPTIM2_OUT,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port D pin 12" ",,TIM4_CH1,,2C4_SCL,,,USART3_RTS_DE,,TSC_G6_IO3,,LCD_SEG32,FMC_A17,SAI2_FS_A,LPTIM2_IN1,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,TSC_G6_IO2,,LCD_SEG31,FMC_A16,SAI2_SD_A,LPTIM2_ETR,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,TSC_G6_IO1,,LCD_SEG30,FMC_D15,SAI2_SCK_A,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,DCMI_PIXCLK,LCD_SEG29,FMC_D14,SAI2_MCLK_A,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,DCMI_HSYNC,LCD_SEG28,FMC_D13,,,EVENTOUT" endif elif (cpuis("STM32L462V*")||cpuis("STM32L452V*")||cpuis("STM32L451V*")) group.long 0x20++0x07 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port D pin 7" ",,,,,,DFSDM1_CKIN1,USART2_CK,,,QUADSPI_BK2_IO3,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port D pin 6" ",,,,,,DFSDM1_DATIN1,USART2_RX,,,QUADSPI_BK2_IO2,,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port D pin 5" ",,,,,,,USART2_TX,,,QUADSPI_BK2_IO1,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port D pin 4" ",,,,,SPI2_MOSI,DFSDM1_CKIN0,USART2_RTS_DE,,,QUADSPI_BK2_IO0,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port D pin 3" ",,,,,SPI2_MISO,DFSDM1_DATIN0,USART2_CTS,,,QUADSPI_BK2_NCS,,,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,USART3_RTS_DE,,TSC_SYNC,,,SDMMC1_CMD,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port D pin 1" ",,,,,SPI2_SCK,,,,CAN1_TX,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port D pin 0" ",,,,,SPI2_NSS,,,,CAN1_RX,,,,,,EVENTOUT" line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port D pin 15" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port D pin 14" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port D pin 13" ",,,,I2C4_SDA,,,,,,,,,,LPTIM2_OUT,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port D pin 12" ",,,,I2C4_SCL,,,USART3_RTS_DE,,TSC_G6_IO3,,,,,LPTIM2_IN1,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port D pin 11" ",,,,I2C4_SMBA,,,USART3_CTS,,TSC_G6_IO2,,,,,LPTIM2_ETR,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port D pin 10" ",,,,,,,USART3_CK,,TSC_G6_IO1,,,,,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port D pin 9" ",,,,,,,USART3_RX,,,,,,,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port D pin 8" ",,,,,,,USART3_TX,,,,,,,,EVENTOUT" elif (cpuis("STM32L462R*")||cpuis("STM32L452R*")||cpuis("STM32L451R*")) group.long 0x20++0x03 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" "TRACED2,,TIM3_ETR,,,,,USART3_RTS_DE,,TSC_SYNC,,,SDMMC1_CMD,,,EVENTOUT" else group.long 0x20++0x03 line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port D pin 2" ",,,,,,,USART3_RTS_DE,,TSC_SYNC,,LCD_COM7/LCD_SEG31/LCD_SEG43,SDMMC1_CMD,,,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOD_BRR,GPIO port bit reset register" sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 15. " BR15 ,Port D Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port D Reset bit 14" "No action,Reset" textline " " bitfld.long 0x00 13. " BR13 ,Port D Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port D Reset bit 12" "No action,Reset" bitfld.long 0x00 11. " BR11 ,Port D Reset bit 11" "No action,Reset" textline " " bitfld.long 0x00 10. " BR10 ,Port D Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port D Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port D Reset bit 8" "No action,Reset" textline " " bitfld.long 0x00 7. " BR7 ,Port D Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port D Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port D Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port D Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port D Reset bit 3" "No action,Reset" textline " " endif bitfld.long 0x00 2. " BR2 ,Port D Reset bit 2" "No action,Reset" textline " " sif (!cpuis("STM32L431R*"))&&(!cpuis("STM32L433R*"))&&(!cpuis("STM32L443RC"))&&(!cpuis("STM32L471RE"))&&(!cpuis("STM32L471RG"))&&(!cpuis("STM32L475RC"))&&(!cpuis("STM32L4?6R*"))&&(!cpuis("STM32L451R*"))&&(!cpuis("STM32L452R*"))&&(!cpuis("STM32L462R*")) bitfld.long 0x00 1. " BR1 ,Port D Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port D Reset bit 0" "No action,Reset" endif sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOD_ASCR,GPIO port analog switch control register" sif (cpuis("STM32L4?6R*")) bitfld.long 0x00 2. " ASC2 ,Port D Reset bit 2" "Disconnected,Connected" else bitfld.long 0x00 15. " ASC15 ,Port D Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port D Reset bit 14" "Disconnected,Connected" textline " " bitfld.long 0x00 13. " ASC13 ,Port D Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port D Reset bit 12" "Disconnected,Connected" bitfld.long 0x00 11. " ASC11 ,Port D Reset bit 11" "Disconnected,Connected" textline " " bitfld.long 0x00 10. " ASC10 ,Port D Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port D Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port D Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port D Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port D Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port D Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port D Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port D Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port D Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port D Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port D Reset bit 0" "Disconnected,Connected" endif endif width 0x0B tree.end endif sif (cpuis("STM32L471VG"))||(cpuis("STM32L431V*"))||(cpuis("STM32L4?6V*"))||(cpuis("STM32L4?6Q*"))||(cpuis("STM32L4?6Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451V*"))||(cpuis("STM32L452V*"))||(cpuis("STM32L462V*")) tree "GPIO E" base ad:0x48001000 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOE_MODER,GPIO port mode register" bitfld.long 0x00 30.--31. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 26.--27. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 22.--23. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 20.--21. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 14.--15. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 4.--5. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 2.--3. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port E configuration bits" "Input,Gen purp output,Alt function,Analog" line.long 0x04 "GPIOE_OTYPER,GPIO port output type register" bitfld.long 0x04 15. " OT15 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 13. " OT13 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port E configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 11. " OT11 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 10. " OT10 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port E configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 7. " OT7 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port E configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 1. " OT1 ,Port E configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port E configuration bits" "Push-pull,Open-drain" line.long 0x08 "GPIOE_OSPEEDR,GPIO port output speed register" bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port E configuration bits" "Low,Medium,High,Very high" line.long 0x0C "GPIOE_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port E configuration bits" "No pulls,Pull-up,Pull-down,?..." rgroup.long 0x10++0x03 line.long 0x00 "GPIOE_IDR,GPIO port input data register" bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" textline " " bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIOE_ODR,GPIO port output data register" bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" textline " " bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" wgroup.long 0x18++0x03 line.long 0x00 "GPIOE_BSRR,GPIO port bit set/reset register" bitfld.long 0x00 31. " BR15 ,Port E reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port E reset bit 14" "No effect,Reset" bitfld.long 0x00 29. " BR13 ,Port E reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port E reset bit 12" "No effect,Reset" textline " " bitfld.long 0x00 27. " BR11 ,Port E reset bit 11" "No effect,Reset" bitfld.long 0x00 26. " BR10 ,Port E reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port E reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port E reset bit 8" "No effect,Reset" textline " " bitfld.long 0x00 23. " BR7 ,Port E reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port E reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port E reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port E reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port E reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port E reset bit 2" "No effect,Reset" bitfld.long 0x00 17. " BR1 ,Port E reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port E reset bit 0" "No effect,Reset" textline " " bitfld.long 0x00 15. " BS15 ,Port E set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port E set bit 14" "No effect,Set" bitfld.long 0x00 13. " BS13 ,Port E set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port E set bit 12" "No effect,Set" textline " " bitfld.long 0x00 11. " BS11 ,Port E set bit 11" "No effect,Set" bitfld.long 0x00 10. " BS10 ,Port E set bit 10" "No effect,Set" bitfld.long 0x00 9. " BS9 ,Port E set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port E set bit 8" "No effect,Set" textline " " bitfld.long 0x00 7. " BS7 ,Port E set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port E set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port E set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port E set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port E set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port E set bit 2" "No effect,Set" bitfld.long 0x00 1. " BS1 ,Port E set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port E set bit 0" "No effect,Set" group.long 0x1C++0x03 line.long 0x00 "GPIOE_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" bitfld.long 0x00 15. " LCK15 ,Port E lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port E lock bit 14" "Not locked,Locked" bitfld.long 0x00 13. " LCK13 ,Port E lock bit 13" "Not locked,Locked" textline " " bitfld.long 0x00 12. " LCK12 ,Port E lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port E lock bit 11" "Not locked,Locked" bitfld.long 0x00 10. " LCK10 ,Port E lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port E lock bit 9" "Not locked,Locked" textline " " bitfld.long 0x00 8. " LCK8 ,Port E lock bit 8" "Not locked,Locked" bitfld.long 0x00 7. " LCK7 ,Port E lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port E lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port E lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port E lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port E lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port E lock bit 2" "Not locked,Locked" bitfld.long 0x00 1. " LCK1 ,Port E lock bit 1" "Not locked,Locked" textline " " bitfld.long 0x00 0. " LCK0 ,Port E lock bit 0" "Not locked,Locked" textline " " width 15. sif (cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long 0x20++0x07 line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM_DATIN2,,,,,,FMC_D4,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port E pin 6" "TRACED3,,TIM3_CH4,,,,,,,,,,FMC_A22,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port E pin 5" "TRACED2,,TIM3_CH3,,,,DFSDM_CKIN3,,,TSC_G7_IO4,,,FMC_A21,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port E pin 4" "TRACED1,,TIM3_CH2,,,,DFSDM_DATIN3,,,TSC_G7_IO3,,,FMC_A20,SAI1_FS_A,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port E pin 3" "TRACED0,,TIM3_CH1,,,,,,,TSC_G7_IO2,,,FMC_A19,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port E pin 2" "TRACECK,,TIM3_ETR,,,,,,,TSC_G7_IO1,,,FMC_A23,SAI1_MCLK_A,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port E pin 1" ",,,,,,,,,,,,FMC_NBL1,,TIM17_CH1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port E pin 0" ",,TIM4_ETR,,,,,,,,,,FMC_NBL0,,TIM16_CH1,EVENTOUT" line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port E pin 15" "JTDI,TIM2_CH1,TIM2_ETR,,,SPI1_NSS,SPI3_NSS,,UART4_RTS_DE,TSC_G3_IO1,,,,SAI2_FS_B,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port E pin 14" ",TIM1_CH4,TIM1_BKIN2,TIM1_BKIN2_COMP2,,SPI1_MISO,,,,,QUADSPI_BK1_IO2,,FMC_D11,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI1_SCK,DFSDM_CKIN5,,,TSC_G5_IO4,QUADSPI_BK1_IO1,,FMC_D10,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI1_NSS,DFSDM_DATIN5,,,TSC_G5_IO3,QUADSPI_BK1_IO0,,FMC_D9,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,,DFSDM_CKIN4,,,TSC_G5_IO2,QUADSPI_NCS,,FMC_D8,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,DFSDM_DATIN4,,,TSC_G5_IO1,QUADSPI_CLK,,FMC_D7,SAI1_MCLK_B,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM_CKOUT,,,,,,FMC_D6,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM_CKIN2,,,,,,FMC_D5,SAI1_SCK_B,,EVENTOUT" elif (cpuis("STM32L443*")) group.long 0x20++0x07 line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,,,,,,,,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port E pin 6" "TRACED3,,,,,,,,,,,,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port E pin 5" "TRACED2,,,,,,,,,TSC_G7_IO4,,,,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port E pin 4" "TRACED1,,,,,,,,,TSC_G7_IO3,,,,SAI1_FS_A,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,,,,TSC_G7_IO2,,LCD_SEG39,,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port E pin 2" "TRACECK,,,,,,,,,TSC_G7_IO1,,LCD_SEG38,,SAI1_MCLK_A,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port E pin 1" ",,,,,,,,,,,LCD_SEG37,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port E pin 0" ",,,,,,,,,,,LCD_SEG36,,,TIM16_CH1,EVENTOUT" line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,TIM1_BKIN_COMP1,,SPI1_MOSI,,,,,QUADSPI_BK1_IO3,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port E pin 14" ",TIM1_CH4,TIM1_BKIN2,TIM1_BKIN2_COMP2,,SPI1_MISO,,,,,QUADSPI_BK1_IO2,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI1_SCK,,,,TSC_G5_IO4,QUADSPI_BK1_IO1,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI1_NSS,,,,TSC_G5_IO3,QUADSPI_BK1_IO0,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,,,,,TSC_G5_IO2,QUADSPI_BK1_NCS,,,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,,TSC_G5_IO1,QUADSPI_CLK,,,SAI1_MCLK_B,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,,,,,,,,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,,,,,,,,SAI1_SCK_B,,EVENTOUT" elif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM1_DATIN2,,,,,,FMC_D4,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port E pin 6" "TRACED3,,TIM3_CH4,,,,,,,,DCMI_D7,,FMC_A22,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port E pin 5" "TRACED2,,TIM3_CH3,,,,DFSDM1_CKIN3,,,TSC_G7_IO4,DCMI_D6,,FMC_A21,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port E pin 4" "TRACED1,,TIM3_CH2,,,,DFSDM1_DATIN3,,,TSC_G7_IO3,DCMI_D4,,FMC_A20,SAI1_FS_A,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port E pin 3" "TRACED0,,TIM3_CH1,,,,,,,TSC_G7_IO2,,LCD_SEG39,FMC_A19,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port E pin 2" "TRACECK,,TIM3_ETR,,,,,,,TSC_G7_IO1,,LCD_SEG38,FMC_A23,SAI1_MCLK_A,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port E pin 1" ",,,,,,,,,,DCMI_D3,LCD_SEG37,FMC_NBL1,,TIM17_CH1,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port E pin 0" ",,TIM4_ETR,,,,,,,,DCMI_D2,LCD_SEG36,FMC_NBL0,,TIM16_CH1,EVENTOUT" line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,TIM1_BKIN_COMP1,,SPI1_MOSI,,,,,QUADSPI_BK1_IO3,,FMC_D12,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port E pin 14" ",TIM1_CH4,TIM1_BKIN2,TIM1_BKIN2_COMP2,,SPI1_MISO,,,,,QUADSPI_BK1_IO2,,FMC_D11,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI1_SCK,DFSDM1_CKIN5,,,TSC_G5_IO4,QUADSPI_BK1_IO1,,FMC_D10,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI1_NSS,DFSDM1_DATIN5,,,TSC_G5_IO3,QUADSPI_BK1_IO0,,FMC_D9,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,,DFSDM1_CKIN4,,,TSC_G5_IO2,QUADSPI_BK1_NCS,,FMC_D8,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,DFSDM1_DATIN4,,,TSC_G5_IO1,QUADSPI_CLK,,FMC_D7,SAI1_MCLK_B,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM1_CKOUT,,,,,,FMC_D6,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM1_CKIN2,,,,,,FMC_D5,SAI1_SCK_B,,EVENTOUT" elif (cpuis("STM32L462V*")||cpuis("STM32L452V*")||cpuis("STM32L451V*")) group.long 0x20++0x07 line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,DFSDM_DATIN2,,,,,,FMC_D4,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port E pin 6" "TRACED3,,TIM3_CH4,,,,,,,,,,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port E pin 5" "TRACED2,,TIM3_CH3,,,,DFSDM_CKIN3,,,TSC_G7_IO4,,,,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port E pin 4" "TRACED1,,TIM3_CH2,,,,DFSDM_DATIN3,,,TSC_G7_IO3,,,,SAI1_FS_A,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port E pin 3" "TRACED0,,TIM3_CH1,,,,,,,TSC_G7_IO2,,,,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port E pin 2" "TRACECK,,TIM3_ETR,,,,,,,TSC_G7_IO1,,,,SAI1_MCLK_A,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port E pin 1" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port E pin 0" ",,,,,,,,,,,,,,TIM16_CH1,EVENTOUT" line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,TIM1_BKIN_COMP1,,SPI1_MOSI,SPI3_NSS,,,,QUADSPI_BK1_IO3,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port E pin 14" ",TIM1_CH4,TIM1_BKIN2,TIM1_BKIN2_COMP2,,SPI1_MISO,,,,,QUADSPI_BK1_IO2,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI1_SCK,,,,TSC_G5_IO4,QUADSPI_BK1_IO1,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI1_NSS,,,,TSC_G5_IO3,QUADSPI_BK1_IO0,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,,,,,TSC_G5_IO2,QUADSPI_NCS,,,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,,TSC_G5_IO1,QUADSPI_CLK,,,SAI1_MCLK_B,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,DFSDM_CKOUT,,,,,,,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,DFSDM_CKIN2,,,,,,,SAI1_SCK_B,,EVENTOUT" else group.long 0x20++0x07 line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port E pin 7" ",TIM1_ETR,,,,,,,,,,,,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port E pin 6" "TRACED3,,,,,,,,,,,,,SAI1_SD_A,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port E pin 5" "TRACED2,,,,,,,,,TSC_G7_IO4,,,,SAI1_SCK_A,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port E pin 4" "TRACED1,,,,,,,,,TSC_G7_IO3,,,,SAI1_FS_A,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port E pin 3" "TRACED0,,,,,,,,,TSC_G7_IO2,,,,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port E pin 2" "TRACECK,,,,,,,,,TSC_G7_IO1,,,,SAI1_MCLK_A,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port E pin 1" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port E pin 0" ",,,,,,,,,,,,,,TIM16_CH1,EVENTOUT" line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port E pin 15" ",TIM1_BKIN,,TIM1_BKIN_COMP1,,SPI1_MOSI,,,,,QUADSPI_BK1_IO3,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port E pin 14" ",TIM1_CH4,TIM1_BKIN2,TIM1_BKIN2_COMP2,,SPI1_MISO,,,,,QUADSPI_BK1_IO2,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port E pin 13" ",TIM1_CH3,,,,SPI1_SCK,,,,TSC_G5_IO4,QUADSPI_BK1_IO1,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port E pin 12" ",TIM1_CH3N,,,,SPI1_NSS,,,,TSC_G5_IO3,QUADSPI_BK1_IO0,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port E pin 11" ",TIM1_CH2,,,,,,,,TSC_G5_IO2,QUADSPI_BK1_NCS,,,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port E pin 10" ",TIM1_CH2N,,,,,,,,TSC_G5_IO1,QUADSPI_CLK,,,SAI1_MCLK_B,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port E pin 9" ",TIM1_CH1,,,,,,,,,,,,SAI1_FS_B,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port E pin 8" ",TIM1_CH1N,,,,,,,,,,,,SAI1_SCK_B,,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOE_BRR,GPIO port bit reset register" bitfld.long 0x00 15. " BR15 ,Port E Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port E Reset bit 14" "No action,Reset" bitfld.long 0x00 13. " BR13 ,Port E Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port E Reset bit 12" "No action,Reset" textline " " bitfld.long 0x00 11. " BR11 ,Port E Reset bit 11" "No action,Reset" bitfld.long 0x00 10. " BR10 ,Port E Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port E Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port E Reset bit 8" "No action,Reset" textline " " bitfld.long 0x00 7. " BR7 ,Port E Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port E Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port E Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port E Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port E Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port E Reset bit 2" "No action,Reset" bitfld.long 0x00 1. " BR1 ,Port E Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port E Reset bit 0" "No action,Reset" sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOE_ASCR,GPIO port analog switch control register" bitfld.long 0x00 15. " ASC15 ,Port E Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port E Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port E Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port E Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port E Reset bit 11" "Disconnected,Connected" bitfld.long 0x00 10. " ASC10 ,Port E Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port E Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port E Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port E Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port E Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port E Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port E Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port E Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port E Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port E Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port E Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end endif sif (cpuis("STM32L471ZE"))||(cpuis("STM32L471ZG"))||(cpuis("STM32L471QG"))||(cpuis("STM32L4?6Q*"))||(cpuis("STM32L4?6Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) tree "GPIO F" base ad:0x48001400 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOF_MODER,GPIO port mode register" bitfld.long 0x00 30.--31. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 26.--27. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 22.--23. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 20.--21. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 18.--19. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 14.--15. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" endif endif bitfld.long 0x00 10.--11. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 4.--5. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 2.--3. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port F configuration bits" "Input,Gen purp output,Alt function,Analog" line.long 0x04 "GPIOF_OTYPER,GPIO port output type register" bitfld.long 0x04 15. " OT15 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 13. " OT13 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port F configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 11. " OT11 ,Port F configuration bits" "Push-pull,Open-drain" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x04 10. " OT10 ,Port F configuration bits" "Push-pull,Open-drain" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x04 9. " OT9 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port F configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 7. " OT7 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port F configuration bits" "Push-pull,Open-drain" endif endif bitfld.long 0x04 5. " OT5 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port F configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 1. " OT1 ,Port F configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port F configuration bits" "Push-pull,Open-drain" line.long 0x08 "GPIOF_OSPEEDR,GPIO port output speed register" bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" endif endif bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port F configuration bits" "Low,Medium,High,Very high" line.long 0x0C "GPIOF_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." sif (!cpuis("STM32L4?6A*")) bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." endif endif bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port F configuration bits" "No pulls,Pull-up,Pull-down,?..." rgroup.long 0x10++0x03 line.long 0x00 "GPIOF_IDR,GPIO port input data register" bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" textline " " bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" endif endif bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIOF_ODR,GPIO port output data register" bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" textline " " bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" endif endif bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" wgroup.long 0x18++0x03 line.long 0x00 "GPIOF_BSRR,GPIO port bit set/reset register" bitfld.long 0x00 31. " BR15 ,Port F reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port F reset bit 14" "No effect,Reset" bitfld.long 0x00 29. " BR13 ,Port F reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port F reset bit 12" "No effect,Reset" textline " " bitfld.long 0x00 27. " BR11 ,Port F reset bit 11" "No effect,Reset" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 26. " BR10 ,Port F reset bit 10" "No effect,Reset" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 25. " BR9 ,Port F reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port F reset bit 8" "No effect,Reset" textline " " bitfld.long 0x00 23. " BR7 ,Port F reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port F reset bit 6" "No effect,Reset" endif endif bitfld.long 0x00 21. " BR5 ,Port F reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port F reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port F reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port F reset bit 2" "No effect,Reset" bitfld.long 0x00 17. " BR1 ,Port F reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port F reset bit 0" "No effect,Reset" textline " " bitfld.long 0x00 15. " BS15 ,Port F set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port F set bit 14" "No effect,Set" bitfld.long 0x00 13. " BS13 ,Port F set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port F set bit 12" "No effect,Set" textline " " bitfld.long 0x00 11. " BS11 ,Port F set bit 11" "No effect,Set" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 10. " BS10 ,Port F set bit 10" "No effect,Set" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 9. " BS9 ,Port F set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port F set bit 8" "No effect,Set" textline " " bitfld.long 0x00 7. " BS7 ,Port F set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port F set bit 6" "No effect,Set" endif endif bitfld.long 0x00 5. " BS5 ,Port F set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port F set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port F set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port F set bit 2" "No effect,Set" bitfld.long 0x00 1. " BS1 ,Port F set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port F set bit 0" "No effect,Set" group.long 0x1C++0x03 line.long 0x00 "GPIOF_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" bitfld.long 0x00 15. " LCK15 ,Port F lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port F lock bit 14" "Not locked,Locked" bitfld.long 0x00 13. " LCK13 ,Port F lock bit 13" "Not locked,Locked" textline " " bitfld.long 0x00 12. " LCK12 ,Port F lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port F lock bit 11" "Not locked,Locked" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 10. " LCK10 ,Port F lock bit 10" "Not locked,Locked" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 9. " LCK9 ,Port F lock bit 9" "Not locked,Locked" textline " " bitfld.long 0x00 8. " LCK8 ,Port F lock bit 8" "Not locked,Locked" bitfld.long 0x00 7. " LCK7 ,Port F lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port F lock bit 6" "Not locked,Locked" endif endif bitfld.long 0x00 5. " LCK5 ,Port F lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port F lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port F lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port F lock bit 2" "Not locked,Locked" bitfld.long 0x00 1. " LCK1 ,Port F lock bit 1" "Not locked,Locked" textline " " bitfld.long 0x00 0. " LCK0 ,Port F lock bit 0" "Not locked,Locked" textline " " width 15. sif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register" sif (!cpuis("STM32L4?6Q*"))&&(!cpuis("STM32L4?6A*")) bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port F pin 7" ",,TIM5_CH2,,,,,,,,QUADSPI_BK1_IO2,,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port F pin 6" ",TIM5_ETR,TIM5_CH1,,,,,,,,QUADSPI_BK1_IO3,,,SAI1_SD_B,,EVENTOUT" endif textline " " bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT" bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT" textline " " bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT" bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT" line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port F pin 15" ",,,,I2C4_SDA,,,,,TSC_G8_IO2,,,FMC_A9,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port F pin 14" ",,,,I2C4_SCL,,DFSDM_CKIN6,,,TSC_G8_IO1,,,FMC_A8,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port F pin 13" ",,,,I2C4_SMBA,,DFSDM_DATIN6,,,,,,FMC_A7,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port F pin 11" ",,,,,,,,,,DCMI_D12,,,,,EVENTOUT" textline " " sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port F pin 10" ",,,QUADSPI_CLK,,,,,,,DCMI_D11,,,,TIM15_CH2,EVENTOUT" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port F pin 9" ",,TIM5_CH4,,,,,,,,QUADSPI_BK1_IO1,,,SAI1_FS_B,TIM15_CH1,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port F pin 8" ",,TIM5_CH3,,,,,,,,QUADSPI_BK1_IO0,,,SAI1_SCK_B,,EVENTOUT" endif endif else group.long 0x20++0x07 line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port F pin 7" ",,TIM5_CH2,,,,,,,,,,,SAI1_MCLK_B,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port F pin 6" ",TIM5_ETR,TIM5_CH1,,,,,,,,,,,SAI1_SD_B,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port F pin 5" ",,,,,,,,,,,,FMC_A5,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port F pin 4" ",,,,,,,,,,,,FMC_A4,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port F pin 3" ",,,,,,,,,,,,FMC_A3,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port F pin 2" ",,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT" line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port F pin 15" ",,,,,,,,,TSC_G8_IO2,,,FMC_A9,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port F pin 14" ",,,,,,DFSDM_CKIN6,,,TSC_G8_IO1,,,FMC_A8,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port F pin 13" ",,,,,,DFSDM_DATIN6,,,,,,FMC_A7,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port F pin 12" ",,,,,,,,,,,,FMC_A6,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port F pin 11" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port F pin 10" ",,,,,,,,,,,,,,TIM15_CH2,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port F pin 9" ",,TIM5_CH4,,,,,,,,,,,SAI1_FS_B,TIM15_CH1,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port F pin 8" ",,TIM5_CH3,,,,,,,,,,,SAI1_SCK_B,,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOF_BRR,GPIO port bit reset register" bitfld.long 0x00 15. " BR15 ,Port F Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port F Reset bit 14" "No action,Reset" bitfld.long 0x00 13. " BR13 ,Port F Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port F Reset bit 12" "No action,Reset" textline " " bitfld.long 0x00 11. " BR11 ,Port F Reset bit 11" "No action,Reset" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 10. " BR10 ,Port F Reset bit 10" "No action,Reset" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 9. " BR9 ,Port F Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port F Reset bit 8" "No action,Reset" textline " " bitfld.long 0x00 7. " BR7 ,Port F Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port F Reset bit 6" "No action,Reset" endif endif bitfld.long 0x00 5. " BR5 ,Port F Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port F Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port F Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port F Reset bit 2" "No action,Reset" bitfld.long 0x00 1. " BR1 ,Port F Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port F Reset bit 0" "No action,Reset" sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOF_ASCR,GPIO port analog switch control register" bitfld.long 0x00 15. " ASC15 ,Port F Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port F Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port F Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port F Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port F Reset bit 11" "Disconnected,Connected" sif (!cpuis("STM32L4?6Q*")) bitfld.long 0x00 10. " ASC10 ,Port F Reset bit 10" "Disconnected,Connected" sif (!cpuis("STM32L4?6A*")) bitfld.long 0x00 9. " ASC9 ,Port F Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port F Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port F Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port F Reset bit 6" "Disconnected,Connected" endif endif bitfld.long 0x00 5. " ASC5 ,Port F Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port F Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port F Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port F Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port F Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port F Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end tree "GPIO G" base ad:0x48001800 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOG_MODER,GPIO port mode register" bitfld.long 0x00 30.--31. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 26.--27. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 22.--23. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 20.--21. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 14.--15. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 4.--5. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 2.--3. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port G configuration bits" "Input,Gen purp output,Alt function,Analog" line.long 0x04 "GPIOG_OTYPER,GPIO port output type register" bitfld.long 0x04 15. " OT15 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 13. " OT13 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port G configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 11. " OT11 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 10. " OT10 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port G configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 7. " OT7 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port G configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 1. " OT1 ,Port G configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port G configuration bits" "Push-pull,Open-drain" line.long 0x08 "GPIOG_OSPEEDR,GPIO port output speed register" bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port G configuration bits" "Low,Medium,High,Very high" line.long 0x0C "GPIOG_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port G configuration bits" "No pulls,Pull-up,Pull-down,?..." rgroup.long 0x10++0x03 line.long 0x00 "GPIOG_IDR,GPIO port input data register" bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" textline " " bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIOG_ODR,GPIO port output data register" bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" textline " " bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" wgroup.long 0x18++0x03 line.long 0x00 "GPIOG_BSRR,GPIO port bit set/reset register" bitfld.long 0x00 31. " BR15 ,Port G reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port G reset bit 14" "No effect,Reset" bitfld.long 0x00 29. " BR13 ,Port G reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port G reset bit 12" "No effect,Reset" textline " " bitfld.long 0x00 27. " BR11 ,Port G reset bit 11" "No effect,Reset" bitfld.long 0x00 26. " BR10 ,Port G reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port G reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port G reset bit 8" "No effect,Reset" textline " " bitfld.long 0x00 23. " BR7 ,Port G reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port G reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port G reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port G reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port G reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port G reset bit 2" "No effect,Reset" bitfld.long 0x00 17. " BR1 ,Port G reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port G reset bit 0" "No effect,Reset" textline " " bitfld.long 0x00 15. " BS15 ,Port G set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port G set bit 14" "No effect,Set" bitfld.long 0x00 13. " BS13 ,Port G set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port G set bit 12" "No effect,Set" textline " " bitfld.long 0x00 11. " BS11 ,Port G set bit 11" "No effect,Set" bitfld.long 0x00 10. " BS10 ,Port G set bit 10" "No effect,Set" bitfld.long 0x00 9. " BS9 ,Port G set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port G set bit 8" "No effect,Set" textline " " bitfld.long 0x00 7. " BS7 ,Port G set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port G set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port G set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port G set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port G set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port G set bit 2" "No effect,Set" bitfld.long 0x00 1. " BS1 ,Port G set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port G set bit 0" "No effect,Set" group.long 0x1C++0x03 line.long 0x00 "GPIOG_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" bitfld.long 0x00 15. " LCK15 ,Port G lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port G lock bit 14" "Not locked,Locked" bitfld.long 0x00 13. " LCK13 ,Port G lock bit 13" "Not locked,Locked" textline " " bitfld.long 0x00 12. " LCK12 ,Port G lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port G lock bit 11" "Not locked,Locked" bitfld.long 0x00 10. " LCK10 ,Port G lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port G lock bit 9" "Not locked,Locked" textline " " bitfld.long 0x00 8. " LCK8 ,Port G lock bit 8" "Not locked,Locked" bitfld.long 0x00 7. " LCK7 ,Port G lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port G lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port G lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port G lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port G lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port G lock bit 2" "Not locked,Locked" bitfld.long 0x00 1. " LCK1 ,Port G lock bit 1" "Not locked,Locked" textline " " bitfld.long 0x00 0. " LCK0 ,Port G lock bit 0" "Not locked,Locked" textline " " width 15. sif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOG_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port G pin 7" ",,,,I2C3_SCL,,,,LPUART1_TX,,,,FMC_INT,SAI1_MCLK_A,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port G pin 6" ",,,,I2C3_SMBA,,,,LPUART1_RTS_DE,,,,,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port G pin 5" ",,,,,SPI1_NSS,,,LPUART1_CTS,,,,FMC_A15,SAI2_SD_B,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port G pin 4" ",,,,,SPI1_MOSI,,,,,,,FMC_A14,SAI2_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port G pin 3" ",,,,,SPI1_MISO,,,,,,,FMC_A13,SAI2_FS_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port G pin 2" ",,,,,SPI1_SCK,,,,,,,FMC_A12,SAI2_SCK_B,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port G pin 1" ",,,,,,,,,TSC_G8_IO4,,,FMC_A11,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port G pin 0" ",,,,,,,,,TSC_G8_IO3,,,FMC_A10,,,EVENTOUT" line.long 0x04 "GPIOG_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port G pin 15" ",LPTIM1_OUT,,,I2C1_SMBA,,,,,,DCMI_D13,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port G pin 14" ",,,,I2C1_SCL,,,,,,,,FMC_A25,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port G pin 13" ",,,,I2C1_SDA,,,USART1_CK,,,,,FMC_A24,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port G pin 12" ",LPTIM1_ETR,,,,,SPI3_NSS,USART1_RTS_DE,,,,,FMC_NE4,SAI2_SD_A,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port G pin 11" ",LPTIM1_IN2,,,,,SPI3_MOSI,USART1_CTS,,,,,,SAI2_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port G pin 10" ",LPTIM1_IN1,,,,,SPI3_MISO,USART1_RX,,,,,FMC_NE3,SAI2_FS_A,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port G pin 9" ",,,,,,SPI3_SCK,USART1_TX,,,,,FMC_NCE3/FMC_NE2,SAI2_SCK_A,TIM15_CH1N,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port G pin 8" ",,,,I2C3_SDA,,,,LPUART1_RX,,,,,,,EVENTOUT" else group.long 0x20++0x07 line.long 0x00 "GPIOG_AFRL,GPIO alternate function low register" bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port G pin 7" ",,,,I2C3_SCL,,,,LPUART1_TX,,,,FMC_INT3,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port G pin 6" ",,,,I2C3_SMBA,,,,LPUART1_RTS_DE,,,,,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port G pin 5" ",,,,,SPI1_NSS,,,LPUART1_CTS,,,,FMC_A15,SAI2_SD_B,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port G pin 4" ",,,,,SPI1_MOSI,,,,,,,FMC_A,SAI2_MCLK_B,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port G pin 3" ",,,,,SPI1_MISO,,,,,,,FMC_A,SAI2_FS_B,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port G pin 2" ",,,,,SPI1_SCK,,,,,,,FMC_A,SAI2_SCK_B,,EVENTOUT" textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port G pin 1" ",,,,,,,,,TSC_G8_IO4,,,FMC_A,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port G pin 0" ",,,,,,,,,TSC_G8_IO3,,,FMC_A,,,EVENTOUT" line.long 0x04 "GPIOG_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port G pin 15" ",LPTIM1_OUT,,,I2C1_SMBA,,,,,,,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port G pin 14" ",,,,I2C1_SCL,,,,,,,,FMC_A25,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port G pin 13" ",,,,I2C1_SDA,,,USART1_CK,,,,,FMC_A24,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port G pin 12" ",LPTIM1_ETR,,,,,SPI3_NSS,USART1_RTS_DE,,,,,FMC_NE4,SAI2_SD_A,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port G pin 11" ",LPTIM1_IN2,,,,,SPI3_MOSI,USART1_CTS,,,,,,SAI2_MCLK_A,TIM15_CH2,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port G pin 10" ",LPTIM1_IN1,,,,,SPI3_MISO,USART1_RX,,,,,FMC_NE3,SAI2_FS_A,TIM15_CH1,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port G pin 9" ",,,,,,SPI3_SCK,USART1_TX,,,,,FMC_NCE3/FMC_NE2,SAI2_SCK_A,TIM15_CH1N,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port G pin 8" ",,,,I2C3_SDA,,,,LPUART1_RX,,,,,,,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOG_BRR,GPIO port bit reset register" bitfld.long 0x00 15. " BR15 ,Port G Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port G Reset bit 14" "No action,Reset" bitfld.long 0x00 13. " BR13 ,Port G Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port G Reset bit 12" "No action,Reset" textline " " bitfld.long 0x00 11. " BR11 ,Port G Reset bit 11" "No action,Reset" bitfld.long 0x00 10. " BR10 ,Port G Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port G Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port G Reset bit 8" "No action,Reset" textline " " bitfld.long 0x00 7. " BR7 ,Port G Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port G Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port G Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port G Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port G Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port G Reset bit 2" "No action,Reset" bitfld.long 0x00 1. " BR1 ,Port G Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port G Reset bit 0" "No action,Reset" sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOG_ASCR,GPIO port analog switch control register" bitfld.long 0x00 15. " ASC15 ,Port G Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port G Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port G Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port G Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port G Reset bit 11" "Disconnected,Connected" bitfld.long 0x00 10. " ASC10 ,Port G Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port G Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port G Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port G Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port G Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port G Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port G Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port G Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port G Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port G Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port G Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end endif sif !cpuis("STM32L471VG") tree "GPIO H" base ad:0x48001C00 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOH_MODER,GPIO port mode register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 30.--31. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 28.--29. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 26.--27. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 24.--25. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 22.--23. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 20.--21. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 18.--19. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 14.--15. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " endif bitfld.long 0x00 6.--7. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 4.--5. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 2.--3. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port H configuration bits" "Input,Gen purp output,Alt function,Analog" endif line.long 0x04 "GPIOH_OTYPER,GPIO port output type register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x04 15. " OT15 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 14. " OT14 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 13. " OT13 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 12. " OT12 ,Port H configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 11. " OT11 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 10. " OT10 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 9. " OT9 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 8. " OT8 ,Port H configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 7. " OT7 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port H configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port H configuration bits" "Push-pull,Open-drain" textline " " else bitfld.long 0x04 3. " OT3 ,Port H configuration bits" "Push-pull,Open-drain" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x04 1. " OT1 ,Port H configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port H configuration bits" "Push-pull,Open-drain" endif line.long 0x08 "GPIOH_OSPEEDR,GPIO port output speed register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x08 30.--31. " OSPEED15[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 28.--29. " OSPEED14[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 26.--27. " OSPEED13[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 24.--25. " OSPEED12[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 22.--23. " OSPEED11[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 20.--21. " OSPEED10[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 18.--19. " OSPEED9[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 14.--15. " OSPEED7[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" textline " " else bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port H configuration bits" "Low,Medium,High,Very high" endif line.long 0x0C "GPIOH_PUPDR,GPIO port pull-up/pull-down register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x0C 30.--31. " PUPD15[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 28.--29. " PUPD14[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 26.--27. " PUPD13[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 24.--25. " PUPD12[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 22.--23. " PUPD11[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 20.--21. " PUPD10[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 18.--19. " PUPD9[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 14.--15. " PUPD7[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " else bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port H configuration bits" "No pulls,Pull-up,Pull-down,?..." endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOH_IDR,GPIO port input data register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 15. " ID15 ,Port input data bit 15" "0,1" bitfld.long 0x00 14. " ID14 ,Port input data bit 14" "0,1" bitfld.long 0x00 13. " ID13 ,Port input data bit 13" "0,1" bitfld.long 0x00 12. " ID12 ,Port input data bit 12" "0,1" textline " " bitfld.long 0x00 11. " ID11 ,Port input data bit 11" "0,1" bitfld.long 0x00 10. " ID10 ,Port input data bit 10" "0,1" bitfld.long 0x00 9. " ID9 ,Port input data bit 9" "0,1" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" textline " " bitfld.long 0x00 7. " ID7 ,Port input data bit 7" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" textline " " else bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" endif group.long 0x14++0x03 line.long 0x00 "GPIOH_ODR,GPIO port output data register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 15. " OD15 ,Port output data bit 15" "0,1" bitfld.long 0x00 14. " OD14 ,Port output data bit 14" "0,1" bitfld.long 0x00 13. " OD13 ,Port output data bit 13" "0,1" bitfld.long 0x00 12. " OD12 ,Port output data bit 12" "0,1" textline " " bitfld.long 0x00 11. " OD11 ,Port output data bit 11" "0,1" bitfld.long 0x00 10. " OD10 ,Port output data bit 10" "0,1" bitfld.long 0x00 9. " OD9 ,Port output data bit 9" "0,1" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" textline " " bitfld.long 0x00 7. " OD7 ,Port output data bit 7" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" textline " " else bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" endif wgroup.long 0x18++0x03 line.long 0x00 "GPIOH_BSRR,GPIO port bit set/reset register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 31. " BR15 ,Port H reset bit 15" "No effect,Reset" bitfld.long 0x00 30. " BR14 ,Port H reset bit 14" "No effect,Reset" bitfld.long 0x00 29. " BR13 ,Port H reset bit 13" "No effect,Reset" bitfld.long 0x00 28. " BR12 ,Port H reset bit 12" "No effect,Reset" textline " " bitfld.long 0x00 27. " BR11 ,Port H reset bit 11" "No effect,Reset" bitfld.long 0x00 26. " BR10 ,Port H reset bit 10" "No effect,Reset" bitfld.long 0x00 25. " BR9 ,Port H reset bit 9" "No effect,Reset" bitfld.long 0x00 24. " BR8 ,Port H reset bit 8" "No effect,Reset" textline " " bitfld.long 0x00 23. " BR7 ,Port H reset bit 7" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port H reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port H reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port H reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port H reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port H reset bit 2" "No effect,Reset" textline " " else bitfld.long 0x00 19. " BR3 ,Port H reset bit 3" "No effect,Reset" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 17. " BR1 ,Port H reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port H reset bit 0" "No effect,Reset" textline " " endif sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 15. " BS15 ,Port H set bit 15" "No effect,Set" bitfld.long 0x00 14. " BS14 ,Port H set bit 14" "No effect,Set" bitfld.long 0x00 13. " BS13 ,Port H set bit 13" "No effect,Set" bitfld.long 0x00 12. " BS12 ,Port H set bit 12" "No effect,Set" textline " " bitfld.long 0x00 11. " BS11 ,Port H set bit 11" "No effect,Set" bitfld.long 0x00 10. " BS10 ,Port H set bit 10" "No effect,Set" bitfld.long 0x00 9. " BS9 ,Port H set bit 9" "No effect,Set" bitfld.long 0x00 8. " BS8 ,Port H set bit 8" "No effect,Set" textline " " bitfld.long 0x00 7. " BS7 ,Port H set bit 7" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port H set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port H set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port H set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port H set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port H set bit 2" "No effect,Set" textline " " else bitfld.long 0x00 3. " BS3 ,Port H set bit 3" "No effect,Set" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 1. " BS1 ,Port H set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port H set bit 0" "No effect,Set" endif group.long 0x1C++0x03 line.long 0x00 "GPIOH_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 15. " LCK15 ,Port H lock bit 15" "Not locked,Locked" bitfld.long 0x00 14. " LCK14 ,Port H lock bit 14" "Not locked,Locked" bitfld.long 0x00 13. " LCK13 ,Port H lock bit 13" "Not locked,Locked" textline " " bitfld.long 0x00 12. " LCK12 ,Port H lock bit 12" "Not locked,Locked" bitfld.long 0x00 11. " LCK11 ,Port H lock bit 11" "Not locked,Locked" bitfld.long 0x00 10. " LCK10 ,Port H lock bit 10" "Not locked,Locked" bitfld.long 0x00 9. " LCK9 ,Port H lock bit 9" "Not locked,Locked" textline " " bitfld.long 0x00 8. " LCK8 ,Port H lock bit 8" "Not locked,Locked" bitfld.long 0x00 7. " LCK7 ,Port H lock bit 7" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port H lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port H lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port H lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port H lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port H lock bit 2" "Not locked,Locked" textline " " else bitfld.long 0x00 3. " LCK3 ,Port H lock bit 3" "Not locked,Locked" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 1. " LCK1 ,Port H lock bit 1" "Not locked,Locked" bitfld.long 0x00 0. " LCK0 ,Port H lock bit 0" "Not locked,Locked" endif textline " " width 15. sif (cpuis("STM32L431K*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC")) group.long 0x20++0x07 line.long 0x00 "GPIOH_AFRL,GPIO alternate function low register" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port H pin 3" ",,,,,,,,,,,,,,,EVENTOUT" elif (cpuis("STM32L4?6*")) group.long 0x20++0x07 line.long 0x00 "GPIOH_AFRL,GPIO alternate function low register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 28.--31. " AFSEL7[3:0] ,Alternate function selection for port H pin 7" ",,,,I2C3_SCL,,,,,,DCMI_D9,,,,,EVENTOUT" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port H pin 6" ",,,,I2C3_SMBA,,,,,,DCMI_D8,,,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port H pin 5" ",,,,I2C2_SDA,,,,,,DCMI_PIXCLK,,,,,EVENTOUT" textline " " bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port H pin 4" ",,,,I2C2_SCL,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port H pin 3" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port H pin 2" ",,,QUADSPI_BK2_IO0,,,,,,,,,,,,EVENTOUT" else bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port H pin 3" ",,,,,,,,,,,,,,,EVENTOUT" endif textline " " bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT" sif (cpuis("STM32L4?6A*")) line.long 0x04 "GPIOH_AFRH,GPIO alternate function high register" bitfld.long 0x04 28.--31. " AFSEL15[3:0] ,Alternate function selection for port H pin 15" ",,,TIM8_CH3N,,,,,,,DCMI_D11,,,,,EVENTOUT" bitfld.long 0x04 24.--27. " AFSEL14[3:0] ,Alternate function selection for port H pin 14" ",,,TIM8_CH2N,,,,,,,DCMI_D4,,,,,EVENTOUT" bitfld.long 0x04 20.--23. " AFSEL13[3:0] ,Alternate function selection for port H pin 13" ",,,TIM8_CH1N,,,,,,CAN1_TX,,,,,,EVENTOUT" textline " " bitfld.long 0x04 16.--19. " AFSEL12[3:0] ,Alternate function selection for port H pin 12" ",,TIM5_CH3,,,,,,,,DCMI_D3,,,,,EVENTOUT" bitfld.long 0x04 12.--15. " AFSEL11[3:0] ,Alternate function selection for port H pin 11" ",,TIM5_CH2,,,,,,,,DCMI_D2,,,,,EVENTOUT" bitfld.long 0x04 8.--11. " AFSEL10[3:0] ,Alternate function selection for port H pin 10" ",,TIM5_CH1,,,,,,,,DCMI_D1,,,,,EVENTOUT" textline " " bitfld.long 0x04 4.--7. " AFSEL9[3:0] ,Alternate function selection for port H pin 9" ",,,,I2C3_SMBA,,,,,,DCMI_D0,,,,,EVENTOUT" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port H pin 8" ",,,,I2C3_SDA,,,,,,DCMI_HSYNC,,,,,EVENTOUT" endif else group.long 0x20++0x07 line.long 0x00 "GPIOH_AFRL,GPIO alternate function low register" bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port H pin 3" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port H pin 1" ",,,,,,,,,,,,,,,EVENTOUT" bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port H pin 0" ",,,,,,,,,,,,,,,EVENTOUT" endif width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOH_BRR,GPIO port bit reset register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 15. " BR15 ,Port H Reset bit 15" "No action,Reset" bitfld.long 0x00 14. " BR14 ,Port H Reset bit 14" "No action,Reset" bitfld.long 0x00 13. " BR13 ,Port H Reset bit 13" "No action,Reset" bitfld.long 0x00 12. " BR12 ,Port H Reset bit 12" "No action,Reset" textline " " bitfld.long 0x00 11. " BR11 ,Port H Reset bit 11" "No action,Reset" bitfld.long 0x00 10. " BR10 ,Port H Reset bit 10" "No action,Reset" bitfld.long 0x00 9. " BR9 ,Port H Reset bit 9" "No action,Reset" bitfld.long 0x00 8. " BR8 ,Port H Reset bit 8" "No action,Reset" textline " " bitfld.long 0x00 7. " BR7 ,Port H Reset bit 7" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port H Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port H Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port H Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port H Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port H Reset bit 2" "No action,Reset" textline " " else bitfld.long 0x00 3. " BR3 ,Port H Reset bit 3" "No action,Reset" textline " " endif sif (!cpuis("STM32L431K*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L442KC")) bitfld.long 0x00 1. " BR1 ,Port H Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port H Reset bit 0" "No action,Reset" endif sif (cpuis("STM32L4?6*")) group.long 0x2C++0x03 line.long 0x00 "GPIOH_ASCR,GPIO port analog switch control register" sif (cpuis("STM32L4?6A*")) bitfld.long 0x00 15. " ASC15 ,Port H Reset bit 15" "Disconnected,Connected" bitfld.long 0x00 14. " ASC14 ,Port H Reset bit 14" "Disconnected,Connected" bitfld.long 0x00 13. " ASC13 ,Port H Reset bit 13" "Disconnected,Connected" bitfld.long 0x00 12. " ASC12 ,Port H Reset bit 12" "Disconnected,Connected" textline " " bitfld.long 0x00 11. " ASC11 ,Port H Reset bit 11" "Disconnected,Connected" bitfld.long 0x00 10. " ASC10 ,Port H Reset bit 10" "Disconnected,Connected" bitfld.long 0x00 9. " ASC9 ,Port H Reset bit 9" "Disconnected,Connected" bitfld.long 0x00 8. " ASC8 ,Port H Reset bit 8" "Disconnected,Connected" textline " " bitfld.long 0x00 7. " ASC7 ,Port H Reset bit 7" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port H Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port H Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port H Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port H Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port H Reset bit 2" "Disconnected,Connected" textline " " else bitfld.long 0x00 3. " ASC3 ,Port H Reset bit 3" "Disconnected,Connected" textline " " endif bitfld.long 0x00 1. " ASC1 ,Port H Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port H Reset bit 0" "Disconnected,Connected" endif width 0x0B tree.end endif sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) tree "GPIO I" base ad:0x48002000 width 15. group.long 0x00++0x0F line.long 0x00 "GPIOI_MODER,GPIO port mode register" bitfld.long 0x00 16.--17. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 12.--13. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 10.--11. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 8.--9. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" textline " " bitfld.long 0x00 6.--7. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 4.--5. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 2.--3. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" bitfld.long 0x00 0.--1. " MODE[1:0] ,Port I configuration bits" "Input,Gen purp output,Alt function,Analog" line.long 0x04 "GPIOI_OTYPER,GPIO port output type register" bitfld.long 0x04 8. " OT8 ,Port I configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 6. " OT6 ,Port I configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 5. " OT5 ,Port I configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 4. " OT4 ,Port I configuration bits" "Push-pull,Open-drain" textline " " bitfld.long 0x04 3. " OT3 ,Port I configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 2. " OT2 ,Port I configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 1. " OT1 ,Port I configuration bits" "Push-pull,Open-drain" bitfld.long 0x04 0. " OT0 ,Port I configuration bits" "Push-pull,Open-drain" line.long 0x08 "GPIOI_OSPEEDR,GPIO port output speed register" bitfld.long 0x08 16.--17. " OSPEED8[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 12.--13. " OSPEED6[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 10.--11. " OSPEED5[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 8.--9. " OSPEED4[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" textline " " bitfld.long 0x08 6.--7. " OSPEED3[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 4.--5. " OSPEED2[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 2.--3. " OSPEED1[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" bitfld.long 0x08 0.--1. " OSPEED0[1:0] ,Port I configuration bits" "Low,Medium,High,Very high" line.long 0x0C "GPIOI_PUPDR,GPIO port pull-up/pull-down register" bitfld.long 0x0C 16.--17. " PUPD8[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 12.--13. " PUPD6[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 10.--11. " PUPD5[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 8.--9. " PUPD4[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." textline " " bitfld.long 0x0C 6.--7. " PUPD3[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 4.--5. " PUPD2[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 2.--3. " PUPD1[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." bitfld.long 0x0C 0.--1. " PUPD0[1:0] ,Port I configuration bits" "No pulls,Pull-up,Pull-down,?..." rgroup.long 0x10++0x03 line.long 0x00 "GPIOI_IDR,GPIO port input data register" bitfld.long 0x00 8. " ID8 ,Port input data bit 8" "0,1" bitfld.long 0x00 6. " ID6 ,Port input data bit 6" "0,1" bitfld.long 0x00 5. " ID5 ,Port input data bit 5" "0,1" bitfld.long 0x00 4. " ID4 ,Port input data bit 4" "0,1" textline " " bitfld.long 0x00 3. " ID3 ,Port input data bit 3" "0,1" bitfld.long 0x00 2. " ID2 ,Port input data bit 2" "0,1" bitfld.long 0x00 1. " ID1 ,Port input data bit 1" "0,1" bitfld.long 0x00 0. " ID0 ,Port input data bit 0" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIOI_ODR,GPIO port output data register" bitfld.long 0x00 8. " OD8 ,Port output data bit 8" "0,1" bitfld.long 0x00 6. " OD6 ,Port output data bit 6" "0,1" bitfld.long 0x00 5. " OD5 ,Port output data bit 5" "0,1" bitfld.long 0x00 4. " OD4 ,Port output data bit 4" "0,1" textline " " bitfld.long 0x00 3. " OD3 ,Port output data bit 3" "0,1" bitfld.long 0x00 2. " OD2 ,Port output data bit 2" "0,1" bitfld.long 0x00 1. " OD1 ,Port output data bit 1" "0,1" bitfld.long 0x00 0. " OD0 ,Port output data bit 0" "0,1" wgroup.long 0x18++0x03 line.long 0x00 "GPIOI_BSRR,GPIO port bit set/reset register" bitfld.long 0x00 24. " BR8 ,Port I reset bit 8" "No effect,Reset" bitfld.long 0x00 22. " BR6 ,Port I reset bit 6" "No effect,Reset" bitfld.long 0x00 21. " BR5 ,Port I reset bit 5" "No effect,Reset" bitfld.long 0x00 20. " BR4 ,Port I reset bit 4" "No effect,Reset" textline " " bitfld.long 0x00 19. " BR3 ,Port I reset bit 3" "No effect,Reset" bitfld.long 0x00 18. " BR2 ,Port I reset bit 2" "No effect,Reset" bitfld.long 0x00 17. " BR1 ,Port I reset bit 1" "No effect,Reset" bitfld.long 0x00 16. " BR0 ,Port I reset bit 0" "No effect,Reset" textline " " bitfld.long 0x00 8. " BS8 ,Port I set bit 8" "No effect,Set" bitfld.long 0x00 6. " BS6 ,Port I set bit 6" "No effect,Set" bitfld.long 0x00 5. " BS5 ,Port I set bit 5" "No effect,Set" bitfld.long 0x00 4. " BS4 ,Port I set bit 4" "No effect,Set" textline " " bitfld.long 0x00 3. " BS3 ,Port I set bit 3" "No effect,Set" bitfld.long 0x00 2. " BS2 ,Port I set bit 2" "No effect,Set" bitfld.long 0x00 1. " BS1 ,Port I set bit 1" "No effect,Set" bitfld.long 0x00 0. " BS0 ,Port I set bit 0" "No effect,Set" group.long 0x1C++0x03 line.long 0x00 "GPIOI_LCKR,GPIO port configuration lock register" bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active" bitfld.long 0x00 8. " LCK8 ,Port I lock bit 8" "Not locked,Locked" bitfld.long 0x00 6. " LCK6 ,Port I lock bit 6" "Not locked,Locked" bitfld.long 0x00 5. " LCK5 ,Port I lock bit 5" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LCK4 ,Port I lock bit 4" "Not locked,Locked" bitfld.long 0x00 3. " LCK3 ,Port I lock bit 3" "Not locked,Locked" bitfld.long 0x00 2. " LCK2 ,Port I lock bit 2" "Not locked,Locked" bitfld.long 0x00 1. " LCK1 ,Port I lock bit 1" "Not locked,Locked" textline " " bitfld.long 0x00 0. " LCK0 ,Port I lock bit 0" "Not locked,Locked" textline " " width 15. group.long 0x20++0x07 line.long 0x00 "GPIOI_AFRL,GPIO alternate function low register" bitfld.long 0x00 24.--27. " AFSEL6[3:0] ,Alternate function selection for port I pin 6" ",,,TIM8_CH2,,,,,,,DCMI_D6,,,,,EVENTOUT" bitfld.long 0x00 20.--23. " AFSEL5[3:0] ,Alternate function selection for port I pin 5" ",,,TIM8_CH1,,,,,,,DCMI_VSYNC,,,,,EVENTOUT" bitfld.long 0x00 16.--19. " AFSEL4[3:0] ,Alternate function selection for port I pin 4" ",,,TIM8_BKIN,,,,,,,DCMI_D5,,,,,EVENTOUT" textline " " bitfld.long 0x00 12.--15. " AFSEL3[3:0] ,Alternate function selection for port I pin 3" ",,,TIM8_ETR,,SPI2_MOSI,,,,,DCMI_D10,,,,,EVENTOUT" bitfld.long 0x00 8.--11. " AFSEL2[3:0] ,Alternate function selection for port I pin 2" ",,,TIM8_CH4,,SPI2_MISO,,,,,DCMI_D9,,,,,EVENTOUT" bitfld.long 0x00 4.--7. " AFSEL1[3:0] ,Alternate function selection for port I pin 1" ",,,,,SPI2_SCK,,,,,DCMI_D8,,,,,EVENTOUT" textline " " bitfld.long 0x00 0.--3. " AFSEL0[3:0] ,Alternate function selection for port I pin 0" ",,TIM5_CH4,,,SPI2_NSS,,,,,,,,,,EVENTOUT" line.long 0x04 "GPIOI_AFRH,GPIO alternate function high register" bitfld.long 0x04 0.--3. " AFSEL8[3:0] ,Alternate function selection for port I pin 8" ",,,,,,,,,,DCMI_D13,,,,,EVENTOUT" width 0x0B textline " " width 15. wgroup.long 0x28++0x03 line.long 0x00 "GPIOI_BRR,GPIO port bit reset register" bitfld.long 0x00 8. " BR8 ,Port I Reset bit 8" "No action,Reset" bitfld.long 0x00 6. " BR6 ,Port I Reset bit 6" "No action,Reset" bitfld.long 0x00 5. " BR5 ,Port I Reset bit 5" "No action,Reset" bitfld.long 0x00 4. " BR4 ,Port I Reset bit 4" "No action,Reset" textline " " bitfld.long 0x00 3. " BR3 ,Port I Reset bit 3" "No action,Reset" bitfld.long 0x00 2. " BR2 ,Port I Reset bit 2" "No action,Reset" bitfld.long 0x00 1. " BR1 ,Port I Reset bit 1" "No action,Reset" bitfld.long 0x00 0. " BR0 ,Port I Reset bit 0" "No action,Reset" group.long 0x2C++0x03 line.long 0x00 "GPIOI_ASCR,GPIO port analog switch control register" bitfld.long 0x00 8. " ASC8 ,Port I Reset bit 8" "Disconnected,Connected" bitfld.long 0x00 6. " ASC6 ,Port I Reset bit 6" "Disconnected,Connected" bitfld.long 0x00 5. " ASC5 ,Port I Reset bit 5" "Disconnected,Connected" bitfld.long 0x00 4. " ASC4 ,Port I Reset bit 4" "Disconnected,Connected" textline " " bitfld.long 0x00 3. " ASC3 ,Port I Reset bit 3" "Disconnected,Connected" bitfld.long 0x00 2. " ASC2 ,Port I Reset bit 2" "Disconnected,Connected" bitfld.long 0x00 1. " ASC1 ,Port I Reset bit 1" "Disconnected,Connected" bitfld.long 0x00 0. " ASC0 ,Port I Reset bit 0" "Disconnected,Connected" width 0x0B tree.end endif tree.end tree "SYSCFG (System configuration controller)" base ad:0x40010000 width 16. sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) group.long 0x00++0x03 line.long 0x00 "SYSCFG_MEMRMP,SYSCFG memory remap register" bitfld.long 0x00 8. " FB_MODE ,Flash Bank mode selection" "Bank1,Bank2" bitfld.long 0x00 0.--2. " MEM_MODE ,Memory mapping selection" "Main flash,System flash,FMC bank1,SRAM1,,,QUADSPI,?..." else group.long 0x00++0x03 line.long 0x00 "SYSCFG_MEMRMP,SYSCFG memory remap register" bitfld.long 0x00 0.--2. " MEM_MODE ,Memory mapping selection" "Main flash,System flash,,SRAM1,,,QUADSPI,?..." endif group.long 0x04++0x03 line.long 0x00 "SYSCFG_CFGR1,SYSCFG configuration register 1" bitfld.long 0x00 31. " FPU_IE[5] ,Inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " FPU_IE[4] ,Input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " FPU_IE[3] ,Overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FPU_IE[2] ,Underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FPU_IE[1] ,Divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " FPU_IE[0] ,Invalid operation interrupt enable" "Disabled,Enabled" sif cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L443*")||cpuis("STM32L442*")||cpuis("STM32L433*")||cpuis("STM32L432*")||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 23. " I2C4_FMP ,I2C4 Fast-mode Plus driving capability activation" "Disabled,Enabled" endif textline " " bitfld.long 0x00 22. " I2C3_FMP ,I2C3 Fast-mode Plus driving capability activation" "Disabled,Enabled" bitfld.long 0x00 21. " I2C2_FMP ,I2C2 Fast-mode Plus driving capability activation" "Disabled,Enabled" bitfld.long 0x00 20. " I2C1_FMP ,I2C1 Fast-mode Plus driving capability activation" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " I2C_PB9_FMP ,Fast-mode Plus (Fm+) driving capability activation on PB9" "Standard,Fm+" bitfld.long 0x00 18. " I2C_PB8_FMP ,Fast-mode Plus (Fm+) driving capability activation on PB8" "Standard,Fm+" bitfld.long 0x00 17. " I2C_PB7_FMP ,Fast-mode Plus (Fm+) driving capability activation on PB7" "Standard,Fm+" textline " " bitfld.long 0x00 16. " I2C_PB6_FMP ,Fast-mode Plus (Fm+) driving capability activation on PB6" "Standard,Fm+" bitfld.long 0x00 8. " BOOSTEN ,I/O analog switch voltage booster enable" "VDDA,VDD" bitfld.long 0x00 0. " FWDIS ,Firewall disable" "No,Yes" sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L451*")) group.long 0x08++0x0F line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1" bitfld.long 0x00 12.--14. " EXTI3 ,EXTI 3 configuration bits" "PA[3],PB[3],PC[3],PD[3],PE[3],,,PH[3]" bitfld.long 0x00 8.--10. " EXTI2 ,EXTI 2 configuration bits" "PA[2],PB[2],PC[2],PD[2],PE[2],?..." bitfld.long 0x00 4.--6. " EXTI1 ,EXTI 1 configuration bits" "PA[1],PB[1],PC[1],PD[1],PE[1],,,PH[1]" bitfld.long 0x00 0.--2. " EXTI0 ,EXTI 0 configuration bits" "PA[0],PB[0],PC[0],PD[0],PE[0],,,PH[0]" line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2" bitfld.long 0x04 12.--14. " EXTI7 ,EXTI 7 configuration bits" "PA[7],PB[7],PC[7],PD[7],PE[7],?..." bitfld.long 0x04 8.--10. " EXTI6 ,EXTI 6 configuration bits" "PA[6],PB[6],PC[6],PD[6],PE[6],?..." bitfld.long 0x04 4.--6. " EXTI5 ,EXTI 5 configuration bits" "PA[5],PB[5],PC[5],PD[5],PE[5],?..." bitfld.long 0x04 0.--2. " EXTI4 ,EXTI 4 configuration bits" "PA[4],PB[4],PC[4],PD[4],PE[4],?..." line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3" bitfld.long 0x08 12.--14. " EXTI11 ,EXTI 11 configuration bits" "PA[11],PB[11],PC[11],PD[11],PE[11],?..." bitfld.long 0x08 8.--10. " EXTI10 ,EXTI 10 configuration bits" "PA[10],PB[10],PC[10],PD[10],PE[10],?..." bitfld.long 0x08 4.--6. " EXTI9 ,EXTI 9 configuration bits" "PA[9],PB[9],PC[9],PD[9],PE[9],?..." bitfld.long 0x08 0.--2. " EXTI8 ,EXTI 8 configuration bits" "PA[8],PB[8],PC[8],PD[8],PE[8],?..." line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4" bitfld.long 0x0C 12.--14. " EXTI15 ,EXTI 15 configuration bits" "PA[15],PB[15],PC[15],PD[15],PE[15],?..." bitfld.long 0x0C 8.--10. " EXTI14 ,EXTI 14 configuration bits" "PA[14],PB[14],PC[14],PD[14],PE[14],?..." bitfld.long 0x0C 4.--6. " EXTI13 ,EXTI 13 configuration bits" "PA[13],PB[13],PC[13],PD[13],PE[13],?..." bitfld.long 0x0C 0.--2. " EXTI12 ,EXTI 12 configuration bits" "PA[12],PB[12],PC[12],PD[12],PE[12],?..." elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) group.long 0x08++0x0F line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1" bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration bits" "PA[3],PB[3],PC[3],PD[3],PE[3],PF[3],PG[3],PH[3],PI[3],?..." bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration bits" "PA[2],PB[2],PC[2],PD[2],PE[2],PF[2],PG[2],PH[2],PI[2],?..." bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration bits" "PA[1],PB[1],PC[1],PD[1],PE[1],PF[1],PG[1],PH[1],PI[1],?..." bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration bits" "PA[0],PB[0],PC[0],PD[0],PE[0],PF[0],PG[0],PH[0],PI[0],?..." line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2" bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration bits" "PA[7],PB[7],PC[7],PD[7],PE[7],PF[7],PG[7],PH[7],PI[7],?..." bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration bits" "PA[6],PB[6],PC[6],PD[6],PE[6],PF[6],PG[6],PH[6],PI[6],?..." bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration bits" "PA[5],PB[5],PC[5],PD[5],PE[5],PF[5],PG[5],PH[5],PI[5],?..." bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration bits" "PA[4],PB[4],PC[4],PD[4],PE[4],PF[4],PG[4],PH[4],PI[4],?..." line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3" bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration bits" "PA[11],PB[11],PC[11],PD[11],PE[11],PF[11],PG[11],PH[11],PI[11],?..." bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration bits" "PA[10],PB[10],PC[10],PD[10],PE[10],PF[10],PG[10],PH[10],PI[10],?..." bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration bits" "PA[9],PB[9],PC[9],PD[9],PE[9],PF[9],PG[9],PH[9],PI[9],?..." bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration bits" "PA[8],PB[8],PC[8],PD[8],PE[8],PF[8],PG[8],PH[8],PI[8],?..." line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4" bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration bits" "PA[15],PB[15],PC[15],PD[15],PE[15],PF[15],PG[15],PH[15],?..." bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration bits" "PA[14],PB[14],PC[14],PD[14],PE[14],PF[14],PG[14],PH[14],?..." bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration bits" "PA[13],PB[13],PC[13],PD[13],PE[13],PF[13],PG[13],PH[13],?..." bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration bits" "PA[12],PB[12],PC[12],PD[12],PE[12],PF[12],PG[12],PH[12],?..." elif (cpuis("STM32L475*")) group.long 0x08++0x0F line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1" bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration bits" "PA[3],PB[3],PC[3],PD[3],PE[3],PF[3],PG[3],?..." bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration bits" "PA[2],PB[2],PC[2],PD[2],PE[2],PF[2],PG[2],?..." bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration bits" "PA[1],PB[1],PC[1],PD[1],PE[1],PF[1],PG[1],PH[1],?..." bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration bits" "PA[0],PB[0],PC[0],PD[0],PE[0],PF[0],PG[0],PH[0],?..." line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2" bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration bits" "PA[7],PB[7],PC[7],PD[7],PE[7],PF[7],PG[7],?..." bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration bits" "PA[6],PB[6],PC[6],PD[6],PE[6],PF[6],PG[6],?..." bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration bits" "PA[5],PB[5],PC[5],PD[5],PE[5],PF[5],PG[5],?..." bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration bits" "PA[4],PB[4],PC[4],PD[4],PE[4],PF[4],PG[4],?..." line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3" bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration bits" "PA[11],PB[11],PC[11],PD[11],PE[11],PF[11],PG[11],?..." bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration bits" "PA[10],PB[10],PC[10],PD[10],PE[10],PF[10],PG[10],?..." bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration bits" "PA[9],PB[9],PC[9],PD[9],PE[9],PF[9],PG[9],?..." bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration bits" "PA[8],PB[8],PC[8],PD[8],PE[8],PF[8],PG[8],?..." line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4" bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration bits" "PA[15],PB[15],PC[15],PD[15],PE[15],PF[15],PG[15],?..." bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration bits" "PA[14],PB[14],PC[14],PD[14],PE[14],PF[14],PG[14],?..." bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration bits" "PA[13],PB[13],PC[13],PD[13],PE[13],PF[13],PG[13],?..." bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration bits" "PA[12],PB[12],PC[12],PD[12],PE[12],PF[12],PG[12],?..." else group.long 0x08++0x0F line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1" bitfld.long 0x00 12.--14. " EXTI3 ,EXTI 3 configuration bits" "PA[3],PB[3],PC[3],PD[3],PE[3],PF[3],PG[3],?..." bitfld.long 0x00 8.--10. " EXTI2 ,EXTI 2 configuration bits" "PA[2],PB[2],PC[2],PD[2],PE[2],PF[2],PG[2],?..." bitfld.long 0x00 4.--6. " EXTI1 ,EXTI 1 configuration bits" "PA[1],PB[1],PC[1],PD[1],PE[1],PF[1],PG[1],PH[1]" bitfld.long 0x00 0.--2. " EXTI0 ,EXTI 0 configuration bits" "PA[0],PB[0],PC[0],PD[0],PE[0],PF[0],PG[0],PH[0]" line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2" bitfld.long 0x04 12.--14. " EXTI7 ,EXTI 7 configuration bits" "PA[7],PB[7],PC[7],PD[7],PE[7],PF[7],PG[7],?..." bitfld.long 0x04 8.--10. " EXTI6 ,EXTI 6 configuration bits" "PA[6],PB[6],PC[6],PD[6],PE[6],PF[6],PG[6],?..." bitfld.long 0x04 4.--6. " EXTI5 ,EXTI 5 configuration bits" "PA[5],PB[5],PC[5],PD[5],PE[5],PF[5],PG[5],?..." bitfld.long 0x04 0.--2. " EXTI4 ,EXTI 4 configuration bits" "PA[4],PB[4],PC[4],PD[4],PE[4],PF[4],PG[4],?..." line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3" bitfld.long 0x08 12.--14. " EXTI11 ,EXTI 11 configuration bits" "PA[11],PB[11],PC[11],PD[11],PE[11],PF[11],PG[11],?..." bitfld.long 0x08 8.--10. " EXTI10 ,EXTI 10 configuration bits" "PA[10],PB[10],PC[10],PD[10],PE[10],PF[10],PG[10],?..." bitfld.long 0x08 4.--6. " EXTI9 ,EXTI 9 configuration bits" "PA[9],PB[9],PC[9],PD[9],PE[9],PF[9],PG[9],?..." bitfld.long 0x08 0.--2. " EXTI8 ,EXTI 8 configuration bits" "PA[8],PB[8],PC[8],PD[8],PE[8],PF[8],PG[8],?..." line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4" bitfld.long 0x0C 12.--14. " EXTI15 ,EXTI 15 configuration bits" "PA[15],PB[15],PC[15],PD[15],PE[15],PF[15],PG[15],?..." bitfld.long 0x0C 8.--10. " EXTI14 ,EXTI 14 configuration bits" "PA[14],PB[14],PC[14],PD[14],PE[14],PF[14],PG[14],?..." bitfld.long 0x0C 4.--6. " EXTI13 ,EXTI 13 configuration bits" "PA[13],PB[13],PC[13],PD[13],PE[13],PF[13],PG[13],?..." bitfld.long 0x0C 0.--2. " EXTI12 ,EXTI 12 configuration bits" "PA[12],PB[12],PC[12],PD[12],PE[12],PF[12],PG[12],?..." endif group.long 0x18++0x07 line.long 0x00 "SYSCFG_SCSR,SYSCFG SRAM2 control and status register" rbitfld.long 0x00 1. " SRAM2BSY ,SRAM2 busy by erase operation" "Idle,Busy" bitfld.long 0x00 0. " SRAM2ER ,SRAM2 Erase" "Not erased,Erased" line.long 0x04 "SYSCFG_CFGR2,SYSCFG configuration register 2" eventfld.long 0x04 8. " SPF ,SRAM2 parity error flag" "No error,Error" bitfld.long 0x04 3. " ECCL ,ECC Lock" "Unlocked,Locked" bitfld.long 0x04 2. " PVDL ,PVD lock enable bit" "Unlocked,Locked" bitfld.long 0x04 1. " SPL ,SRAM2 parity lock bit enable" "Unlocked,Locked" textline " " bitfld.long 0x04 0. " CLL ,Cortex-M4 LOCKUP (Hardfault) output enable bit" "Unlocked,Locked" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) group.long 0x20++0x03 line.long 0x00 "SYSCFG_SWPR,SYSCFG SRAM2 write protection register" bitfld.long 0x00 31. " P31WP ,SRAM2 page 31 write protection" "Disabled,Enabled" bitfld.long 0x00 30. " P30WP ,SRAM2 page 30 write protection" "Disabled,Enabled" bitfld.long 0x00 29. " P29WP ,SRAM2 page 29 write protection" "Disabled,Enabled" bitfld.long 0x00 28. " P28WP ,SRAM2 page 28 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " P27WP ,SRAM2 page 27 write protection" "Disabled,Enabled" bitfld.long 0x00 26. " P26WP ,SRAM2 page 26 write protection" "Disabled,Enabled" bitfld.long 0x00 25. " P25WP ,SRAM2 page 25 write protection" "Disabled,Enabled" bitfld.long 0x00 24. " P24WP ,SRAM2 page 24 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " P23WP ,SRAM2 page 23 write protection" "Disabled,Enabled" bitfld.long 0x00 22. " P22WP ,SRAM2 page 22 write protection" "Disabled,Enabled" bitfld.long 0x00 21. " P21WP ,SRAM2 page 21 write protection" "Disabled,Enabled" bitfld.long 0x00 20. " P20WP ,SRAM2 page 20 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " P19WP ,SRAM2 page 19 write protection" "Disabled,Enabled" bitfld.long 0x00 18. " P18WP ,SRAM2 page 18 write protection" "Disabled,Enabled" bitfld.long 0x00 17. " P17WP ,SRAM2 page 17 write protection" "Disabled,Enabled" bitfld.long 0x00 16. " P16WP ,SRAM2 page 16 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " P15WP ,SRAM2 page 15 write protection" "Disabled,Enabled" bitfld.long 0x00 14. " P14WP ,SRAM2 page 14 write protection" "Disabled,Enabled" bitfld.long 0x00 13. " P13WP ,SRAM2 page 13 write protection" "Disabled,Enabled" bitfld.long 0x00 12. " P12WP ,SRAM2 page 12 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P11WP ,SRAM2 page 11 write protection" "Disabled,Enabled" bitfld.long 0x00 10. " P10WP ,SRAM2 page 10 write protection" "Disabled,Enabled" bitfld.long 0x00 9. " P9WP ,SRAM2 page 9 write protection" "Disabled,Enabled" bitfld.long 0x00 8. " P8WP ,SRAM2 page 8 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P7WP ,SRAM2 page 7 write protection" "Disabled,Enabled" bitfld.long 0x00 6. " P6WP ,SRAM2 page 6 write protection" "Disabled,Enabled" bitfld.long 0x00 5. " P5WP ,SRAM2 page 5 write protection" "Disabled,Enabled" bitfld.long 0x00 4. " P4WP ,SRAM2 page 4 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P3WP ,SRAM2 page 3 write protection" "Disabled,Enabled" bitfld.long 0x00 2. " P2WP ,SRAM2 page 2 write protection" "Disabled,Enabled" bitfld.long 0x00 1. " P1WP ,SRAM2 page 1 write protection" "Disabled,Enabled" bitfld.long 0x00 0. " P0WP ,SRAM2 page 0 write protection" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "SYSCFG_SWPR,SYSCFG SRAM2 write protection register" bitfld.long 0x00 15. " P15WP ,SRAM2 page 15 write protection" "Disabled,Enabled" bitfld.long 0x00 14. " P14WP ,SRAM2 page 14 write protection" "Disabled,Enabled" bitfld.long 0x00 13. " P13WP ,SRAM2 page 13 write protection" "Disabled,Enabled" bitfld.long 0x00 12. " P12WP ,SRAM2 page 12 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P11WP ,SRAM2 page 11 write protection" "Disabled,Enabled" bitfld.long 0x00 10. " P10WP ,SRAM2 page 10 write protection" "Disabled,Enabled" bitfld.long 0x00 9. " P9WP ,SRAM2 page 9 write protection" "Disabled,Enabled" bitfld.long 0x00 8. " P8WP ,SRAM2 page 8 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P7WP ,SRAM2 page 7 write protection" "Disabled,Enabled" bitfld.long 0x00 6. " P6WP ,SRAM2 page 6 write protection" "Disabled,Enabled" bitfld.long 0x00 5. " P5WP ,SRAM2 page 5 write protection" "Disabled,Enabled" bitfld.long 0x00 4. " P4WP ,SRAM2 page 4 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P3WP ,SRAM2 page 3 write protection" "Disabled,Enabled" bitfld.long 0x00 2. " P2WP ,SRAM2 page 2 write protection" "Disabled,Enabled" bitfld.long 0x00 1. " P1WP ,SRAM2 page 1 write protection" "Disabled,Enabled" bitfld.long 0x00 0. " P0WP ,SRAM2 page 0 write protection" "Disabled,Enabled" endif wgroup.long 0x24++0x03 line.long 0x00 "SYSCFG_SKR,SYSCFG SRAM2 key register" hexmask.long.byte 0x00 0.--7. 1. " KEY ,SRAM2 write protection key for software erase" sif cpuis("STM32L496*")||cpuis("STM32L4A6*") group.long 0x28++0x03 line.long 0x00 "SYSCFG_SWPR2,SYSCFG SRAM2 write protection register 2" bitfld.long 0x00 31. " P63WP , SRAM2 page 63 write protection" "Disabled,Enabled" bitfld.long 0x00 30. " P62WP , SRAM2 page 62 write protection" "Disabled,Enabled" bitfld.long 0x00 29. " P61WP , SRAM2 page 61 write protection" "Disabled,Enabled" bitfld.long 0x00 28. " P60WP , SRAM2 page 60 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " P59WP , SRAM2 page 59 write protection" "Disabled,Enabled" bitfld.long 0x00 26. " P58WP , SRAM2 page 58 write protection" "Disabled,Enabled" bitfld.long 0x00 25. " P57WP , SRAM2 page 57 write protection" "Disabled,Enabled" bitfld.long 0x00 24. " P56WP , SRAM2 page 56 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " P55WP , SRAM2 page 55 write protection" "Disabled,Enabled" bitfld.long 0x00 22. " P54WP , SRAM2 page 54 write protection" "Disabled,Enabled" bitfld.long 0x00 21. " P53WP , SRAM2 page 53 write protection" "Disabled,Enabled" bitfld.long 0x00 20. " P52WP , SRAM2 page 52 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " P51WP , SRAM2 page 51 write protection" "Disabled,Enabled" bitfld.long 0x00 18. " P50WP , SRAM2 page 50 write protection" "Disabled,Enabled" bitfld.long 0x00 17. " P49WP , SRAM2 page 49 write protection" "Disabled,Enabled" bitfld.long 0x00 16. " P48WP , SRAM2 page 48 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " P47WP , SRAM2 page 47 write protection" "Disabled,Enabled" bitfld.long 0x00 14. " P46WP , SRAM2 page 46 write protection" "Disabled,Enabled" bitfld.long 0x00 13. " P45WP , SRAM2 page 45 write protection" "Disabled,Enabled" bitfld.long 0x00 12. " P44WP , SRAM2 page 44 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P43WP , SRAM2 page 43 write protection" "Disabled,Enabled" bitfld.long 0x00 10. " P42WP , SRAM2 page 42 write protection" "Disabled,Enabled" bitfld.long 0x00 9. " P41WP , SRAM2 page 41 write protection" "Disabled,Enabled" bitfld.long 0x00 8. " P40WP , SRAM2 page 40 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P39WP , SRAM2 page 39 write protection" "Disabled,Enabled" bitfld.long 0x00 6. " P38WP , SRAM2 page 38 write protection" "Disabled,Enabled" bitfld.long 0x00 5. " P37WP , SRAM2 page 37 write protection" "Disabled,Enabled" bitfld.long 0x00 4. " P36WP , SRAM2 page 36 write protection" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P35WP , SRAM2 page 35 write protection" "Disabled,Enabled" bitfld.long 0x00 2. " P34WP , SRAM2 page 34 write protection" "Disabled,Enabled" bitfld.long 0x00 1. " P33WP , SRAM2 page 33 write protection" "Disabled,Enabled" bitfld.long 0x00 0. " P32WP , SRAM2 page 32 write protection" "Disabled,Enabled" endif width 0x0B tree.end tree "DMA (Direct memory access)" tree "DMA1" base ad:0x40020000 width 13. rgroup.long 0x00++0x03 line.long 0x00 "DMA1_ISR,DMA interrupt status register" bitfld.long 0x00 27. " TEIF7 ,Channel 7 transfer error flag" "No error,Error" bitfld.long 0x00 26. " HTIF7 ,Channel 7 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 25. " TCIF7 ,Channel 7 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 24. " GIF7 ,Channel 7 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 23. " TEIF6 ,Channel 6 transfer error flag" "No error,Error" bitfld.long 0x00 22. " HTIF6 ,Channel 6 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 21. " TCIF6 ,Channel 6 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 20. " GIF6 ,Channel 6 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 19. " TEIF5 ,Channel 5 transfer error flag" "No error,Error" bitfld.long 0x00 18. " HTIF5 ,Channel 5 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 17. " TCIF5 ,Channel 5 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 16. " GIF5 ,Channel 5 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 15. " TEIF4 ,Channel 4 transfer error flag" "No error,Error" bitfld.long 0x00 14. " HTIF4 ,Channel 4 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 13. " TCIF4 ,Channel 4 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 12. " GIF4 ,Channel 4 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 11. " TEIF3 ,Channel 3 transfer error flag" "No error,Error" bitfld.long 0x00 10. " HTIF3 ,Channel 3 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 9. " TCIF3 ,Channel 3 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 8. " GIF3 ,Channel 3 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 7. " TEIF2 ,Channel 2 transfer error flag" "No error,Error" bitfld.long 0x00 6. " HTIF2 ,Channel 2 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 5. " TCIF2 ,Channel 2 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 4. " GIF2 ,Channel 2 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 3. " TEIF1 ,Channel 1 transfer error flag" "No error,Error" bitfld.long 0x00 2. " HTIF1 ,Channel 1 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 1. " TCIF1 ,Channel 1 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 0. " GIF1 ,Channel 1 global interrupt flag" "No TE/HT/TC,TE/HT/TC" wgroup.long 0x04++0x03 line.long 0x00 "DMA1_IFCR,DMA interrupt flag clear register" bitfld.long 0x00 27. " CTEIF7 ,Channel 7 transfer error clear" "No effect,Clear" bitfld.long 0x00 26. " CHTIF7 ,Channel 7 half transfer clear" "No effect,Clear" bitfld.long 0x00 25. " CTCIF7 ,Channel 7 transfer complete clear" "No effect,Clear" bitfld.long 0x00 24. " CGIF7 ,Channel 7 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 23. " CTEIF6 ,Channel 6 transfer error clear" "No effect,Clear" bitfld.long 0x00 22. " CHTIF6 ,Channel 6 half transfer clear" "No effect,Clear" bitfld.long 0x00 21. " CTCIF6 ,Channel 6 transfer complete clear" "No effect,Clear" bitfld.long 0x00 20. " CGIF6 ,Channel 6 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 19. " CTEIF5 ,Channel 5 transfer error clear" "No effect,Clear" bitfld.long 0x00 18. " CHTIF5 ,Channel 5 half transfer clear" "No effect,Clear" bitfld.long 0x00 17. " CTCIF5 ,Channel 5 transfer complete clear" "No effect,Clear" bitfld.long 0x00 16. " CGIF5 ,Channel 5 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 15. " CTEIF4 ,Channel 4 transfer error clear" "No effect,Clear" bitfld.long 0x00 14. " CHTIF4 ,Channel 4 half transfer clear" "No effect,Clear" bitfld.long 0x00 13. " CTCIF4 ,Channel 4 transfer complete clear" "No effect,Clear" bitfld.long 0x00 12. " CGIF4 ,Channel 4 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 11. " CTEIF3 ,Channel 3 transfer error clear" "No effect,Clear" bitfld.long 0x00 10. " CHTIF3 ,Channel 3 half transfer clear" "No effect,Clear" bitfld.long 0x00 9. " CTCIF3 ,Channel 3 transfer complete clear" "No effect,Clear" bitfld.long 0x00 8. " CGIF3 ,Channel 3 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 7. " CTEIF2 ,Channel 2 transfer error clear" "No effect,Clear" bitfld.long 0x00 6. " CHTIF2 ,Channel 2 half transfer clear" "No effect,Clear" bitfld.long 0x00 5. " CTCIF2 ,Channel 2 transfer complete clear" "No effect,Clear" bitfld.long 0x00 4. " CGIF2 ,Channel 2 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " CTEIF1 ,Channel 1 transfer error clear" "No effect,Clear" bitfld.long 0x00 2. " CHTIF1 ,Channel 1 half transfer clear" "No effect,Clear" bitfld.long 0x00 1. " CTCIF1 ,Channel 1 transfer complete clear" "No effect,Clear" bitfld.long 0x00 0. " CGIF1 ,Channel 1 global interrupt clear" "No effect,Clear" group.long 0x8++0x03 line.long 0x00 "DMA1_CCR1,DMA channel 1 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x8))&0x01)==0x00) group.long (0x8+0x04)++0x03 line.long 0x00 "DMA1_CNDTR1,DMA channel 1 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x8))&0x300)==0x100) group.long (0x8+0x08)++0x03 line.long 0x00 "DMA1_CPAR1,DMA channel 1 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x8))&0x300)==0x200) group.long (0x8+0x08)++0x03 line.long 0x00 "DMA1_CPAR1,DMA channel 1 peripheral address register" endif if (((per.l(ad:0x40020000+0x8))&0xC00)==0x400) group.long (0x8+0x0C)++0x03 line.long 0x00 "DMA1_CMAR1,DMA channel 1 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x8))&0xC00)==0x800) group.long (0x8+0x0C)++0x03 line.long 0x00 "DMA1_CMAR1,DMA channel 1 memory address register" endif else rgroup.long (0x8+0x04)++0x03 line.long 0x00 "DMA1_CNDTR1,DMA channel 1 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x8))&0x300)==0x100) rgroup.long (0x8+0x08)++0x03 line.long 0x00 "DMA1_CPAR1,DMA channel 1 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x8))&0x300)==0x200) rgroup.long (0x8+0x08)++0x03 line.long 0x00 "DMA1_CPAR1,DMA channel 1 peripheral address register" endif if (((per.l(ad:0x40020000+0x8))&0xC00)==0x400) rgroup.long (0x8+0x0C)++0x03 line.long 0x00 "DMA1_CMAR1,DMA channel 1 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x8))&0xC00)==0x800) rgroup.long (0x8+0x0C)++0x03 line.long 0x00 "DMA1_CMAR1,DMA channel 1 memory address register" endif endif group.long 0x1C++0x03 line.long 0x00 "DMA1_CCR2,DMA channel 2 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x1C))&0x01)==0x00) group.long (0x1C+0x04)++0x03 line.long 0x00 "DMA1_CNDTR2,DMA channel 2 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x1C))&0x300)==0x100) group.long (0x1C+0x08)++0x03 line.long 0x00 "DMA1_CPAR2,DMA channel 2 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x1C))&0x300)==0x200) group.long (0x1C+0x08)++0x03 line.long 0x00 "DMA1_CPAR2,DMA channel 2 peripheral address register" endif if (((per.l(ad:0x40020000+0x1C))&0xC00)==0x400) group.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR2,DMA channel 2 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x1C))&0xC00)==0x800) group.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR2,DMA channel 2 memory address register" endif else rgroup.long (0x1C+0x04)++0x03 line.long 0x00 "DMA1_CNDTR2,DMA channel 2 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x1C))&0x300)==0x100) rgroup.long (0x1C+0x08)++0x03 line.long 0x00 "DMA1_CPAR2,DMA channel 2 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x1C))&0x300)==0x200) rgroup.long (0x1C+0x08)++0x03 line.long 0x00 "DMA1_CPAR2,DMA channel 2 peripheral address register" endif if (((per.l(ad:0x40020000+0x1C))&0xC00)==0x400) rgroup.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR2,DMA channel 2 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x1C))&0xC00)==0x800) rgroup.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR2,DMA channel 2 memory address register" endif endif group.long 0x30++0x03 line.long 0x00 "DMA1_CCR3,DMA channel 3 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x30))&0x01)==0x00) group.long (0x30+0x04)++0x03 line.long 0x00 "DMA1_CNDTR3,DMA channel 3 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x30))&0x300)==0x100) group.long (0x30+0x08)++0x03 line.long 0x00 "DMA1_CPAR3,DMA channel 3 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x30))&0x300)==0x200) group.long (0x30+0x08)++0x03 line.long 0x00 "DMA1_CPAR3,DMA channel 3 peripheral address register" endif if (((per.l(ad:0x40020000+0x30))&0xC00)==0x400) group.long (0x30+0x0C)++0x03 line.long 0x00 "DMA1_CMAR3,DMA channel 3 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x30))&0xC00)==0x800) group.long (0x30+0x0C)++0x03 line.long 0x00 "DMA1_CMAR3,DMA channel 3 memory address register" endif else rgroup.long (0x30+0x04)++0x03 line.long 0x00 "DMA1_CNDTR3,DMA channel 3 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x30))&0x300)==0x100) rgroup.long (0x30+0x08)++0x03 line.long 0x00 "DMA1_CPAR3,DMA channel 3 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x30))&0x300)==0x200) rgroup.long (0x30+0x08)++0x03 line.long 0x00 "DMA1_CPAR3,DMA channel 3 peripheral address register" endif if (((per.l(ad:0x40020000+0x30))&0xC00)==0x400) rgroup.long (0x30+0x0C)++0x03 line.long 0x00 "DMA1_CMAR3,DMA channel 3 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x30))&0xC00)==0x800) rgroup.long (0x30+0x0C)++0x03 line.long 0x00 "DMA1_CMAR3,DMA channel 3 memory address register" endif endif group.long 0x44++0x03 line.long 0x00 "DMA1_CCR4,DMA channel 4 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x44))&0x01)==0x00) group.long (0x44+0x04)++0x03 line.long 0x00 "DMA1_CNDTR4,DMA channel 4 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x44))&0x300)==0x100) group.long (0x44+0x08)++0x03 line.long 0x00 "DMA1_CPAR4,DMA channel 4 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x44))&0x300)==0x200) group.long (0x44+0x08)++0x03 line.long 0x00 "DMA1_CPAR4,DMA channel 4 peripheral address register" endif if (((per.l(ad:0x40020000+0x44))&0xC00)==0x400) group.long (0x44+0x0C)++0x03 line.long 0x00 "DMA1_CMAR4,DMA channel 4 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x44))&0xC00)==0x800) group.long (0x44+0x0C)++0x03 line.long 0x00 "DMA1_CMAR4,DMA channel 4 memory address register" endif else rgroup.long (0x44+0x04)++0x03 line.long 0x00 "DMA1_CNDTR4,DMA channel 4 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x44))&0x300)==0x100) rgroup.long (0x44+0x08)++0x03 line.long 0x00 "DMA1_CPAR4,DMA channel 4 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x44))&0x300)==0x200) rgroup.long (0x44+0x08)++0x03 line.long 0x00 "DMA1_CPAR4,DMA channel 4 peripheral address register" endif if (((per.l(ad:0x40020000+0x44))&0xC00)==0x400) rgroup.long (0x44+0x0C)++0x03 line.long 0x00 "DMA1_CMAR4,DMA channel 4 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x44))&0xC00)==0x800) rgroup.long (0x44+0x0C)++0x03 line.long 0x00 "DMA1_CMAR4,DMA channel 4 memory address register" endif endif group.long 0x58++0x03 line.long 0x00 "DMA1_CCR5,DMA channel 5 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x58))&0x01)==0x00) group.long (0x58+0x04)++0x03 line.long 0x00 "DMA1_CNDTR5,DMA channel 5 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x58))&0x300)==0x100) group.long (0x58+0x08)++0x03 line.long 0x00 "DMA1_CPAR5,DMA channel 5 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x58))&0x300)==0x200) group.long (0x58+0x08)++0x03 line.long 0x00 "DMA1_CPAR5,DMA channel 5 peripheral address register" endif if (((per.l(ad:0x40020000+0x58))&0xC00)==0x400) group.long (0x58+0x0C)++0x03 line.long 0x00 "DMA1_CMAR5,DMA channel 5 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x58))&0xC00)==0x800) group.long (0x58+0x0C)++0x03 line.long 0x00 "DMA1_CMAR5,DMA channel 5 memory address register" endif else rgroup.long (0x58+0x04)++0x03 line.long 0x00 "DMA1_CNDTR5,DMA channel 5 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x58))&0x300)==0x100) rgroup.long (0x58+0x08)++0x03 line.long 0x00 "DMA1_CPAR5,DMA channel 5 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x58))&0x300)==0x200) rgroup.long (0x58+0x08)++0x03 line.long 0x00 "DMA1_CPAR5,DMA channel 5 peripheral address register" endif if (((per.l(ad:0x40020000+0x58))&0xC00)==0x400) rgroup.long (0x58+0x0C)++0x03 line.long 0x00 "DMA1_CMAR5,DMA channel 5 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x58))&0xC00)==0x800) rgroup.long (0x58+0x0C)++0x03 line.long 0x00 "DMA1_CMAR5,DMA channel 5 memory address register" endif endif group.long 0x6C++0x03 line.long 0x00 "DMA1_CCR6,DMA channel 6 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x6C))&0x01)==0x00) group.long (0x6C+0x04)++0x03 line.long 0x00 "DMA1_CNDTR6,DMA channel 6 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x6C))&0x300)==0x100) group.long (0x6C+0x08)++0x03 line.long 0x00 "DMA1_CPAR6,DMA channel 6 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x6C))&0x300)==0x200) group.long (0x6C+0x08)++0x03 line.long 0x00 "DMA1_CPAR6,DMA channel 6 peripheral address register" endif if (((per.l(ad:0x40020000+0x6C))&0xC00)==0x400) group.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR6,DMA channel 6 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x6C))&0xC00)==0x800) group.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR6,DMA channel 6 memory address register" endif else rgroup.long (0x6C+0x04)++0x03 line.long 0x00 "DMA1_CNDTR6,DMA channel 6 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x6C))&0x300)==0x100) rgroup.long (0x6C+0x08)++0x03 line.long 0x00 "DMA1_CPAR6,DMA channel 6 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x6C))&0x300)==0x200) rgroup.long (0x6C+0x08)++0x03 line.long 0x00 "DMA1_CPAR6,DMA channel 6 peripheral address register" endif if (((per.l(ad:0x40020000+0x6C))&0xC00)==0x400) rgroup.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR6,DMA channel 6 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x6C))&0xC00)==0x800) rgroup.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA1_CMAR6,DMA channel 6 memory address register" endif endif group.long 0x80++0x03 line.long 0x00 "DMA1_CCR7,DMA channel 7 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020000+0x80))&0x01)==0x00) group.long (0x80+0x04)++0x03 line.long 0x00 "DMA1_CNDTR7,DMA channel 7 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x80))&0x300)==0x100) group.long (0x80+0x08)++0x03 line.long 0x00 "DMA1_CPAR7,DMA channel 7 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x80))&0x300)==0x200) group.long (0x80+0x08)++0x03 line.long 0x00 "DMA1_CPAR7,DMA channel 7 peripheral address register" endif if (((per.l(ad:0x40020000+0x80))&0xC00)==0x400) group.long (0x80+0x0C)++0x03 line.long 0x00 "DMA1_CMAR7,DMA channel 7 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x80))&0xC00)==0x800) group.long (0x80+0x0C)++0x03 line.long 0x00 "DMA1_CMAR7,DMA channel 7 memory address register" endif else rgroup.long (0x80+0x04)++0x03 line.long 0x00 "DMA1_CNDTR7,DMA channel 7 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020000+0x80))&0x300)==0x100) rgroup.long (0x80+0x08)++0x03 line.long 0x00 "DMA1_CPAR7,DMA channel 7 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020000+0x80))&0x300)==0x200) rgroup.long (0x80+0x08)++0x03 line.long 0x00 "DMA1_CPAR7,DMA channel 7 peripheral address register" endif if (((per.l(ad:0x40020000+0x80))&0xC00)==0x400) rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DMA1_CMAR7,DMA channel 7 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020000+0x80))&0xC00)==0x800) rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DMA1_CMAR7,DMA channel 7 memory address register" endif endif sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0xA8++0x03 line.long 0x00 "DMA1_CSELR,DMA1 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",,USART2_TX,I2C1_RX,TIM2_CH2/4,,,TIM1_CH3,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",,USART2_RX,I2C1_TX,TIM16_CH1/UP,TIM3_CH1/TRIG,,TIM1_UP,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" ",SPI2_TX,USART1_RX,I2C2_RX,TIM2_CH1,QUADSPI,,TIM15_CH1/UP/TRIG/COM,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" ",SPI2_RX,USART1_TX,I2C2_TX,,,,TIM1_CH4/TRIG/COM,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" ",SPI1_TX,USART3_RX,I2C3_RX,TIM16_CH1/UP,TIM3_CH4/UP,TIM6_UP/DAC1,TIM1_CH2,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SPI1_RX,USART3_TX,I2C3_TX,TIM2_UP,TIM3_CH3,,TIM1_CH1,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC1,,,,TIM2_CH3,?..." elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L4?2*")) group.long 0xA8++0x03 line.long 0x00 "DMA1_CSELR,DMA1 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",,USART2_TX,I2C1_RX,TIM2_CH2/4,,,TIM1_CH3,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",,USART2_RX,I2C1_TX,TIM16_CH1/UP,,,TIM1_UP,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" ",SPI2_TX,USART1_RX,I2C2_RX,TIM2_CH1,QUADSPI,,TIM15_CH1/UP/TRIG/COM,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" ",SPI2_RX,USART1_TX,I2C2_TX,,TIM7_UP/DAC2,,TIM1_CH4/TRIG/COM,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" ",SPI1_TX,USART3_RX,I2C3_RX,TIM16_CH1/UP,,TIM6_UP/DAC1,TIM1_CH2,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SPI1_RX,USART3_TX,I2C3_TX,TIM2_UP,,,TIM1_CH1,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC1,,,,TIM2_CH3,?..." elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) group.long 0xA8++0x03 line.long 0x00 "DMA1_CSELR,DMA1 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" "DFSDM1_FLT3,SAI2_B,USART2_TX,I2C1_RX,TIM2_CH2/TIM2_CH4,TIM17_CH1/TIM17_UP,TIM4_UP,TIM1_CH3,?..." bitfld.long 0x00 20.--23. "C6S ,DMA channel 6 selection" "DFSDM1_FLT2,SAI2_A,USART2_RX,I2C1_TX,TIM16_CH1/TIM16_UP,TIM3_CH1/TIM3_TRIG,,TIM1_UP,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "DFSDM1_FLT1,SPI2_TX,USART1_RX,I2C2_RX,TIM2_CH1,QUADSPI,TIM4_CH3,TIM15_CH1/TIM15_UP/TIM15_TRIG/TIM15_COM,?..." textline " " bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" "DFSDM1_FLT0,SPI2_RX,USART1_TX,I2C2_TX,,TIM7_UP/DAC2,TIM4_CH2,TIM1_CH4/TIM1_TRIG/TIM1_COM,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC3,SPI1_TX,USART3_RX,I2C3_RX,TIM16_CH1/TIM16_UP,TIM3_CH4/TIM3_UP,TIM6_UP/DAC1,TIM1_CH2,?..." bitfld.long 0x00 4.--7. "C2S ,DMA channel 2 selection" "ADC2,SPI1_RX,USART3_TX,I2C3_TX,TIM2_UP,TIM3_CH3,,TIM1_CH1,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC1,,,,TIM2_CH3,TIM17_CH1/TIM17_UP,TIM4_CH1,?..." elif (cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long 0xA8++0x03 line.long 0x00 "DMA1_CSELR,DMA1 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" "DFSDM1_FLT3,SAI2_B,USART2_TX,I2C1_RX,TIM2_CH2/TIM2_CH4,TIM17_CH1/TIM1_UP,TIM4_UP,TIM1_CH3,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" "DFSDM1_FLT2,SAI2_A,USART2_RX,I2C1_TX,TIM16_CH1/TIM16_UP,TIM3_CH1/TIM3_TRIG,,TIM1_UP,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "DFSDM1_FLT1,SPI2_TX,USART1_RX,I2C2_RX,TIM2_CH1,QUADSPI,TIM4_CH3,TIM15_CH1/TIM15_UP/TIM15_TRIG/TIM15_COM,?..." textline " " bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" "DFSDM1_FLT0,SPI2_RX,USART1_TX,I2C2_TX,,TIM7_UP/DAC2,TIM4_CH2,TIM1_CH4/TIM1_TRIG/TIM1_COM,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC3,SPI1_TX,USART3_RX,I2C3_RX,TIM16_CH1/TIM16_UP,TIM3_CH4/TIM3_UP,TIM6_UP/DAC1,TIM1_CH2,?..." bitfld.long 0x00 4.--7. "C2S ,DMA channel 2 selection" "ADC2,SPI1_RX,USART3_TX,I2C3_TX,TIM2_UP,TIM3_CH3,,TIM1_CH1,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC1,,,,TIM2_CH3,TIM17_CH1/TIM17_UP,TIM4_CH1,?..." else group.long 0xA8++0x03 line.long 0x00 "DMA1_CSELR,DMA1 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" "DFSDM4,SAI2_B,USART2_TX,I2C1_RX,TIM2_CH2/4,TIM17_CH1/UP,TIM4_UP,TIM1_CH3,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" "DFSDM3,SAI2_A,USART2_RX,I2C1_TX,TIM16_CH1/UP,TIM3_CH1/TRIG,,TIM1_UP,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "DFSDM2,SPI2_TX,USART1_RX,I2C2_RX,TIM2_CH1,QUADSPI,TIM4_CH3,TIM15_CH1/UP/TRIG/COM,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" "DFSDM1,SPI2_RX,USART1_TX,I2C2_TX,,TIM7_UP/DAC2,TIM4_CH2,TIM1_CH4/TRIG/COM,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC3,SPI1_TX,USART3_RX,I2C3_RX,TIM16_CH1/UP,TIM3_CH4/TIM3_UP,TIM6_UP/DAC1,TIM1_CH2,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" "ADC2,SPI1_RX,USART3_TX,I2C3_TX,TIM2_UP,TIM3_CH3,,TIM1_CH1,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC1,,,,TIM2_CH3,TIM17_CH1/UP,TIM4_CH1,?..." endif width 0x0B tree.end tree "DMA2" base ad:0x40020400 width 13. rgroup.long 0x00++0x03 line.long 0x00 "DMA2_ISR,DMA interrupt status register" bitfld.long 0x00 27. " TEIF7 ,Channel 7 transfer error flag" "No error,Error" bitfld.long 0x00 26. " HTIF7 ,Channel 7 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 25. " TCIF7 ,Channel 7 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 24. " GIF7 ,Channel 7 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 23. " TEIF6 ,Channel 6 transfer error flag" "No error,Error" bitfld.long 0x00 22. " HTIF6 ,Channel 6 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 21. " TCIF6 ,Channel 6 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 20. " GIF6 ,Channel 6 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 19. " TEIF5 ,Channel 5 transfer error flag" "No error,Error" bitfld.long 0x00 18. " HTIF5 ,Channel 5 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 17. " TCIF5 ,Channel 5 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 16. " GIF5 ,Channel 5 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 15. " TEIF4 ,Channel 4 transfer error flag" "No error,Error" bitfld.long 0x00 14. " HTIF4 ,Channel 4 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 13. " TCIF4 ,Channel 4 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 12. " GIF4 ,Channel 4 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 11. " TEIF3 ,Channel 3 transfer error flag" "No error,Error" bitfld.long 0x00 10. " HTIF3 ,Channel 3 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 9. " TCIF3 ,Channel 3 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 8. " GIF3 ,Channel 3 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 7. " TEIF2 ,Channel 2 transfer error flag" "No error,Error" bitfld.long 0x00 6. " HTIF2 ,Channel 2 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 5. " TCIF2 ,Channel 2 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 4. " GIF2 ,Channel 2 global interrupt flag" "No TE/HT/TC,TE/HT/TC" textline " " bitfld.long 0x00 3. " TEIF1 ,Channel 1 transfer error flag" "No error,Error" bitfld.long 0x00 2. " HTIF1 ,Channel 1 half transfer flag" "No htransfer,Htransfer" bitfld.long 0x00 1. " TCIF1 ,Channel 1 transfer complete flag" "No transfer,Transfer" bitfld.long 0x00 0. " GIF1 ,Channel 1 global interrupt flag" "No TE/HT/TC,TE/HT/TC" wgroup.long 0x04++0x03 line.long 0x00 "DMA2_IFCR,DMA interrupt flag clear register" bitfld.long 0x00 27. " CTEIF7 ,Channel 7 transfer error clear" "No effect,Clear" bitfld.long 0x00 26. " CHTIF7 ,Channel 7 half transfer clear" "No effect,Clear" bitfld.long 0x00 25. " CTCIF7 ,Channel 7 transfer complete clear" "No effect,Clear" bitfld.long 0x00 24. " CGIF7 ,Channel 7 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 23. " CTEIF6 ,Channel 6 transfer error clear" "No effect,Clear" bitfld.long 0x00 22. " CHTIF6 ,Channel 6 half transfer clear" "No effect,Clear" bitfld.long 0x00 21. " CTCIF6 ,Channel 6 transfer complete clear" "No effect,Clear" bitfld.long 0x00 20. " CGIF6 ,Channel 6 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 19. " CTEIF5 ,Channel 5 transfer error clear" "No effect,Clear" bitfld.long 0x00 18. " CHTIF5 ,Channel 5 half transfer clear" "No effect,Clear" bitfld.long 0x00 17. " CTCIF5 ,Channel 5 transfer complete clear" "No effect,Clear" bitfld.long 0x00 16. " CGIF5 ,Channel 5 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 15. " CTEIF4 ,Channel 4 transfer error clear" "No effect,Clear" bitfld.long 0x00 14. " CHTIF4 ,Channel 4 half transfer clear" "No effect,Clear" bitfld.long 0x00 13. " CTCIF4 ,Channel 4 transfer complete clear" "No effect,Clear" bitfld.long 0x00 12. " CGIF4 ,Channel 4 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 11. " CTEIF3 ,Channel 3 transfer error clear" "No effect,Clear" bitfld.long 0x00 10. " CHTIF3 ,Channel 3 half transfer clear" "No effect,Clear" bitfld.long 0x00 9. " CTCIF3 ,Channel 3 transfer complete clear" "No effect,Clear" bitfld.long 0x00 8. " CGIF3 ,Channel 3 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 7. " CTEIF2 ,Channel 2 transfer error clear" "No effect,Clear" bitfld.long 0x00 6. " CHTIF2 ,Channel 2 half transfer clear" "No effect,Clear" bitfld.long 0x00 5. " CTCIF2 ,Channel 2 transfer complete clear" "No effect,Clear" bitfld.long 0x00 4. " CGIF2 ,Channel 2 global interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " CTEIF1 ,Channel 1 transfer error clear" "No effect,Clear" bitfld.long 0x00 2. " CHTIF1 ,Channel 1 half transfer clear" "No effect,Clear" bitfld.long 0x00 1. " CTCIF1 ,Channel 1 transfer complete clear" "No effect,Clear" bitfld.long 0x00 0. " CGIF1 ,Channel 1 global interrupt clear" "No effect,Clear" group.long 0x8++0x03 line.long 0x00 "DMA2_CCR1,DMA channel 1 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x8))&0x01)==0x00) group.long (0x8+0x04)++0x03 line.long 0x00 "DMA2_CNDTR1,DMA channel 1 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x8))&0x300)==0x100) group.long (0x8+0x08)++0x03 line.long 0x00 "DMA2_CPAR1,DMA channel 1 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x8))&0x300)==0x200) group.long (0x8+0x08)++0x03 line.long 0x00 "DMA2_CPAR1,DMA channel 1 peripheral address register" endif if (((per.l(ad:0x40020400+0x8))&0xC00)==0x400) group.long (0x8+0x0C)++0x03 line.long 0x00 "DMA2_CMAR1,DMA channel 1 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x8))&0xC00)==0x800) group.long (0x8+0x0C)++0x03 line.long 0x00 "DMA2_CMAR1,DMA channel 1 memory address register" endif else rgroup.long (0x8+0x04)++0x03 line.long 0x00 "DMA2_CNDTR1,DMA channel 1 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x8))&0x300)==0x100) rgroup.long (0x8+0x08)++0x03 line.long 0x00 "DMA2_CPAR1,DMA channel 1 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x8))&0x300)==0x200) rgroup.long (0x8+0x08)++0x03 line.long 0x00 "DMA2_CPAR1,DMA channel 1 peripheral address register" endif if (((per.l(ad:0x40020400+0x8))&0xC00)==0x400) rgroup.long (0x8+0x0C)++0x03 line.long 0x00 "DMA2_CMAR1,DMA channel 1 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x8))&0xC00)==0x800) rgroup.long (0x8+0x0C)++0x03 line.long 0x00 "DMA2_CMAR1,DMA channel 1 memory address register" endif endif group.long 0x1C++0x03 line.long 0x00 "DMA2_CCR2,DMA channel 2 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x1C))&0x01)==0x00) group.long (0x1C+0x04)++0x03 line.long 0x00 "DMA2_CNDTR2,DMA channel 2 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x1C))&0x300)==0x100) group.long (0x1C+0x08)++0x03 line.long 0x00 "DMA2_CPAR2,DMA channel 2 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x1C))&0x300)==0x200) group.long (0x1C+0x08)++0x03 line.long 0x00 "DMA2_CPAR2,DMA channel 2 peripheral address register" endif if (((per.l(ad:0x40020400+0x1C))&0xC00)==0x400) group.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR2,DMA channel 2 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x1C))&0xC00)==0x800) group.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR2,DMA channel 2 memory address register" endif else rgroup.long (0x1C+0x04)++0x03 line.long 0x00 "DMA2_CNDTR2,DMA channel 2 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x1C))&0x300)==0x100) rgroup.long (0x1C+0x08)++0x03 line.long 0x00 "DMA2_CPAR2,DMA channel 2 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x1C))&0x300)==0x200) rgroup.long (0x1C+0x08)++0x03 line.long 0x00 "DMA2_CPAR2,DMA channel 2 peripheral address register" endif if (((per.l(ad:0x40020400+0x1C))&0xC00)==0x400) rgroup.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR2,DMA channel 2 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x1C))&0xC00)==0x800) rgroup.long (0x1C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR2,DMA channel 2 memory address register" endif endif group.long 0x30++0x03 line.long 0x00 "DMA2_CCR3,DMA channel 3 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x30))&0x01)==0x00) group.long (0x30+0x04)++0x03 line.long 0x00 "DMA2_CNDTR3,DMA channel 3 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x30))&0x300)==0x100) group.long (0x30+0x08)++0x03 line.long 0x00 "DMA2_CPAR3,DMA channel 3 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x30))&0x300)==0x200) group.long (0x30+0x08)++0x03 line.long 0x00 "DMA2_CPAR3,DMA channel 3 peripheral address register" endif if (((per.l(ad:0x40020400+0x30))&0xC00)==0x400) group.long (0x30+0x0C)++0x03 line.long 0x00 "DMA2_CMAR3,DMA channel 3 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x30))&0xC00)==0x800) group.long (0x30+0x0C)++0x03 line.long 0x00 "DMA2_CMAR3,DMA channel 3 memory address register" endif else rgroup.long (0x30+0x04)++0x03 line.long 0x00 "DMA2_CNDTR3,DMA channel 3 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x30))&0x300)==0x100) rgroup.long (0x30+0x08)++0x03 line.long 0x00 "DMA2_CPAR3,DMA channel 3 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x30))&0x300)==0x200) rgroup.long (0x30+0x08)++0x03 line.long 0x00 "DMA2_CPAR3,DMA channel 3 peripheral address register" endif if (((per.l(ad:0x40020400+0x30))&0xC00)==0x400) rgroup.long (0x30+0x0C)++0x03 line.long 0x00 "DMA2_CMAR3,DMA channel 3 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x30))&0xC00)==0x800) rgroup.long (0x30+0x0C)++0x03 line.long 0x00 "DMA2_CMAR3,DMA channel 3 memory address register" endif endif group.long 0x44++0x03 line.long 0x00 "DMA2_CCR4,DMA channel 4 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x44))&0x01)==0x00) group.long (0x44+0x04)++0x03 line.long 0x00 "DMA2_CNDTR4,DMA channel 4 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x44))&0x300)==0x100) group.long (0x44+0x08)++0x03 line.long 0x00 "DMA2_CPAR4,DMA channel 4 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x44))&0x300)==0x200) group.long (0x44+0x08)++0x03 line.long 0x00 "DMA2_CPAR4,DMA channel 4 peripheral address register" endif if (((per.l(ad:0x40020400+0x44))&0xC00)==0x400) group.long (0x44+0x0C)++0x03 line.long 0x00 "DMA2_CMAR4,DMA channel 4 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x44))&0xC00)==0x800) group.long (0x44+0x0C)++0x03 line.long 0x00 "DMA2_CMAR4,DMA channel 4 memory address register" endif else rgroup.long (0x44+0x04)++0x03 line.long 0x00 "DMA2_CNDTR4,DMA channel 4 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x44))&0x300)==0x100) rgroup.long (0x44+0x08)++0x03 line.long 0x00 "DMA2_CPAR4,DMA channel 4 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x44))&0x300)==0x200) rgroup.long (0x44+0x08)++0x03 line.long 0x00 "DMA2_CPAR4,DMA channel 4 peripheral address register" endif if (((per.l(ad:0x40020400+0x44))&0xC00)==0x400) rgroup.long (0x44+0x0C)++0x03 line.long 0x00 "DMA2_CMAR4,DMA channel 4 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x44))&0xC00)==0x800) rgroup.long (0x44+0x0C)++0x03 line.long 0x00 "DMA2_CMAR4,DMA channel 4 memory address register" endif endif group.long 0x58++0x03 line.long 0x00 "DMA2_CCR5,DMA channel 5 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x58))&0x01)==0x00) group.long (0x58+0x04)++0x03 line.long 0x00 "DMA2_CNDTR5,DMA channel 5 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x58))&0x300)==0x100) group.long (0x58+0x08)++0x03 line.long 0x00 "DMA2_CPAR5,DMA channel 5 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x58))&0x300)==0x200) group.long (0x58+0x08)++0x03 line.long 0x00 "DMA2_CPAR5,DMA channel 5 peripheral address register" endif if (((per.l(ad:0x40020400+0x58))&0xC00)==0x400) group.long (0x58+0x0C)++0x03 line.long 0x00 "DMA2_CMAR5,DMA channel 5 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x58))&0xC00)==0x800) group.long (0x58+0x0C)++0x03 line.long 0x00 "DMA2_CMAR5,DMA channel 5 memory address register" endif else rgroup.long (0x58+0x04)++0x03 line.long 0x00 "DMA2_CNDTR5,DMA channel 5 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x58))&0x300)==0x100) rgroup.long (0x58+0x08)++0x03 line.long 0x00 "DMA2_CPAR5,DMA channel 5 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x58))&0x300)==0x200) rgroup.long (0x58+0x08)++0x03 line.long 0x00 "DMA2_CPAR5,DMA channel 5 peripheral address register" endif if (((per.l(ad:0x40020400+0x58))&0xC00)==0x400) rgroup.long (0x58+0x0C)++0x03 line.long 0x00 "DMA2_CMAR5,DMA channel 5 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x58))&0xC00)==0x800) rgroup.long (0x58+0x0C)++0x03 line.long 0x00 "DMA2_CMAR5,DMA channel 5 memory address register" endif endif group.long 0x6C++0x03 line.long 0x00 "DMA2_CCR6,DMA channel 6 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x6C))&0x01)==0x00) group.long (0x6C+0x04)++0x03 line.long 0x00 "DMA2_CNDTR6,DMA channel 6 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x6C))&0x300)==0x100) group.long (0x6C+0x08)++0x03 line.long 0x00 "DMA2_CPAR6,DMA channel 6 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x6C))&0x300)==0x200) group.long (0x6C+0x08)++0x03 line.long 0x00 "DMA2_CPAR6,DMA channel 6 peripheral address register" endif if (((per.l(ad:0x40020400+0x6C))&0xC00)==0x400) group.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR6,DMA channel 6 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x6C))&0xC00)==0x800) group.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR6,DMA channel 6 memory address register" endif else rgroup.long (0x6C+0x04)++0x03 line.long 0x00 "DMA2_CNDTR6,DMA channel 6 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x6C))&0x300)==0x100) rgroup.long (0x6C+0x08)++0x03 line.long 0x00 "DMA2_CPAR6,DMA channel 6 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x6C))&0x300)==0x200) rgroup.long (0x6C+0x08)++0x03 line.long 0x00 "DMA2_CPAR6,DMA channel 6 peripheral address register" endif if (((per.l(ad:0x40020400+0x6C))&0xC00)==0x400) rgroup.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR6,DMA channel 6 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x6C))&0xC00)==0x800) rgroup.long (0x6C+0x0C)++0x03 line.long 0x00 "DMA2_CMAR6,DMA channel 6 memory address register" endif endif group.long 0x80++0x03 line.long 0x00 "DMA2_CCR7,DMA channel 7 configuration register" bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled" bitfld.long 0x00 12.--13. " PL ,Channel priority level" "Low,Medium,High,VeryHigh" bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8b,16b,32b,?..." bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8b,16b,32b,?..." textline " " bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled" bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled" bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled" bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory" textline " " bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " HTIE ,Half transfer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled" if (((per.l(ad:0x40020400+0x80))&0x01)==0x00) group.long (0x80+0x04)++0x03 line.long 0x00 "DMA2_CNDTR7,DMA channel 7 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x80))&0x300)==0x100) group.long (0x80+0x08)++0x03 line.long 0x00 "DMA2_CPAR7,DMA channel 7 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x80))&0x300)==0x200) group.long (0x80+0x08)++0x03 line.long 0x00 "DMA2_CPAR7,DMA channel 7 peripheral address register" endif if (((per.l(ad:0x40020400+0x80))&0xC00)==0x400) group.long (0x80+0x0C)++0x03 line.long 0x00 "DMA2_CMAR7,DMA channel 7 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x80))&0xC00)==0x800) group.long (0x80+0x0C)++0x03 line.long 0x00 "DMA2_CMAR7,DMA channel 7 memory address register" endif else rgroup.long (0x80+0x04)++0x03 line.long 0x00 "DMA2_CNDTR7,DMA channel 7 number of data register" hexmask.long.word 0x00 0.--15. 1. " NDT ,Number of data to transfer" if (((per.l(ad:0x40020400+0x80))&0x300)==0x100) rgroup.long (0x80+0x08)++0x03 line.long 0x00 "DMA2_CPAR7,DMA channel 7 peripheral address register" hexmask.long.word 0x00 0.--15. 1. " PA ,Peripheral address" elif (((per.l(ad:0x40020400+0x80))&0x300)==0x200) rgroup.long (0x80+0x08)++0x03 line.long 0x00 "DMA2_CPAR7,DMA channel 7 peripheral address register" endif if (((per.l(ad:0x40020400+0x80))&0xC00)==0x400) rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DMA2_CMAR7,DMA channel 7 memory address register" hexmask.long.word 0x00 0.--15. 1. " MA ,Memory address" elif (((per.l(ad:0x40020400+0x80))&0xC00)==0x800) rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DMA2_CMAR7,DMA channel 7 memory address register" endif endif sif (cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0xA8++0x03 line.long 0x00 "DMA2_CSELR,DMA2 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",,USART2_TX,I2C1_RX,TIM2_CH2/CH4,,,TIM1_CH3,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",,USART2_RX,I2C1_TX,TIM16_CH1/UP,TIM3_CH1/TRIG,,TIM1_UP,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" ",SPI2_TX,USART1_RX,I2C2_RX,TIM2_CH1,QUADSPI,,TIM15_CH1/UP/TRIG/COM,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" ",SPI2_RX,USART1_TX,I2C2_TX,,,,TIM1_CH4/TRIG/COM,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" ",SPI1_TX,USART3_RX,I2C3_RX,TIM16_CH1/UP,TIM3_CH4/UP,TIM6_UP/DAC1,TIM1_CH2,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SPI1_RX,USART3_TX,I2C3_TX,TIM2_UP,TIM3_CH3,,TIM1_CH1,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC1,,,,TIM2_CH3,?..." elif (cpuis("STM32L43*"))||(cpuis("STM32L431*")) group.long 0xA8++0x03 line.long 0x00 "DMA2_CSELR,DMA2 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",SAI1_B,USART1_RX,QUADSPI,LPUART_RX,I2C1_TX,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",SAI1_A,USART1_TX,,LPUART_TX,I2C1_RX,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" ",,,TIM7_UP/DAC2,,,,SDMMC1,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" ",,,TIM6_UP/DAC1,SPI1_TX,,,SDMMC1,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC1,,,,SPI1_RX,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SAI1_B,,SPI3_TX,SWPMI1_TX,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" ",SAI1_A,,SPI3_RX,SWPMI1_RX,?..." elif (cpuis("STM32L44*")) group.long 0xA8++0x03 line.long 0x00 "DMA2_CSELR,DMA2 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",SAI1_B,USART1_RX,QUADSPI,LPUART_RX,I2C1_TX,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",SAI1_A,USART1_TX,,LPUART_TX,I2C1_RX,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" ",,,TIM7_UP/DAC2,,,AES_IN,SDMMC1,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" ",,,TIM6_UP/DAC1,SPI1_TX,,,SDMMC1,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC1,,,,SPI1_RX,,AES_OUT,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SAI1_B,,SPI3_TX,SWPMI1_TX,,AES_OUT,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" ",SAI1_A,,SPI3_RX,SWPMI1_RX,,AES_IN,?..." elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) group.long 0xA8++0x03 line.long 0x00 "DMA2_CSELR,DMA2 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",SAI1_B,USART1_RX,QUADSPI,LPUART_RX,I2C1_TX,HASH_IN,TIM8_CH2,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" "DCMI,SAI1_A,USART1_TX,,LPUART_TX,I2C1_RX,,TIM8_CH1,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "ADC3,,UART4_RX,TIM7_UP/DAC2,DCMI,TIM5_CH1,AES_IN,SDMMC1,?..." textline " " bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" "ADC2,SAI2_B,,TIM6_UP/DAC1,SPI1_TX,TIM5_CH2,,SDMMC1,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC1,SAI2_A,UART4_TX,,SPI1_RX,,AES_OUT,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" "I2C4_TX,SAI1_B,UART5_RX,SPI3_TX,SWPMI1_TX,TIM5_CH3/TIM5_UP,AES_OUT,TIM8_CH4/TIM8_TRIG/TIM8_COM,?..." textline " " bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "I2C4_RX,SAI1_A,UART5_TX,SPI3_RX,SWPMI1_RX,TIM5_CH4/TIM5_TRIG,AES_IN,TIM8_CH3/TIM8_UP,?..." elif (cpuis("STM32L471*")) group.long 0xA8++0x03 line.long 0x00 "DMA2_CSELR,DMA2 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",SAI1_B,USART1_RX,QUADSPI,LPUART_RX,I2C1_TX,,TIM8_CH2,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",SAI1_A,USART1_TX,,LPUART_TX,I2C1_RX,,TIM8_CH1,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "ADC3,,UART4_RX,TIM7_UP/DAC2,,TIM5_CH1,,SDMMC1,?..." textline " " bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" "ADC2,SAI2_B,,TIM6_UP/DAC1,SPI1_TX,TIM5_CH2,,SDMMC1,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC1,SAI2_A,UART4_TX,,SPI1_RX,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SAI1_B,UART5_RX,SPI3_TX,SWPMI1_TX,TIM5_CH3/TIM5_UP,,TIM8_CH4/TIM8_TRIG/TIM8_COM,?..." textline " " bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" ",SAI1_A,UART5_TX,SPI3_RX,SWPMI1_RX,TIM5_CH4/TIM5_TRIG,,TIM8_CH3/TIM8_UP,?..." else group.long 0xA8++0x03 line.long 0x00 "DMA2_CSELR,DMA2 channel selection register" bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" ",SAI1_B,USART1_RX,QUADSPI,LPUART_RX,I2C1_TX,,TIM8_CH2,?..." bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" ",SAI1_A,USART1_TX,,LPUART_TX,I2C1_RX,,TIM8_CH1,?..." bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "ADC3,,UART4_RX,TIM7_UP/DAC2,,TIM5_CH1,AES_IN,SDMMC,?..." bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" "ADC2,SAI2_B,,TIM6_UP/DAC1,,SPI1_TX,TIM5_CH2,,SDMMC,?..." textline " " bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "ADC1,SAI2_A,UART4_TX,,SPI1_RX,,AES_OUT,?..." bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",SAI1_B,UART5_RX,SPI3_TX,SWPMI1_TX,TIM5_CH3/UP,AES_OUT,TIM8_CH4/TRIG/COM,?..." bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" ",SAI1_A,UART5_TX,SPI3_RX,SWPMI1_RX,TIM5_CH4/TRIG/COM,AES_IN,TIM8_CH3/UP,?..." endif width 0x0B tree.end tree.end sif (!cpuis("STM32L462*")&&!cpuis("STM32L452*")&&!cpuis("STM32L451*")) tree "DMA2D (Chrom-Art Accelerator controller)" base ad:0x4002B000 width 11. if (((per.l(ad:0x4002B000))&0x07)==(0x01)) group.long 0x00++0x03 line.long 0x00 "CR,DMA2D Control Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") rbitfld.long 0x00 16.--18. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory,Memory-to-memory,Memory-to-memory,?..." else rbitfld.long 0x00 16.--17. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory" endif newline bitfld.long 0x00 13. " CEIE ,Configuration error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " CTCIE ,CLUT transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CAEIE ,CLUT access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " TWIE ,Transfer watermark interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" newline sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") rbitfld.long 0x00 6. " LOM ,Line offset mode" "Expressed in pixels,Expressed in bytes" newline endif bitfld.long 0x00 2. " ABORT ,Abort" "Not requested,Requested" bitfld.long 0x00 1. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 0. " START ,Start" "Not started,Started" else group.long 0x00++0x03 line.long 0x00 "CR,DMA2D Control Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x00 16.--18. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory,Memory-to-memory,Memory-to-memory,?..." else bitfld.long 0x00 16.--17. " MODE ,DMA2D mode" "Memory-to-memory,Memory-to-memory with PFC,Memory-to-memory with blending,Register-to-memory" endif newline bitfld.long 0x00 13. " CEIE ,Configuration error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " CTCIE ,CLUT transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CAEIE ,CLUT access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " TWIE ,Transfer watermark interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" newline sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x00 6. " LOM ,Line offset mode" "Expressed in pixels,Expressed in bytes" newline endif bitfld.long 0x00 2. " ABORT ,Abort" "Not requested,Requested" bitfld.long 0x00 1. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 0. " START ,Start" "Not started,Started" endif rgroup.long 0x04++0x03 line.long 0x00 "ISR,DMA2D Interrupt Status Register" bitfld.long 0x00 5. " CEIF ,Configuration error interrupt flag" "No error,Error" bitfld.long 0x00 4. " CTCIF ,CLUT transfer complete interrupt flag" "Not completed,Completed" bitfld.long 0x00 3. " CAEIF ,CLUT access error interrupt flag" "No error,Error" bitfld.long 0x00 2. " TWIF ,Transfer watermark interrupt flag" "Not transferred,Transferred" newline bitfld.long 0x00 1. " TCIF ,Transfer complete interrupt flag" "Not completed,Completed" bitfld.long 0x00 0. " TEIF ,Transfer error interrupt flag" "No error,Error" group.long 0x08++0x03 line.long 0x00 "IFCR,DMA2D Interrupt Flag Clear Register" eventfld.long 0x00 5. " CCEIF ,Clear configuration error interrupt flag" "No effect,Clear" eventfld.long 0x00 4. " CCTCIF ,Clear CLUT transfer complete interrupt flag" "No effect,Clear" eventfld.long 0x00 3. " CAECIF ,Clear CLUT access error interrupt flag" "No effect,Clear" eventfld.long 0x00 2. " CTWIF ,Clear transfer watermark interrupt flag" "No effect,Clear" newline eventfld.long 0x00 1. " CTCIF ,Clear transfer complete interrupt flag" "No effect,Clear" eventfld.long 0x00 0. " CTEIF ,Clear transfer error interrupt flag" "No effect,Clear" if (((per.l(ad:0x4002B000))&0x07)==(0x01)) rgroup.long 0x0C++0x13 line.long 0x00 "FGMAR,DMA2D Foreground Memory Address Register" line.long 0x04 "FGOR,DMA2D Foreground Offset Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") hexmask.long.word 0x04 0.--15. 0x01 " LO ,Line offset" else hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset" endif line.long 0x08 "BGMAR,DMA2D Background Memory Address Register" line.long 0x0C "BGOR,DMA2D Background Offset Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") hexmask.long.word 0x0C 0.--15. 0x01 " LO ,Line offset" else hexmask.long.word 0x0C 0.--13. 0x01 " LO ,Line offset" endif line.long 0x10 "FGPFCCR,DMA2D Foreground PFC Control Register" hexmask.long.byte 0x10 24.--31. 1. " ALPHA ,Alpha value" newline sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted" bitfld.long 0x10 18.--19. " CSS ,Chroma sub-sampling" "4:4:4,4:2:2,4:2:0,?..." newline elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*") bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted" newline endif bitfld.long 0x10 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..." hexmask.long.byte 0x10 8.--15. 0x01 " CS ,CLUT size" bitfld.long 0x10 5. " START ,Start" "Not started,Started" bitfld.long 0x10 4. " CCM ,CLUT color mode" "ARGB8888,RGB888" newline bitfld.long 0x10 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,YCbCr,?..." else group.long 0x0C++0x13 line.long 0x00 "FGMAR,DMA2D Foreground Memory Address Register" line.long 0x04 "FGOR,DMA2D Foreground Offset Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") hexmask.long.word 0x04 0.--15. 0x01 " LO ,Line offset" else hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset" endif line.long 0x08 "BGMAR,DMA2D Background Memory Address Register" line.long 0x0C "BGOR,DMA2D Background Offset Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") hexmask.long.word 0x0C 0.--15. 0x01 " LO ,Line offset" else hexmask.long.word 0x0C 0.--13. 0x01 " LO ,Line offset" endif line.long 0x10 "FGPFCCR,DMA2D Foreground PFC Control Register" hexmask.long.byte 0x10 24.--31. 1. " ALPHA ,Alpha value" newline sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted" bitfld.long 0x10 18.--19. " CSS ,Chroma sub-sampling" "4:4:4,4:2:2,4:2:0,?..." newline elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*") bitfld.long 0x10 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x10 20. " AI ,Alpha inverted" "Regular,Inverted" newline endif bitfld.long 0x10 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..." hexmask.long.byte 0x10 8.--15. 1. " CS ,CLUT size" bitfld.long 0x10 5. " START ,Start" "Not started,Started" bitfld.long 0x10 4. " CCM ,CLUT color mode" "ARGB8888,RGB888" newline bitfld.long 0x10 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,YCbCr,?..." endif if (((per.l(ad:0x4002B000))&0x07)==(0x01)) rgroup.long 0x20++0x03 line.long 0x00 "FGCOLR,DMA2D Foreground Color Register" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" group.long 0x24++0x03 line.long 0x00 "BGPFCCR,DMA2D Background PFC Control Register" hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha value" newline sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") rbitfld.long 0x00 21. " RBS ,Red blue swap" "Regular,Swap" rbitfld.long 0x00 20. " AI ,Alpha inverted" "Regular,Inverted" newline endif rbitfld.long 0x00 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..." hexmask.long.byte 0x00 8.--15. 1. " CS ,CLUT size" eventfld.long 0x00 5. " START ,Start" "Not started,Started" rbitfld.long 0x00 4. " CCM ,CLUT color mode" "ARGB8888,RGB888" newline rbitfld.long 0x00 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,?..." else group.long 0x20++0x07 line.long 0x00 "FGCOLR,DMA2D Foreground Color Register" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" line.long 0x04 "BGPFCCR,DMA2D Background PFC Control Register" hexmask.long.byte 0x04 24.--31. 1. " ALPHA ,Alpha value" newline sif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x04 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x04 20. " AI ,Alpha inverted" "Regular,Inverted" newline endif bitfld.long 0x04 16.--17. " AM ,Alpha mode" "No modification,ALPHA,Alpha * original,?..." hexmask.long.byte 0x04 8.--15. 1. " CS ,CLUT size" eventfld.long 0x04 5. " START ,Start" "Not started,Started" bitfld.long 0x04 4. " CCM ,CLUT color mode" "ARGB8888,RGB888" newline bitfld.long 0x04 0.--3. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88,L4,A8,A4,?..." endif if (((per.l(ad:0x4002B000))&0x07)==(0x01)) rgroup.long 0x28++0x0F line.long 0x00 "BGCOLR,DMA2D Background Color Register" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" line.long 0x04 "FGCMAR,DMA2D Foreground CLUT Memory Address Register" line.long 0x08 "BGCMAR,DMA2D Background CLUT Memory Address Register" line.long 0x0C "OPFCCR,DMA2D Output PFC Control Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted" bitfld.long 0x0C 8. " SB ,Swap bytes" "Regular,Swapped" newline elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*") bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted" newline endif bitfld.long 0x0C 0.--2. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,?..." if (((per.l((ad:0x4002B000+0x34))&0x07))==0x00) rgroup.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha value" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x01) rgroup.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x02) rgroup.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" bitfld.long 0x00 11.--15. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--10. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x03) rgroup.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" bitfld.long 0x00 15. " ALPHA ,Alpha value" "0,1" bitfld.long 0x00 10.--14. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x04) rgroup.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" bitfld.long 0x00 12.--15. " ALPHA ,Alpha value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x38++0x03 hide.long 0x00 "OCOLR,DMA2D Output Color Register" endif rgroup.long 0x3C++0x0F line.long 0x00 "OMAR,DMA2D Output Memory Address Register" line.long 0x04 "OOR,DMA2D Output Offset Register" hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset" line.long 0x08 "NLR,DMA2D Number Of Line Register" hexmask.long.word 0x08 16.--29. 1. " PL ,Pixel per lines" hexmask.long.word 0x08 0.--15. 1. " NL ,Number of lines" line.long 0x0C "LWR,DMA2D Line Watermark Register" hexmask.long.word 0x0C 0.--15. 1. " LW ,Line watermark" else group.long 0x28++0x0F line.long 0x00 "BGCOLR,DMA2D Background Color Register" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" line.long 0x04 "FGCMAR,DMA2D Foreground CLUT Memory Address Register" line.long 0x08 "BGCMAR,DMA2D Background CLUT Memory Address Register" line.long 0x0C "OPFCCR,DMA2D Output PFC Control Register" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted" bitfld.long 0x0C 8. " SB ,Swap bytes" "Regular,Swapped" newline elif cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32L496*")||cpuis("STM32L4A6*") bitfld.long 0x0C 21. " RBS ,Red blue swap" "Regular,Swap" bitfld.long 0x0C 20. " AI ,Alpha inverted" "Regular,Inverted" newline endif bitfld.long 0x0C 0.--2. " CM ,Color mode" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,?..." if (((per.l((ad:0x4002B000+0x34))&0x07))==0x00) group.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha value" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x01) group.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x02) group.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" bitfld.long 0x00 11.--15. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--10. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x03) group.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" bitfld.long 0x00 15. " ALPHA ,Alpha value" "0,1" bitfld.long 0x00 10.--14. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l((ad:0x4002B000+0x34))&0x07))==0x04) group.long 0x38++0x03 line.long 0x00 "OCOLR,DMA2D Output Color Register" bitfld.long 0x00 12.--15. " ALPHA ,Alpha value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RED ,Red value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " GREEN ,Green value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " BLUE ,Blue value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long 0x38++0x03 hide.long 0x00 "OCOLR,DMA2D Output Color Register" endif group.long 0x3C++0x0F line.long 0x00 "OMAR,DMA2D Output Memory Address Register" line.long 0x04 "OOR,DMA2D Output Offset Register" hexmask.long.word 0x04 0.--13. 0x01 " LO ,Line offset" line.long 0x08 "NLR,DMA2D Number Of Line Register" hexmask.long.word 0x08 16.--29. 1. " PL ,Pixel per lines" hexmask.long.word 0x08 0.--15. 1. " NL ,Number of lines" line.long 0x0C "LWR,DMA2D Line Watermark Register" hexmask.long.word 0x0C 0.--15. 1. " LW ,Line watermark" endif group.long 0x4C++0x03 line.long 0x00 "AMTCR,DMA2D AHB Master Timer Configuration Register" hexmask.long.byte 0x00 8.--15. 1. " DT ,Dead time" bitfld.long 0x00 0. " EN ,Enable dead time functionality" "Disabled,Enabled" sif cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32H742*")||cpuis("STM32H750*") tree "DMA2D Foreground CLUT" group.long 0x400++0x03 line.long 0x00 "FGCLUT0 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA0 ,Alpha0 " hexmask.long.byte 0x00 16.--23. 1. " RED0 ,Red0 " hexmask.long.byte 0x00 8.--15. 1. " GREEN0 ,Green0 " hexmask.long.byte 0x00 0.--7. 1. " BLUE0 ,Blue0 " group.long 0x404++0x03 line.long 0x00 "FGCLUT1 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA1 ,Alpha1 " hexmask.long.byte 0x00 16.--23. 1. " RED1 ,Red1 " hexmask.long.byte 0x00 8.--15. 1. " GREEN1 ,Green1 " hexmask.long.byte 0x00 0.--7. 1. " BLUE1 ,Blue1 " group.long 0x408++0x03 line.long 0x00 "FGCLUT2 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA2 ,Alpha2 " hexmask.long.byte 0x00 16.--23. 1. " RED2 ,Red2 " hexmask.long.byte 0x00 8.--15. 1. " GREEN2 ,Green2 " hexmask.long.byte 0x00 0.--7. 1. " BLUE2 ,Blue2 " group.long 0x40C++0x03 line.long 0x00 "FGCLUT3 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA3 ,Alpha3 " hexmask.long.byte 0x00 16.--23. 1. " RED3 ,Red3 " hexmask.long.byte 0x00 8.--15. 1. " GREEN3 ,Green3 " hexmask.long.byte 0x00 0.--7. 1. " BLUE3 ,Blue3 " group.long 0x410++0x03 line.long 0x00 "FGCLUT4 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA4 ,Alpha4 " hexmask.long.byte 0x00 16.--23. 1. " RED4 ,Red4 " hexmask.long.byte 0x00 8.--15. 1. " GREEN4 ,Green4 " hexmask.long.byte 0x00 0.--7. 1. " BLUE4 ,Blue4 " group.long 0x414++0x03 line.long 0x00 "FGCLUT5 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA5 ,Alpha5 " hexmask.long.byte 0x00 16.--23. 1. " RED5 ,Red5 " hexmask.long.byte 0x00 8.--15. 1. " GREEN5 ,Green5 " hexmask.long.byte 0x00 0.--7. 1. " BLUE5 ,Blue5 " group.long 0x418++0x03 line.long 0x00 "FGCLUT6 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA6 ,Alpha6 " hexmask.long.byte 0x00 16.--23. 1. " RED6 ,Red6 " hexmask.long.byte 0x00 8.--15. 1. " GREEN6 ,Green6 " hexmask.long.byte 0x00 0.--7. 1. " BLUE6 ,Blue6 " group.long 0x41C++0x03 line.long 0x00 "FGCLUT7 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA7 ,Alpha7 " hexmask.long.byte 0x00 16.--23. 1. " RED7 ,Red7 " hexmask.long.byte 0x00 8.--15. 1. " GREEN7 ,Green7 " hexmask.long.byte 0x00 0.--7. 1. " BLUE7 ,Blue7 " group.long 0x420++0x03 line.long 0x00 "FGCLUT8 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA8 ,Alpha8 " hexmask.long.byte 0x00 16.--23. 1. " RED8 ,Red8 " hexmask.long.byte 0x00 8.--15. 1. " GREEN8 ,Green8 " hexmask.long.byte 0x00 0.--7. 1. " BLUE8 ,Blue8 " group.long 0x424++0x03 line.long 0x00 "FGCLUT9 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA9 ,Alpha9 " hexmask.long.byte 0x00 16.--23. 1. " RED9 ,Red9 " hexmask.long.byte 0x00 8.--15. 1. " GREEN9 ,Green9 " hexmask.long.byte 0x00 0.--7. 1. " BLUE9 ,Blue9 " group.long 0x428++0x03 line.long 0x00 "FGCLUT10 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA10 ,Alpha10 " hexmask.long.byte 0x00 16.--23. 1. " RED10 ,Red10 " hexmask.long.byte 0x00 8.--15. 1. " GREEN10 ,Green10 " hexmask.long.byte 0x00 0.--7. 1. " BLUE10 ,Blue10 " group.long 0x42C++0x03 line.long 0x00 "FGCLUT11 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA11 ,Alpha11 " hexmask.long.byte 0x00 16.--23. 1. " RED11 ,Red11 " hexmask.long.byte 0x00 8.--15. 1. " GREEN11 ,Green11 " hexmask.long.byte 0x00 0.--7. 1. " BLUE11 ,Blue11 " group.long 0x430++0x03 line.long 0x00 "FGCLUT12 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA12 ,Alpha12 " hexmask.long.byte 0x00 16.--23. 1. " RED12 ,Red12 " hexmask.long.byte 0x00 8.--15. 1. " GREEN12 ,Green12 " hexmask.long.byte 0x00 0.--7. 1. " BLUE12 ,Blue12 " group.long 0x434++0x03 line.long 0x00 "FGCLUT13 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA13 ,Alpha13 " hexmask.long.byte 0x00 16.--23. 1. " RED13 ,Red13 " hexmask.long.byte 0x00 8.--15. 1. " GREEN13 ,Green13 " hexmask.long.byte 0x00 0.--7. 1. " BLUE13 ,Blue13 " group.long 0x438++0x03 line.long 0x00 "FGCLUT14 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA14 ,Alpha14 " hexmask.long.byte 0x00 16.--23. 1. " RED14 ,Red14 " hexmask.long.byte 0x00 8.--15. 1. " GREEN14 ,Green14 " hexmask.long.byte 0x00 0.--7. 1. " BLUE14 ,Blue14 " group.long 0x43C++0x03 line.long 0x00 "FGCLUT15 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA15 ,Alpha15 " hexmask.long.byte 0x00 16.--23. 1. " RED15 ,Red15 " hexmask.long.byte 0x00 8.--15. 1. " GREEN15 ,Green15 " hexmask.long.byte 0x00 0.--7. 1. " BLUE15 ,Blue15 " group.long 0x440++0x03 line.long 0x00 "FGCLUT16 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA16 ,Alpha16 " hexmask.long.byte 0x00 16.--23. 1. " RED16 ,Red16 " hexmask.long.byte 0x00 8.--15. 1. " GREEN16 ,Green16 " hexmask.long.byte 0x00 0.--7. 1. " BLUE16 ,Blue16 " group.long 0x444++0x03 line.long 0x00 "FGCLUT17 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA17 ,Alpha17 " hexmask.long.byte 0x00 16.--23. 1. " RED17 ,Red17 " hexmask.long.byte 0x00 8.--15. 1. " GREEN17 ,Green17 " hexmask.long.byte 0x00 0.--7. 1. " BLUE17 ,Blue17 " group.long 0x448++0x03 line.long 0x00 "FGCLUT18 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA18 ,Alpha18 " hexmask.long.byte 0x00 16.--23. 1. " RED18 ,Red18 " hexmask.long.byte 0x00 8.--15. 1. " GREEN18 ,Green18 " hexmask.long.byte 0x00 0.--7. 1. " BLUE18 ,Blue18 " group.long 0x44C++0x03 line.long 0x00 "FGCLUT19 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA19 ,Alpha19 " hexmask.long.byte 0x00 16.--23. 1. " RED19 ,Red19 " hexmask.long.byte 0x00 8.--15. 1. " GREEN19 ,Green19 " hexmask.long.byte 0x00 0.--7. 1. " BLUE19 ,Blue19 " group.long 0x450++0x03 line.long 0x00 "FGCLUT20 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA20 ,Alpha20 " hexmask.long.byte 0x00 16.--23. 1. " RED20 ,Red20 " hexmask.long.byte 0x00 8.--15. 1. " GREEN20 ,Green20 " hexmask.long.byte 0x00 0.--7. 1. " BLUE20 ,Blue20 " group.long 0x454++0x03 line.long 0x00 "FGCLUT21 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA21 ,Alpha21 " hexmask.long.byte 0x00 16.--23. 1. " RED21 ,Red21 " hexmask.long.byte 0x00 8.--15. 1. " GREEN21 ,Green21 " hexmask.long.byte 0x00 0.--7. 1. " BLUE21 ,Blue21 " group.long 0x458++0x03 line.long 0x00 "FGCLUT22 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA22 ,Alpha22 " hexmask.long.byte 0x00 16.--23. 1. " RED22 ,Red22 " hexmask.long.byte 0x00 8.--15. 1. " GREEN22 ,Green22 " hexmask.long.byte 0x00 0.--7. 1. " BLUE22 ,Blue22 " group.long 0x45C++0x03 line.long 0x00 "FGCLUT23 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA23 ,Alpha23 " hexmask.long.byte 0x00 16.--23. 1. " RED23 ,Red23 " hexmask.long.byte 0x00 8.--15. 1. " GREEN23 ,Green23 " hexmask.long.byte 0x00 0.--7. 1. " BLUE23 ,Blue23 " group.long 0x460++0x03 line.long 0x00 "FGCLUT24 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA24 ,Alpha24 " hexmask.long.byte 0x00 16.--23. 1. " RED24 ,Red24 " hexmask.long.byte 0x00 8.--15. 1. " GREEN24 ,Green24 " hexmask.long.byte 0x00 0.--7. 1. " BLUE24 ,Blue24 " group.long 0x464++0x03 line.long 0x00 "FGCLUT25 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA25 ,Alpha25 " hexmask.long.byte 0x00 16.--23. 1. " RED25 ,Red25 " hexmask.long.byte 0x00 8.--15. 1. " GREEN25 ,Green25 " hexmask.long.byte 0x00 0.--7. 1. " BLUE25 ,Blue25 " group.long 0x468++0x03 line.long 0x00 "FGCLUT26 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA26 ,Alpha26 " hexmask.long.byte 0x00 16.--23. 1. " RED26 ,Red26 " hexmask.long.byte 0x00 8.--15. 1. " GREEN26 ,Green26 " hexmask.long.byte 0x00 0.--7. 1. " BLUE26 ,Blue26 " group.long 0x46C++0x03 line.long 0x00 "FGCLUT27 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA27 ,Alpha27 " hexmask.long.byte 0x00 16.--23. 1. " RED27 ,Red27 " hexmask.long.byte 0x00 8.--15. 1. " GREEN27 ,Green27 " hexmask.long.byte 0x00 0.--7. 1. " BLUE27 ,Blue27 " group.long 0x470++0x03 line.long 0x00 "FGCLUT28 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA28 ,Alpha28 " hexmask.long.byte 0x00 16.--23. 1. " RED28 ,Red28 " hexmask.long.byte 0x00 8.--15. 1. " GREEN28 ,Green28 " hexmask.long.byte 0x00 0.--7. 1. " BLUE28 ,Blue28 " group.long 0x474++0x03 line.long 0x00 "FGCLUT29 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA29 ,Alpha29 " hexmask.long.byte 0x00 16.--23. 1. " RED29 ,Red29 " hexmask.long.byte 0x00 8.--15. 1. " GREEN29 ,Green29 " hexmask.long.byte 0x00 0.--7. 1. " BLUE29 ,Blue29 " group.long 0x478++0x03 line.long 0x00 "FGCLUT30 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA30 ,Alpha30 " hexmask.long.byte 0x00 16.--23. 1. " RED30 ,Red30 " hexmask.long.byte 0x00 8.--15. 1. " GREEN30 ,Green30 " hexmask.long.byte 0x00 0.--7. 1. " BLUE30 ,Blue30 " group.long 0x47C++0x03 line.long 0x00 "FGCLUT31 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA31 ,Alpha31 " hexmask.long.byte 0x00 16.--23. 1. " RED31 ,Red31 " hexmask.long.byte 0x00 8.--15. 1. " GREEN31 ,Green31 " hexmask.long.byte 0x00 0.--7. 1. " BLUE31 ,Blue31 " group.long 0x480++0x03 line.long 0x00 "FGCLUT32 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA32 ,Alpha32 " hexmask.long.byte 0x00 16.--23. 1. " RED32 ,Red32 " hexmask.long.byte 0x00 8.--15. 1. " GREEN32 ,Green32 " hexmask.long.byte 0x00 0.--7. 1. " BLUE32 ,Blue32 " group.long 0x484++0x03 line.long 0x00 "FGCLUT33 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA33 ,Alpha33 " hexmask.long.byte 0x00 16.--23. 1. " RED33 ,Red33 " hexmask.long.byte 0x00 8.--15. 1. " GREEN33 ,Green33 " hexmask.long.byte 0x00 0.--7. 1. " BLUE33 ,Blue33 " group.long 0x488++0x03 line.long 0x00 "FGCLUT34 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA34 ,Alpha34 " hexmask.long.byte 0x00 16.--23. 1. " RED34 ,Red34 " hexmask.long.byte 0x00 8.--15. 1. " GREEN34 ,Green34 " hexmask.long.byte 0x00 0.--7. 1. " BLUE34 ,Blue34 " group.long 0x48C++0x03 line.long 0x00 "FGCLUT35 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA35 ,Alpha35 " hexmask.long.byte 0x00 16.--23. 1. " RED35 ,Red35 " hexmask.long.byte 0x00 8.--15. 1. " GREEN35 ,Green35 " hexmask.long.byte 0x00 0.--7. 1. " BLUE35 ,Blue35 " group.long 0x490++0x03 line.long 0x00 "FGCLUT36 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA36 ,Alpha36 " hexmask.long.byte 0x00 16.--23. 1. " RED36 ,Red36 " hexmask.long.byte 0x00 8.--15. 1. " GREEN36 ,Green36 " hexmask.long.byte 0x00 0.--7. 1. " BLUE36 ,Blue36 " group.long 0x494++0x03 line.long 0x00 "FGCLUT37 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA37 ,Alpha37 " hexmask.long.byte 0x00 16.--23. 1. " RED37 ,Red37 " hexmask.long.byte 0x00 8.--15. 1. " GREEN37 ,Green37 " hexmask.long.byte 0x00 0.--7. 1. " BLUE37 ,Blue37 " group.long 0x498++0x03 line.long 0x00 "FGCLUT38 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA38 ,Alpha38 " hexmask.long.byte 0x00 16.--23. 1. " RED38 ,Red38 " hexmask.long.byte 0x00 8.--15. 1. " GREEN38 ,Green38 " hexmask.long.byte 0x00 0.--7. 1. " BLUE38 ,Blue38 " group.long 0x49C++0x03 line.long 0x00 "FGCLUT39 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA39 ,Alpha39 " hexmask.long.byte 0x00 16.--23. 1. " RED39 ,Red39 " hexmask.long.byte 0x00 8.--15. 1. " GREEN39 ,Green39 " hexmask.long.byte 0x00 0.--7. 1. " BLUE39 ,Blue39 " group.long 0x4A0++0x03 line.long 0x00 "FGCLUT40 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA40 ,Alpha40 " hexmask.long.byte 0x00 16.--23. 1. " RED40 ,Red40 " hexmask.long.byte 0x00 8.--15. 1. " GREEN40 ,Green40 " hexmask.long.byte 0x00 0.--7. 1. " BLUE40 ,Blue40 " group.long 0x4A4++0x03 line.long 0x00 "FGCLUT41 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA41 ,Alpha41 " hexmask.long.byte 0x00 16.--23. 1. " RED41 ,Red41 " hexmask.long.byte 0x00 8.--15. 1. " GREEN41 ,Green41 " hexmask.long.byte 0x00 0.--7. 1. " BLUE41 ,Blue41 " group.long 0x4A8++0x03 line.long 0x00 "FGCLUT42 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA42 ,Alpha42 " hexmask.long.byte 0x00 16.--23. 1. " RED42 ,Red42 " hexmask.long.byte 0x00 8.--15. 1. " GREEN42 ,Green42 " hexmask.long.byte 0x00 0.--7. 1. " BLUE42 ,Blue42 " group.long 0x4AC++0x03 line.long 0x00 "FGCLUT43 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA43 ,Alpha43 " hexmask.long.byte 0x00 16.--23. 1. " RED43 ,Red43 " hexmask.long.byte 0x00 8.--15. 1. " GREEN43 ,Green43 " hexmask.long.byte 0x00 0.--7. 1. " BLUE43 ,Blue43 " group.long 0x4B0++0x03 line.long 0x00 "FGCLUT44 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA44 ,Alpha44 " hexmask.long.byte 0x00 16.--23. 1. " RED44 ,Red44 " hexmask.long.byte 0x00 8.--15. 1. " GREEN44 ,Green44 " hexmask.long.byte 0x00 0.--7. 1. " BLUE44 ,Blue44 " group.long 0x4B4++0x03 line.long 0x00 "FGCLUT45 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA45 ,Alpha45 " hexmask.long.byte 0x00 16.--23. 1. " RED45 ,Red45 " hexmask.long.byte 0x00 8.--15. 1. " GREEN45 ,Green45 " hexmask.long.byte 0x00 0.--7. 1. " BLUE45 ,Blue45 " group.long 0x4B8++0x03 line.long 0x00 "FGCLUT46 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA46 ,Alpha46 " hexmask.long.byte 0x00 16.--23. 1. " RED46 ,Red46 " hexmask.long.byte 0x00 8.--15. 1. " GREEN46 ,Green46 " hexmask.long.byte 0x00 0.--7. 1. " BLUE46 ,Blue46 " group.long 0x4BC++0x03 line.long 0x00 "FGCLUT47 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA47 ,Alpha47 " hexmask.long.byte 0x00 16.--23. 1. " RED47 ,Red47 " hexmask.long.byte 0x00 8.--15. 1. " GREEN47 ,Green47 " hexmask.long.byte 0x00 0.--7. 1. " BLUE47 ,Blue47 " group.long 0x4C0++0x03 line.long 0x00 "FGCLUT48 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA48 ,Alpha48 " hexmask.long.byte 0x00 16.--23. 1. " RED48 ,Red48 " hexmask.long.byte 0x00 8.--15. 1. " GREEN48 ,Green48 " hexmask.long.byte 0x00 0.--7. 1. " BLUE48 ,Blue48 " group.long 0x4C4++0x03 line.long 0x00 "FGCLUT49 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA49 ,Alpha49 " hexmask.long.byte 0x00 16.--23. 1. " RED49 ,Red49 " hexmask.long.byte 0x00 8.--15. 1. " GREEN49 ,Green49 " hexmask.long.byte 0x00 0.--7. 1. " BLUE49 ,Blue49 " group.long 0x4C8++0x03 line.long 0x00 "FGCLUT50 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA50 ,Alpha50 " hexmask.long.byte 0x00 16.--23. 1. " RED50 ,Red50 " hexmask.long.byte 0x00 8.--15. 1. " GREEN50 ,Green50 " hexmask.long.byte 0x00 0.--7. 1. " BLUE50 ,Blue50 " group.long 0x4CC++0x03 line.long 0x00 "FGCLUT51 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA51 ,Alpha51 " hexmask.long.byte 0x00 16.--23. 1. " RED51 ,Red51 " hexmask.long.byte 0x00 8.--15. 1. " GREEN51 ,Green51 " hexmask.long.byte 0x00 0.--7. 1. " BLUE51 ,Blue51 " group.long 0x4D0++0x03 line.long 0x00 "FGCLUT52 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA52 ,Alpha52 " hexmask.long.byte 0x00 16.--23. 1. " RED52 ,Red52 " hexmask.long.byte 0x00 8.--15. 1. " GREEN52 ,Green52 " hexmask.long.byte 0x00 0.--7. 1. " BLUE52 ,Blue52 " group.long 0x4D4++0x03 line.long 0x00 "FGCLUT53 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA53 ,Alpha53 " hexmask.long.byte 0x00 16.--23. 1. " RED53 ,Red53 " hexmask.long.byte 0x00 8.--15. 1. " GREEN53 ,Green53 " hexmask.long.byte 0x00 0.--7. 1. " BLUE53 ,Blue53 " group.long 0x4D8++0x03 line.long 0x00 "FGCLUT54 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA54 ,Alpha54 " hexmask.long.byte 0x00 16.--23. 1. " RED54 ,Red54 " hexmask.long.byte 0x00 8.--15. 1. " GREEN54 ,Green54 " hexmask.long.byte 0x00 0.--7. 1. " BLUE54 ,Blue54 " group.long 0x4DC++0x03 line.long 0x00 "FGCLUT55 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA55 ,Alpha55 " hexmask.long.byte 0x00 16.--23. 1. " RED55 ,Red55 " hexmask.long.byte 0x00 8.--15. 1. " GREEN55 ,Green55 " hexmask.long.byte 0x00 0.--7. 1. " BLUE55 ,Blue55 " group.long 0x4E0++0x03 line.long 0x00 "FGCLUT56 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA56 ,Alpha56 " hexmask.long.byte 0x00 16.--23. 1. " RED56 ,Red56 " hexmask.long.byte 0x00 8.--15. 1. " GREEN56 ,Green56 " hexmask.long.byte 0x00 0.--7. 1. " BLUE56 ,Blue56 " group.long 0x4E4++0x03 line.long 0x00 "FGCLUT57 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA57 ,Alpha57 " hexmask.long.byte 0x00 16.--23. 1. " RED57 ,Red57 " hexmask.long.byte 0x00 8.--15. 1. " GREEN57 ,Green57 " hexmask.long.byte 0x00 0.--7. 1. " BLUE57 ,Blue57 " group.long 0x4E8++0x03 line.long 0x00 "FGCLUT58 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA58 ,Alpha58 " hexmask.long.byte 0x00 16.--23. 1. " RED58 ,Red58 " hexmask.long.byte 0x00 8.--15. 1. " GREEN58 ,Green58 " hexmask.long.byte 0x00 0.--7. 1. " BLUE58 ,Blue58 " group.long 0x4EC++0x03 line.long 0x00 "FGCLUT59 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA59 ,Alpha59 " hexmask.long.byte 0x00 16.--23. 1. " RED59 ,Red59 " hexmask.long.byte 0x00 8.--15. 1. " GREEN59 ,Green59 " hexmask.long.byte 0x00 0.--7. 1. " BLUE59 ,Blue59 " group.long 0x4F0++0x03 line.long 0x00 "FGCLUT60 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA60 ,Alpha60 " hexmask.long.byte 0x00 16.--23. 1. " RED60 ,Red60 " hexmask.long.byte 0x00 8.--15. 1. " GREEN60 ,Green60 " hexmask.long.byte 0x00 0.--7. 1. " BLUE60 ,Blue60 " group.long 0x4F4++0x03 line.long 0x00 "FGCLUT61 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA61 ,Alpha61 " hexmask.long.byte 0x00 16.--23. 1. " RED61 ,Red61 " hexmask.long.byte 0x00 8.--15. 1. " GREEN61 ,Green61 " hexmask.long.byte 0x00 0.--7. 1. " BLUE61 ,Blue61 " group.long 0x4F8++0x03 line.long 0x00 "FGCLUT62 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA62 ,Alpha62 " hexmask.long.byte 0x00 16.--23. 1. " RED62 ,Red62 " hexmask.long.byte 0x00 8.--15. 1. " GREEN62 ,Green62 " hexmask.long.byte 0x00 0.--7. 1. " BLUE62 ,Blue62 " group.long 0x4FC++0x03 line.long 0x00 "FGCLUT63 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA63 ,Alpha63 " hexmask.long.byte 0x00 16.--23. 1. " RED63 ,Red63 " hexmask.long.byte 0x00 8.--15. 1. " GREEN63 ,Green63 " hexmask.long.byte 0x00 0.--7. 1. " BLUE63 ,Blue63 " group.long 0x500++0x03 line.long 0x00 "FGCLUT64 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA64 ,Alpha64 " hexmask.long.byte 0x00 16.--23. 1. " RED64 ,Red64 " hexmask.long.byte 0x00 8.--15. 1. " GREEN64 ,Green64 " hexmask.long.byte 0x00 0.--7. 1. " BLUE64 ,Blue64 " group.long 0x504++0x03 line.long 0x00 "FGCLUT65 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA65 ,Alpha65 " hexmask.long.byte 0x00 16.--23. 1. " RED65 ,Red65 " hexmask.long.byte 0x00 8.--15. 1. " GREEN65 ,Green65 " hexmask.long.byte 0x00 0.--7. 1. " BLUE65 ,Blue65 " group.long 0x508++0x03 line.long 0x00 "FGCLUT66 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA66 ,Alpha66 " hexmask.long.byte 0x00 16.--23. 1. " RED66 ,Red66 " hexmask.long.byte 0x00 8.--15. 1. " GREEN66 ,Green66 " hexmask.long.byte 0x00 0.--7. 1. " BLUE66 ,Blue66 " group.long 0x50C++0x03 line.long 0x00 "FGCLUT67 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA67 ,Alpha67 " hexmask.long.byte 0x00 16.--23. 1. " RED67 ,Red67 " hexmask.long.byte 0x00 8.--15. 1. " GREEN67 ,Green67 " hexmask.long.byte 0x00 0.--7. 1. " BLUE67 ,Blue67 " group.long 0x510++0x03 line.long 0x00 "FGCLUT68 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA68 ,Alpha68 " hexmask.long.byte 0x00 16.--23. 1. " RED68 ,Red68 " hexmask.long.byte 0x00 8.--15. 1. " GREEN68 ,Green68 " hexmask.long.byte 0x00 0.--7. 1. " BLUE68 ,Blue68 " group.long 0x514++0x03 line.long 0x00 "FGCLUT69 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA69 ,Alpha69 " hexmask.long.byte 0x00 16.--23. 1. " RED69 ,Red69 " hexmask.long.byte 0x00 8.--15. 1. " GREEN69 ,Green69 " hexmask.long.byte 0x00 0.--7. 1. " BLUE69 ,Blue69 " group.long 0x518++0x03 line.long 0x00 "FGCLUT70 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA70 ,Alpha70 " hexmask.long.byte 0x00 16.--23. 1. " RED70 ,Red70 " hexmask.long.byte 0x00 8.--15. 1. " GREEN70 ,Green70 " hexmask.long.byte 0x00 0.--7. 1. " BLUE70 ,Blue70 " group.long 0x51C++0x03 line.long 0x00 "FGCLUT71 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA71 ,Alpha71 " hexmask.long.byte 0x00 16.--23. 1. " RED71 ,Red71 " hexmask.long.byte 0x00 8.--15. 1. " GREEN71 ,Green71 " hexmask.long.byte 0x00 0.--7. 1. " BLUE71 ,Blue71 " group.long 0x520++0x03 line.long 0x00 "FGCLUT72 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA72 ,Alpha72 " hexmask.long.byte 0x00 16.--23. 1. " RED72 ,Red72 " hexmask.long.byte 0x00 8.--15. 1. " GREEN72 ,Green72 " hexmask.long.byte 0x00 0.--7. 1. " BLUE72 ,Blue72 " group.long 0x524++0x03 line.long 0x00 "FGCLUT73 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA73 ,Alpha73 " hexmask.long.byte 0x00 16.--23. 1. " RED73 ,Red73 " hexmask.long.byte 0x00 8.--15. 1. " GREEN73 ,Green73 " hexmask.long.byte 0x00 0.--7. 1. " BLUE73 ,Blue73 " group.long 0x528++0x03 line.long 0x00 "FGCLUT74 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA74 ,Alpha74 " hexmask.long.byte 0x00 16.--23. 1. " RED74 ,Red74 " hexmask.long.byte 0x00 8.--15. 1. " GREEN74 ,Green74 " hexmask.long.byte 0x00 0.--7. 1. " BLUE74 ,Blue74 " group.long 0x52C++0x03 line.long 0x00 "FGCLUT75 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA75 ,Alpha75 " hexmask.long.byte 0x00 16.--23. 1. " RED75 ,Red75 " hexmask.long.byte 0x00 8.--15. 1. " GREEN75 ,Green75 " hexmask.long.byte 0x00 0.--7. 1. " BLUE75 ,Blue75 " group.long 0x530++0x03 line.long 0x00 "FGCLUT76 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA76 ,Alpha76 " hexmask.long.byte 0x00 16.--23. 1. " RED76 ,Red76 " hexmask.long.byte 0x00 8.--15. 1. " GREEN76 ,Green76 " hexmask.long.byte 0x00 0.--7. 1. " BLUE76 ,Blue76 " group.long 0x534++0x03 line.long 0x00 "FGCLUT77 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA77 ,Alpha77 " hexmask.long.byte 0x00 16.--23. 1. " RED77 ,Red77 " hexmask.long.byte 0x00 8.--15. 1. " GREEN77 ,Green77 " hexmask.long.byte 0x00 0.--7. 1. " BLUE77 ,Blue77 " group.long 0x538++0x03 line.long 0x00 "FGCLUT78 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA78 ,Alpha78 " hexmask.long.byte 0x00 16.--23. 1. " RED78 ,Red78 " hexmask.long.byte 0x00 8.--15. 1. " GREEN78 ,Green78 " hexmask.long.byte 0x00 0.--7. 1. " BLUE78 ,Blue78 " group.long 0x53C++0x03 line.long 0x00 "FGCLUT79 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA79 ,Alpha79 " hexmask.long.byte 0x00 16.--23. 1. " RED79 ,Red79 " hexmask.long.byte 0x00 8.--15. 1. " GREEN79 ,Green79 " hexmask.long.byte 0x00 0.--7. 1. " BLUE79 ,Blue79 " group.long 0x540++0x03 line.long 0x00 "FGCLUT80 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA80 ,Alpha80 " hexmask.long.byte 0x00 16.--23. 1. " RED80 ,Red80 " hexmask.long.byte 0x00 8.--15. 1. " GREEN80 ,Green80 " hexmask.long.byte 0x00 0.--7. 1. " BLUE80 ,Blue80 " group.long 0x544++0x03 line.long 0x00 "FGCLUT81 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA81 ,Alpha81 " hexmask.long.byte 0x00 16.--23. 1. " RED81 ,Red81 " hexmask.long.byte 0x00 8.--15. 1. " GREEN81 ,Green81 " hexmask.long.byte 0x00 0.--7. 1. " BLUE81 ,Blue81 " group.long 0x548++0x03 line.long 0x00 "FGCLUT82 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA82 ,Alpha82 " hexmask.long.byte 0x00 16.--23. 1. " RED82 ,Red82 " hexmask.long.byte 0x00 8.--15. 1. " GREEN82 ,Green82 " hexmask.long.byte 0x00 0.--7. 1. " BLUE82 ,Blue82 " group.long 0x54C++0x03 line.long 0x00 "FGCLUT83 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA83 ,Alpha83 " hexmask.long.byte 0x00 16.--23. 1. " RED83 ,Red83 " hexmask.long.byte 0x00 8.--15. 1. " GREEN83 ,Green83 " hexmask.long.byte 0x00 0.--7. 1. " BLUE83 ,Blue83 " group.long 0x550++0x03 line.long 0x00 "FGCLUT84 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA84 ,Alpha84 " hexmask.long.byte 0x00 16.--23. 1. " RED84 ,Red84 " hexmask.long.byte 0x00 8.--15. 1. " GREEN84 ,Green84 " hexmask.long.byte 0x00 0.--7. 1. " BLUE84 ,Blue84 " group.long 0x554++0x03 line.long 0x00 "FGCLUT85 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA85 ,Alpha85 " hexmask.long.byte 0x00 16.--23. 1. " RED85 ,Red85 " hexmask.long.byte 0x00 8.--15. 1. " GREEN85 ,Green85 " hexmask.long.byte 0x00 0.--7. 1. " BLUE85 ,Blue85 " group.long 0x558++0x03 line.long 0x00 "FGCLUT86 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA86 ,Alpha86 " hexmask.long.byte 0x00 16.--23. 1. " RED86 ,Red86 " hexmask.long.byte 0x00 8.--15. 1. " GREEN86 ,Green86 " hexmask.long.byte 0x00 0.--7. 1. " BLUE86 ,Blue86 " group.long 0x55C++0x03 line.long 0x00 "FGCLUT87 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA87 ,Alpha87 " hexmask.long.byte 0x00 16.--23. 1. " RED87 ,Red87 " hexmask.long.byte 0x00 8.--15. 1. " GREEN87 ,Green87 " hexmask.long.byte 0x00 0.--7. 1. " BLUE87 ,Blue87 " group.long 0x560++0x03 line.long 0x00 "FGCLUT88 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA88 ,Alpha88 " hexmask.long.byte 0x00 16.--23. 1. " RED88 ,Red88 " hexmask.long.byte 0x00 8.--15. 1. " GREEN88 ,Green88 " hexmask.long.byte 0x00 0.--7. 1. " BLUE88 ,Blue88 " group.long 0x564++0x03 line.long 0x00 "FGCLUT89 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA89 ,Alpha89 " hexmask.long.byte 0x00 16.--23. 1. " RED89 ,Red89 " hexmask.long.byte 0x00 8.--15. 1. " GREEN89 ,Green89 " hexmask.long.byte 0x00 0.--7. 1. " BLUE89 ,Blue89 " group.long 0x568++0x03 line.long 0x00 "FGCLUT90 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA90 ,Alpha90 " hexmask.long.byte 0x00 16.--23. 1. " RED90 ,Red90 " hexmask.long.byte 0x00 8.--15. 1. " GREEN90 ,Green90 " hexmask.long.byte 0x00 0.--7. 1. " BLUE90 ,Blue90 " group.long 0x56C++0x03 line.long 0x00 "FGCLUT91 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA91 ,Alpha91 " hexmask.long.byte 0x00 16.--23. 1. " RED91 ,Red91 " hexmask.long.byte 0x00 8.--15. 1. " GREEN91 ,Green91 " hexmask.long.byte 0x00 0.--7. 1. " BLUE91 ,Blue91 " group.long 0x570++0x03 line.long 0x00 "FGCLUT92 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA92 ,Alpha92 " hexmask.long.byte 0x00 16.--23. 1. " RED92 ,Red92 " hexmask.long.byte 0x00 8.--15. 1. " GREEN92 ,Green92 " hexmask.long.byte 0x00 0.--7. 1. " BLUE92 ,Blue92 " group.long 0x574++0x03 line.long 0x00 "FGCLUT93 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA93 ,Alpha93 " hexmask.long.byte 0x00 16.--23. 1. " RED93 ,Red93 " hexmask.long.byte 0x00 8.--15. 1. " GREEN93 ,Green93 " hexmask.long.byte 0x00 0.--7. 1. " BLUE93 ,Blue93 " group.long 0x578++0x03 line.long 0x00 "FGCLUT94 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA94 ,Alpha94 " hexmask.long.byte 0x00 16.--23. 1. " RED94 ,Red94 " hexmask.long.byte 0x00 8.--15. 1. " GREEN94 ,Green94 " hexmask.long.byte 0x00 0.--7. 1. " BLUE94 ,Blue94 " group.long 0x57C++0x03 line.long 0x00 "FGCLUT95 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA95 ,Alpha95 " hexmask.long.byte 0x00 16.--23. 1. " RED95 ,Red95 " hexmask.long.byte 0x00 8.--15. 1. " GREEN95 ,Green95 " hexmask.long.byte 0x00 0.--7. 1. " BLUE95 ,Blue95 " group.long 0x580++0x03 line.long 0x00 "FGCLUT96 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA96 ,Alpha96 " hexmask.long.byte 0x00 16.--23. 1. " RED96 ,Red96 " hexmask.long.byte 0x00 8.--15. 1. " GREEN96 ,Green96 " hexmask.long.byte 0x00 0.--7. 1. " BLUE96 ,Blue96 " group.long 0x584++0x03 line.long 0x00 "FGCLUT97 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA97 ,Alpha97 " hexmask.long.byte 0x00 16.--23. 1. " RED97 ,Red97 " hexmask.long.byte 0x00 8.--15. 1. " GREEN97 ,Green97 " hexmask.long.byte 0x00 0.--7. 1. " BLUE97 ,Blue97 " group.long 0x588++0x03 line.long 0x00 "FGCLUT98 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA98 ,Alpha98 " hexmask.long.byte 0x00 16.--23. 1. " RED98 ,Red98 " hexmask.long.byte 0x00 8.--15. 1. " GREEN98 ,Green98 " hexmask.long.byte 0x00 0.--7. 1. " BLUE98 ,Blue98 " group.long 0x58C++0x03 line.long 0x00 "FGCLUT99 ,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA99 ,Alpha99 " hexmask.long.byte 0x00 16.--23. 1. " RED99 ,Red99 " hexmask.long.byte 0x00 8.--15. 1. " GREEN99 ,Green99 " hexmask.long.byte 0x00 0.--7. 1. " BLUE99 ,Blue99 " group.long 0x590++0x03 line.long 0x00 "FGCLUT100,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA100 ,Alpha100" hexmask.long.byte 0x00 16.--23. 1. " RED100 ,Red100" hexmask.long.byte 0x00 8.--15. 1. " GREEN100 ,Green100" hexmask.long.byte 0x00 0.--7. 1. " BLUE100 ,Blue100" group.long 0x594++0x03 line.long 0x00 "FGCLUT101,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA101 ,Alpha101" hexmask.long.byte 0x00 16.--23. 1. " RED101 ,Red101" hexmask.long.byte 0x00 8.--15. 1. " GREEN101 ,Green101" hexmask.long.byte 0x00 0.--7. 1. " BLUE101 ,Blue101" group.long 0x598++0x03 line.long 0x00 "FGCLUT102,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA102 ,Alpha102" hexmask.long.byte 0x00 16.--23. 1. " RED102 ,Red102" hexmask.long.byte 0x00 8.--15. 1. " GREEN102 ,Green102" hexmask.long.byte 0x00 0.--7. 1. " BLUE102 ,Blue102" group.long 0x59C++0x03 line.long 0x00 "FGCLUT103,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA103 ,Alpha103" hexmask.long.byte 0x00 16.--23. 1. " RED103 ,Red103" hexmask.long.byte 0x00 8.--15. 1. " GREEN103 ,Green103" hexmask.long.byte 0x00 0.--7. 1. " BLUE103 ,Blue103" group.long 0x5A0++0x03 line.long 0x00 "FGCLUT104,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA104 ,Alpha104" hexmask.long.byte 0x00 16.--23. 1. " RED104 ,Red104" hexmask.long.byte 0x00 8.--15. 1. " GREEN104 ,Green104" hexmask.long.byte 0x00 0.--7. 1. " BLUE104 ,Blue104" group.long 0x5A4++0x03 line.long 0x00 "FGCLUT105,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA105 ,Alpha105" hexmask.long.byte 0x00 16.--23. 1. " RED105 ,Red105" hexmask.long.byte 0x00 8.--15. 1. " GREEN105 ,Green105" hexmask.long.byte 0x00 0.--7. 1. " BLUE105 ,Blue105" group.long 0x5A8++0x03 line.long 0x00 "FGCLUT106,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA106 ,Alpha106" hexmask.long.byte 0x00 16.--23. 1. " RED106 ,Red106" hexmask.long.byte 0x00 8.--15. 1. " GREEN106 ,Green106" hexmask.long.byte 0x00 0.--7. 1. " BLUE106 ,Blue106" group.long 0x5AC++0x03 line.long 0x00 "FGCLUT107,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA107 ,Alpha107" hexmask.long.byte 0x00 16.--23. 1. " RED107 ,Red107" hexmask.long.byte 0x00 8.--15. 1. " GREEN107 ,Green107" hexmask.long.byte 0x00 0.--7. 1. " BLUE107 ,Blue107" group.long 0x5B0++0x03 line.long 0x00 "FGCLUT108,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA108 ,Alpha108" hexmask.long.byte 0x00 16.--23. 1. " RED108 ,Red108" hexmask.long.byte 0x00 8.--15. 1. " GREEN108 ,Green108" hexmask.long.byte 0x00 0.--7. 1. " BLUE108 ,Blue108" group.long 0x5B4++0x03 line.long 0x00 "FGCLUT109,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA109 ,Alpha109" hexmask.long.byte 0x00 16.--23. 1. " RED109 ,Red109" hexmask.long.byte 0x00 8.--15. 1. " GREEN109 ,Green109" hexmask.long.byte 0x00 0.--7. 1. " BLUE109 ,Blue109" group.long 0x5B8++0x03 line.long 0x00 "FGCLUT110,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA110 ,Alpha110" hexmask.long.byte 0x00 16.--23. 1. " RED110 ,Red110" hexmask.long.byte 0x00 8.--15. 1. " GREEN110 ,Green110" hexmask.long.byte 0x00 0.--7. 1. " BLUE110 ,Blue110" group.long 0x5BC++0x03 line.long 0x00 "FGCLUT111,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA111 ,Alpha111" hexmask.long.byte 0x00 16.--23. 1. " RED111 ,Red111" hexmask.long.byte 0x00 8.--15. 1. " GREEN111 ,Green111" hexmask.long.byte 0x00 0.--7. 1. " BLUE111 ,Blue111" group.long 0x5C0++0x03 line.long 0x00 "FGCLUT112,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA112 ,Alpha112" hexmask.long.byte 0x00 16.--23. 1. " RED112 ,Red112" hexmask.long.byte 0x00 8.--15. 1. " GREEN112 ,Green112" hexmask.long.byte 0x00 0.--7. 1. " BLUE112 ,Blue112" group.long 0x5C4++0x03 line.long 0x00 "FGCLUT113,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA113 ,Alpha113" hexmask.long.byte 0x00 16.--23. 1. " RED113 ,Red113" hexmask.long.byte 0x00 8.--15. 1. " GREEN113 ,Green113" hexmask.long.byte 0x00 0.--7. 1. " BLUE113 ,Blue113" group.long 0x5C8++0x03 line.long 0x00 "FGCLUT114,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA114 ,Alpha114" hexmask.long.byte 0x00 16.--23. 1. " RED114 ,Red114" hexmask.long.byte 0x00 8.--15. 1. " GREEN114 ,Green114" hexmask.long.byte 0x00 0.--7. 1. " BLUE114 ,Blue114" group.long 0x5CC++0x03 line.long 0x00 "FGCLUT115,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA115 ,Alpha115" hexmask.long.byte 0x00 16.--23. 1. " RED115 ,Red115" hexmask.long.byte 0x00 8.--15. 1. " GREEN115 ,Green115" hexmask.long.byte 0x00 0.--7. 1. " BLUE115 ,Blue115" group.long 0x5D0++0x03 line.long 0x00 "FGCLUT116,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA116 ,Alpha116" hexmask.long.byte 0x00 16.--23. 1. " RED116 ,Red116" hexmask.long.byte 0x00 8.--15. 1. " GREEN116 ,Green116" hexmask.long.byte 0x00 0.--7. 1. " BLUE116 ,Blue116" group.long 0x5D4++0x03 line.long 0x00 "FGCLUT117,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA117 ,Alpha117" hexmask.long.byte 0x00 16.--23. 1. " RED117 ,Red117" hexmask.long.byte 0x00 8.--15. 1. " GREEN117 ,Green117" hexmask.long.byte 0x00 0.--7. 1. " BLUE117 ,Blue117" group.long 0x5D8++0x03 line.long 0x00 "FGCLUT118,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA118 ,Alpha118" hexmask.long.byte 0x00 16.--23. 1. " RED118 ,Red118" hexmask.long.byte 0x00 8.--15. 1. " GREEN118 ,Green118" hexmask.long.byte 0x00 0.--7. 1. " BLUE118 ,Blue118" group.long 0x5DC++0x03 line.long 0x00 "FGCLUT119,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA119 ,Alpha119" hexmask.long.byte 0x00 16.--23. 1. " RED119 ,Red119" hexmask.long.byte 0x00 8.--15. 1. " GREEN119 ,Green119" hexmask.long.byte 0x00 0.--7. 1. " BLUE119 ,Blue119" group.long 0x5E0++0x03 line.long 0x00 "FGCLUT120,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA120 ,Alpha120" hexmask.long.byte 0x00 16.--23. 1. " RED120 ,Red120" hexmask.long.byte 0x00 8.--15. 1. " GREEN120 ,Green120" hexmask.long.byte 0x00 0.--7. 1. " BLUE120 ,Blue120" group.long 0x5E4++0x03 line.long 0x00 "FGCLUT121,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA121 ,Alpha121" hexmask.long.byte 0x00 16.--23. 1. " RED121 ,Red121" hexmask.long.byte 0x00 8.--15. 1. " GREEN121 ,Green121" hexmask.long.byte 0x00 0.--7. 1. " BLUE121 ,Blue121" group.long 0x5E8++0x03 line.long 0x00 "FGCLUT122,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA122 ,Alpha122" hexmask.long.byte 0x00 16.--23. 1. " RED122 ,Red122" hexmask.long.byte 0x00 8.--15. 1. " GREEN122 ,Green122" hexmask.long.byte 0x00 0.--7. 1. " BLUE122 ,Blue122" group.long 0x5EC++0x03 line.long 0x00 "FGCLUT123,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA123 ,Alpha123" hexmask.long.byte 0x00 16.--23. 1. " RED123 ,Red123" hexmask.long.byte 0x00 8.--15. 1. " GREEN123 ,Green123" hexmask.long.byte 0x00 0.--7. 1. " BLUE123 ,Blue123" group.long 0x5F0++0x03 line.long 0x00 "FGCLUT124,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA124 ,Alpha124" hexmask.long.byte 0x00 16.--23. 1. " RED124 ,Red124" hexmask.long.byte 0x00 8.--15. 1. " GREEN124 ,Green124" hexmask.long.byte 0x00 0.--7. 1. " BLUE124 ,Blue124" group.long 0x5F4++0x03 line.long 0x00 "FGCLUT125,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA125 ,Alpha125" hexmask.long.byte 0x00 16.--23. 1. " RED125 ,Red125" hexmask.long.byte 0x00 8.--15. 1. " GREEN125 ,Green125" hexmask.long.byte 0x00 0.--7. 1. " BLUE125 ,Blue125" group.long 0x5F8++0x03 line.long 0x00 "FGCLUT126,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA126 ,Alpha126" hexmask.long.byte 0x00 16.--23. 1. " RED126 ,Red126" hexmask.long.byte 0x00 8.--15. 1. " GREEN126 ,Green126" hexmask.long.byte 0x00 0.--7. 1. " BLUE126 ,Blue126" group.long 0x5FC++0x03 line.long 0x00 "FGCLUT127,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA127 ,Alpha127" hexmask.long.byte 0x00 16.--23. 1. " RED127 ,Red127" hexmask.long.byte 0x00 8.--15. 1. " GREEN127 ,Green127" hexmask.long.byte 0x00 0.--7. 1. " BLUE127 ,Blue127" group.long 0x600++0x03 line.long 0x00 "FGCLUT128,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA128 ,Alpha128" hexmask.long.byte 0x00 16.--23. 1. " RED128 ,Red128" hexmask.long.byte 0x00 8.--15. 1. " GREEN128 ,Green128" hexmask.long.byte 0x00 0.--7. 1. " BLUE128 ,Blue128" group.long 0x604++0x03 line.long 0x00 "FGCLUT129,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA129 ,Alpha129" hexmask.long.byte 0x00 16.--23. 1. " RED129 ,Red129" hexmask.long.byte 0x00 8.--15. 1. " GREEN129 ,Green129" hexmask.long.byte 0x00 0.--7. 1. " BLUE129 ,Blue129" group.long 0x608++0x03 line.long 0x00 "FGCLUT130,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA130 ,Alpha130" hexmask.long.byte 0x00 16.--23. 1. " RED130 ,Red130" hexmask.long.byte 0x00 8.--15. 1. " GREEN130 ,Green130" hexmask.long.byte 0x00 0.--7. 1. " BLUE130 ,Blue130" group.long 0x60C++0x03 line.long 0x00 "FGCLUT131,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA131 ,Alpha131" hexmask.long.byte 0x00 16.--23. 1. " RED131 ,Red131" hexmask.long.byte 0x00 8.--15. 1. " GREEN131 ,Green131" hexmask.long.byte 0x00 0.--7. 1. " BLUE131 ,Blue131" group.long 0x610++0x03 line.long 0x00 "FGCLUT132,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA132 ,Alpha132" hexmask.long.byte 0x00 16.--23. 1. " RED132 ,Red132" hexmask.long.byte 0x00 8.--15. 1. " GREEN132 ,Green132" hexmask.long.byte 0x00 0.--7. 1. " BLUE132 ,Blue132" group.long 0x614++0x03 line.long 0x00 "FGCLUT133,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA133 ,Alpha133" hexmask.long.byte 0x00 16.--23. 1. " RED133 ,Red133" hexmask.long.byte 0x00 8.--15. 1. " GREEN133 ,Green133" hexmask.long.byte 0x00 0.--7. 1. " BLUE133 ,Blue133" group.long 0x618++0x03 line.long 0x00 "FGCLUT134,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA134 ,Alpha134" hexmask.long.byte 0x00 16.--23. 1. " RED134 ,Red134" hexmask.long.byte 0x00 8.--15. 1. " GREEN134 ,Green134" hexmask.long.byte 0x00 0.--7. 1. " BLUE134 ,Blue134" group.long 0x61C++0x03 line.long 0x00 "FGCLUT135,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA135 ,Alpha135" hexmask.long.byte 0x00 16.--23. 1. " RED135 ,Red135" hexmask.long.byte 0x00 8.--15. 1. " GREEN135 ,Green135" hexmask.long.byte 0x00 0.--7. 1. " BLUE135 ,Blue135" group.long 0x620++0x03 line.long 0x00 "FGCLUT136,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA136 ,Alpha136" hexmask.long.byte 0x00 16.--23. 1. " RED136 ,Red136" hexmask.long.byte 0x00 8.--15. 1. " GREEN136 ,Green136" hexmask.long.byte 0x00 0.--7. 1. " BLUE136 ,Blue136" group.long 0x624++0x03 line.long 0x00 "FGCLUT137,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA137 ,Alpha137" hexmask.long.byte 0x00 16.--23. 1. " RED137 ,Red137" hexmask.long.byte 0x00 8.--15. 1. " GREEN137 ,Green137" hexmask.long.byte 0x00 0.--7. 1. " BLUE137 ,Blue137" group.long 0x628++0x03 line.long 0x00 "FGCLUT138,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA138 ,Alpha138" hexmask.long.byte 0x00 16.--23. 1. " RED138 ,Red138" hexmask.long.byte 0x00 8.--15. 1. " GREEN138 ,Green138" hexmask.long.byte 0x00 0.--7. 1. " BLUE138 ,Blue138" group.long 0x62C++0x03 line.long 0x00 "FGCLUT139,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA139 ,Alpha139" hexmask.long.byte 0x00 16.--23. 1. " RED139 ,Red139" hexmask.long.byte 0x00 8.--15. 1. " GREEN139 ,Green139" hexmask.long.byte 0x00 0.--7. 1. " BLUE139 ,Blue139" group.long 0x630++0x03 line.long 0x00 "FGCLUT140,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA140 ,Alpha140" hexmask.long.byte 0x00 16.--23. 1. " RED140 ,Red140" hexmask.long.byte 0x00 8.--15. 1. " GREEN140 ,Green140" hexmask.long.byte 0x00 0.--7. 1. " BLUE140 ,Blue140" group.long 0x634++0x03 line.long 0x00 "FGCLUT141,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA141 ,Alpha141" hexmask.long.byte 0x00 16.--23. 1. " RED141 ,Red141" hexmask.long.byte 0x00 8.--15. 1. " GREEN141 ,Green141" hexmask.long.byte 0x00 0.--7. 1. " BLUE141 ,Blue141" group.long 0x638++0x03 line.long 0x00 "FGCLUT142,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA142 ,Alpha142" hexmask.long.byte 0x00 16.--23. 1. " RED142 ,Red142" hexmask.long.byte 0x00 8.--15. 1. " GREEN142 ,Green142" hexmask.long.byte 0x00 0.--7. 1. " BLUE142 ,Blue142" group.long 0x63C++0x03 line.long 0x00 "FGCLUT143,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA143 ,Alpha143" hexmask.long.byte 0x00 16.--23. 1. " RED143 ,Red143" hexmask.long.byte 0x00 8.--15. 1. " GREEN143 ,Green143" hexmask.long.byte 0x00 0.--7. 1. " BLUE143 ,Blue143" group.long 0x640++0x03 line.long 0x00 "FGCLUT144,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA144 ,Alpha144" hexmask.long.byte 0x00 16.--23. 1. " RED144 ,Red144" hexmask.long.byte 0x00 8.--15. 1. " GREEN144 ,Green144" hexmask.long.byte 0x00 0.--7. 1. " BLUE144 ,Blue144" group.long 0x644++0x03 line.long 0x00 "FGCLUT145,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA145 ,Alpha145" hexmask.long.byte 0x00 16.--23. 1. " RED145 ,Red145" hexmask.long.byte 0x00 8.--15. 1. " GREEN145 ,Green145" hexmask.long.byte 0x00 0.--7. 1. " BLUE145 ,Blue145" group.long 0x648++0x03 line.long 0x00 "FGCLUT146,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA146 ,Alpha146" hexmask.long.byte 0x00 16.--23. 1. " RED146 ,Red146" hexmask.long.byte 0x00 8.--15. 1. " GREEN146 ,Green146" hexmask.long.byte 0x00 0.--7. 1. " BLUE146 ,Blue146" group.long 0x64C++0x03 line.long 0x00 "FGCLUT147,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA147 ,Alpha147" hexmask.long.byte 0x00 16.--23. 1. " RED147 ,Red147" hexmask.long.byte 0x00 8.--15. 1. " GREEN147 ,Green147" hexmask.long.byte 0x00 0.--7. 1. " BLUE147 ,Blue147" group.long 0x650++0x03 line.long 0x00 "FGCLUT148,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA148 ,Alpha148" hexmask.long.byte 0x00 16.--23. 1. " RED148 ,Red148" hexmask.long.byte 0x00 8.--15. 1. " GREEN148 ,Green148" hexmask.long.byte 0x00 0.--7. 1. " BLUE148 ,Blue148" group.long 0x654++0x03 line.long 0x00 "FGCLUT149,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA149 ,Alpha149" hexmask.long.byte 0x00 16.--23. 1. " RED149 ,Red149" hexmask.long.byte 0x00 8.--15. 1. " GREEN149 ,Green149" hexmask.long.byte 0x00 0.--7. 1. " BLUE149 ,Blue149" group.long 0x658++0x03 line.long 0x00 "FGCLUT150,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA150 ,Alpha150" hexmask.long.byte 0x00 16.--23. 1. " RED150 ,Red150" hexmask.long.byte 0x00 8.--15. 1. " GREEN150 ,Green150" hexmask.long.byte 0x00 0.--7. 1. " BLUE150 ,Blue150" group.long 0x65C++0x03 line.long 0x00 "FGCLUT151,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA151 ,Alpha151" hexmask.long.byte 0x00 16.--23. 1. " RED151 ,Red151" hexmask.long.byte 0x00 8.--15. 1. " GREEN151 ,Green151" hexmask.long.byte 0x00 0.--7. 1. " BLUE151 ,Blue151" group.long 0x660++0x03 line.long 0x00 "FGCLUT152,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA152 ,Alpha152" hexmask.long.byte 0x00 16.--23. 1. " RED152 ,Red152" hexmask.long.byte 0x00 8.--15. 1. " GREEN152 ,Green152" hexmask.long.byte 0x00 0.--7. 1. " BLUE152 ,Blue152" group.long 0x664++0x03 line.long 0x00 "FGCLUT153,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA153 ,Alpha153" hexmask.long.byte 0x00 16.--23. 1. " RED153 ,Red153" hexmask.long.byte 0x00 8.--15. 1. " GREEN153 ,Green153" hexmask.long.byte 0x00 0.--7. 1. " BLUE153 ,Blue153" group.long 0x668++0x03 line.long 0x00 "FGCLUT154,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA154 ,Alpha154" hexmask.long.byte 0x00 16.--23. 1. " RED154 ,Red154" hexmask.long.byte 0x00 8.--15. 1. " GREEN154 ,Green154" hexmask.long.byte 0x00 0.--7. 1. " BLUE154 ,Blue154" group.long 0x66C++0x03 line.long 0x00 "FGCLUT155,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA155 ,Alpha155" hexmask.long.byte 0x00 16.--23. 1. " RED155 ,Red155" hexmask.long.byte 0x00 8.--15. 1. " GREEN155 ,Green155" hexmask.long.byte 0x00 0.--7. 1. " BLUE155 ,Blue155" group.long 0x670++0x03 line.long 0x00 "FGCLUT156,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA156 ,Alpha156" hexmask.long.byte 0x00 16.--23. 1. " RED156 ,Red156" hexmask.long.byte 0x00 8.--15. 1. " GREEN156 ,Green156" hexmask.long.byte 0x00 0.--7. 1. " BLUE156 ,Blue156" group.long 0x674++0x03 line.long 0x00 "FGCLUT157,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA157 ,Alpha157" hexmask.long.byte 0x00 16.--23. 1. " RED157 ,Red157" hexmask.long.byte 0x00 8.--15. 1. " GREEN157 ,Green157" hexmask.long.byte 0x00 0.--7. 1. " BLUE157 ,Blue157" group.long 0x678++0x03 line.long 0x00 "FGCLUT158,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA158 ,Alpha158" hexmask.long.byte 0x00 16.--23. 1. " RED158 ,Red158" hexmask.long.byte 0x00 8.--15. 1. " GREEN158 ,Green158" hexmask.long.byte 0x00 0.--7. 1. " BLUE158 ,Blue158" group.long 0x67C++0x03 line.long 0x00 "FGCLUT159,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA159 ,Alpha159" hexmask.long.byte 0x00 16.--23. 1. " RED159 ,Red159" hexmask.long.byte 0x00 8.--15. 1. " GREEN159 ,Green159" hexmask.long.byte 0x00 0.--7. 1. " BLUE159 ,Blue159" group.long 0x680++0x03 line.long 0x00 "FGCLUT160,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA160 ,Alpha160" hexmask.long.byte 0x00 16.--23. 1. " RED160 ,Red160" hexmask.long.byte 0x00 8.--15. 1. " GREEN160 ,Green160" hexmask.long.byte 0x00 0.--7. 1. " BLUE160 ,Blue160" group.long 0x684++0x03 line.long 0x00 "FGCLUT161,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA161 ,Alpha161" hexmask.long.byte 0x00 16.--23. 1. " RED161 ,Red161" hexmask.long.byte 0x00 8.--15. 1. " GREEN161 ,Green161" hexmask.long.byte 0x00 0.--7. 1. " BLUE161 ,Blue161" group.long 0x688++0x03 line.long 0x00 "FGCLUT162,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA162 ,Alpha162" hexmask.long.byte 0x00 16.--23. 1. " RED162 ,Red162" hexmask.long.byte 0x00 8.--15. 1. " GREEN162 ,Green162" hexmask.long.byte 0x00 0.--7. 1. " BLUE162 ,Blue162" group.long 0x68C++0x03 line.long 0x00 "FGCLUT163,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA163 ,Alpha163" hexmask.long.byte 0x00 16.--23. 1. " RED163 ,Red163" hexmask.long.byte 0x00 8.--15. 1. " GREEN163 ,Green163" hexmask.long.byte 0x00 0.--7. 1. " BLUE163 ,Blue163" group.long 0x690++0x03 line.long 0x00 "FGCLUT164,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA164 ,Alpha164" hexmask.long.byte 0x00 16.--23. 1. " RED164 ,Red164" hexmask.long.byte 0x00 8.--15. 1. " GREEN164 ,Green164" hexmask.long.byte 0x00 0.--7. 1. " BLUE164 ,Blue164" group.long 0x694++0x03 line.long 0x00 "FGCLUT165,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA165 ,Alpha165" hexmask.long.byte 0x00 16.--23. 1. " RED165 ,Red165" hexmask.long.byte 0x00 8.--15. 1. " GREEN165 ,Green165" hexmask.long.byte 0x00 0.--7. 1. " BLUE165 ,Blue165" group.long 0x698++0x03 line.long 0x00 "FGCLUT166,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA166 ,Alpha166" hexmask.long.byte 0x00 16.--23. 1. " RED166 ,Red166" hexmask.long.byte 0x00 8.--15. 1. " GREEN166 ,Green166" hexmask.long.byte 0x00 0.--7. 1. " BLUE166 ,Blue166" group.long 0x69C++0x03 line.long 0x00 "FGCLUT167,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA167 ,Alpha167" hexmask.long.byte 0x00 16.--23. 1. " RED167 ,Red167" hexmask.long.byte 0x00 8.--15. 1. " GREEN167 ,Green167" hexmask.long.byte 0x00 0.--7. 1. " BLUE167 ,Blue167" group.long 0x6A0++0x03 line.long 0x00 "FGCLUT168,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA168 ,Alpha168" hexmask.long.byte 0x00 16.--23. 1. " RED168 ,Red168" hexmask.long.byte 0x00 8.--15. 1. " GREEN168 ,Green168" hexmask.long.byte 0x00 0.--7. 1. " BLUE168 ,Blue168" group.long 0x6A4++0x03 line.long 0x00 "FGCLUT169,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA169 ,Alpha169" hexmask.long.byte 0x00 16.--23. 1. " RED169 ,Red169" hexmask.long.byte 0x00 8.--15. 1. " GREEN169 ,Green169" hexmask.long.byte 0x00 0.--7. 1. " BLUE169 ,Blue169" group.long 0x6A8++0x03 line.long 0x00 "FGCLUT170,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA170 ,Alpha170" hexmask.long.byte 0x00 16.--23. 1. " RED170 ,Red170" hexmask.long.byte 0x00 8.--15. 1. " GREEN170 ,Green170" hexmask.long.byte 0x00 0.--7. 1. " BLUE170 ,Blue170" group.long 0x6AC++0x03 line.long 0x00 "FGCLUT171,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA171 ,Alpha171" hexmask.long.byte 0x00 16.--23. 1. " RED171 ,Red171" hexmask.long.byte 0x00 8.--15. 1. " GREEN171 ,Green171" hexmask.long.byte 0x00 0.--7. 1. " BLUE171 ,Blue171" group.long 0x6B0++0x03 line.long 0x00 "FGCLUT172,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA172 ,Alpha172" hexmask.long.byte 0x00 16.--23. 1. " RED172 ,Red172" hexmask.long.byte 0x00 8.--15. 1. " GREEN172 ,Green172" hexmask.long.byte 0x00 0.--7. 1. " BLUE172 ,Blue172" group.long 0x6B4++0x03 line.long 0x00 "FGCLUT173,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA173 ,Alpha173" hexmask.long.byte 0x00 16.--23. 1. " RED173 ,Red173" hexmask.long.byte 0x00 8.--15. 1. " GREEN173 ,Green173" hexmask.long.byte 0x00 0.--7. 1. " BLUE173 ,Blue173" group.long 0x6B8++0x03 line.long 0x00 "FGCLUT174,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA174 ,Alpha174" hexmask.long.byte 0x00 16.--23. 1. " RED174 ,Red174" hexmask.long.byte 0x00 8.--15. 1. " GREEN174 ,Green174" hexmask.long.byte 0x00 0.--7. 1. " BLUE174 ,Blue174" group.long 0x6BC++0x03 line.long 0x00 "FGCLUT175,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA175 ,Alpha175" hexmask.long.byte 0x00 16.--23. 1. " RED175 ,Red175" hexmask.long.byte 0x00 8.--15. 1. " GREEN175 ,Green175" hexmask.long.byte 0x00 0.--7. 1. " BLUE175 ,Blue175" group.long 0x6C0++0x03 line.long 0x00 "FGCLUT176,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA176 ,Alpha176" hexmask.long.byte 0x00 16.--23. 1. " RED176 ,Red176" hexmask.long.byte 0x00 8.--15. 1. " GREEN176 ,Green176" hexmask.long.byte 0x00 0.--7. 1. " BLUE176 ,Blue176" group.long 0x6C4++0x03 line.long 0x00 "FGCLUT177,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA177 ,Alpha177" hexmask.long.byte 0x00 16.--23. 1. " RED177 ,Red177" hexmask.long.byte 0x00 8.--15. 1. " GREEN177 ,Green177" hexmask.long.byte 0x00 0.--7. 1. " BLUE177 ,Blue177" group.long 0x6C8++0x03 line.long 0x00 "FGCLUT178,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA178 ,Alpha178" hexmask.long.byte 0x00 16.--23. 1. " RED178 ,Red178" hexmask.long.byte 0x00 8.--15. 1. " GREEN178 ,Green178" hexmask.long.byte 0x00 0.--7. 1. " BLUE178 ,Blue178" group.long 0x6CC++0x03 line.long 0x00 "FGCLUT179,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA179 ,Alpha179" hexmask.long.byte 0x00 16.--23. 1. " RED179 ,Red179" hexmask.long.byte 0x00 8.--15. 1. " GREEN179 ,Green179" hexmask.long.byte 0x00 0.--7. 1. " BLUE179 ,Blue179" group.long 0x6D0++0x03 line.long 0x00 "FGCLUT180,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA180 ,Alpha180" hexmask.long.byte 0x00 16.--23. 1. " RED180 ,Red180" hexmask.long.byte 0x00 8.--15. 1. " GREEN180 ,Green180" hexmask.long.byte 0x00 0.--7. 1. " BLUE180 ,Blue180" group.long 0x6D4++0x03 line.long 0x00 "FGCLUT181,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA181 ,Alpha181" hexmask.long.byte 0x00 16.--23. 1. " RED181 ,Red181" hexmask.long.byte 0x00 8.--15. 1. " GREEN181 ,Green181" hexmask.long.byte 0x00 0.--7. 1. " BLUE181 ,Blue181" group.long 0x6D8++0x03 line.long 0x00 "FGCLUT182,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA182 ,Alpha182" hexmask.long.byte 0x00 16.--23. 1. " RED182 ,Red182" hexmask.long.byte 0x00 8.--15. 1. " GREEN182 ,Green182" hexmask.long.byte 0x00 0.--7. 1. " BLUE182 ,Blue182" group.long 0x6DC++0x03 line.long 0x00 "FGCLUT183,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA183 ,Alpha183" hexmask.long.byte 0x00 16.--23. 1. " RED183 ,Red183" hexmask.long.byte 0x00 8.--15. 1. " GREEN183 ,Green183" hexmask.long.byte 0x00 0.--7. 1. " BLUE183 ,Blue183" group.long 0x6E0++0x03 line.long 0x00 "FGCLUT184,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA184 ,Alpha184" hexmask.long.byte 0x00 16.--23. 1. " RED184 ,Red184" hexmask.long.byte 0x00 8.--15. 1. " GREEN184 ,Green184" hexmask.long.byte 0x00 0.--7. 1. " BLUE184 ,Blue184" group.long 0x6E4++0x03 line.long 0x00 "FGCLUT185,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA185 ,Alpha185" hexmask.long.byte 0x00 16.--23. 1. " RED185 ,Red185" hexmask.long.byte 0x00 8.--15. 1. " GREEN185 ,Green185" hexmask.long.byte 0x00 0.--7. 1. " BLUE185 ,Blue185" group.long 0x6E8++0x03 line.long 0x00 "FGCLUT186,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA186 ,Alpha186" hexmask.long.byte 0x00 16.--23. 1. " RED186 ,Red186" hexmask.long.byte 0x00 8.--15. 1. " GREEN186 ,Green186" hexmask.long.byte 0x00 0.--7. 1. " BLUE186 ,Blue186" group.long 0x6EC++0x03 line.long 0x00 "FGCLUT187,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA187 ,Alpha187" hexmask.long.byte 0x00 16.--23. 1. " RED187 ,Red187" hexmask.long.byte 0x00 8.--15. 1. " GREEN187 ,Green187" hexmask.long.byte 0x00 0.--7. 1. " BLUE187 ,Blue187" group.long 0x6F0++0x03 line.long 0x00 "FGCLUT188,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA188 ,Alpha188" hexmask.long.byte 0x00 16.--23. 1. " RED188 ,Red188" hexmask.long.byte 0x00 8.--15. 1. " GREEN188 ,Green188" hexmask.long.byte 0x00 0.--7. 1. " BLUE188 ,Blue188" group.long 0x6F4++0x03 line.long 0x00 "FGCLUT189,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA189 ,Alpha189" hexmask.long.byte 0x00 16.--23. 1. " RED189 ,Red189" hexmask.long.byte 0x00 8.--15. 1. " GREEN189 ,Green189" hexmask.long.byte 0x00 0.--7. 1. " BLUE189 ,Blue189" group.long 0x6F8++0x03 line.long 0x00 "FGCLUT190,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA190 ,Alpha190" hexmask.long.byte 0x00 16.--23. 1. " RED190 ,Red190" hexmask.long.byte 0x00 8.--15. 1. " GREEN190 ,Green190" hexmask.long.byte 0x00 0.--7. 1. " BLUE190 ,Blue190" group.long 0x6FC++0x03 line.long 0x00 "FGCLUT191,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA191 ,Alpha191" hexmask.long.byte 0x00 16.--23. 1. " RED191 ,Red191" hexmask.long.byte 0x00 8.--15. 1. " GREEN191 ,Green191" hexmask.long.byte 0x00 0.--7. 1. " BLUE191 ,Blue191" group.long 0x700++0x03 line.long 0x00 "FGCLUT192,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA192 ,Alpha192" hexmask.long.byte 0x00 16.--23. 1. " RED192 ,Red192" hexmask.long.byte 0x00 8.--15. 1. " GREEN192 ,Green192" hexmask.long.byte 0x00 0.--7. 1. " BLUE192 ,Blue192" group.long 0x704++0x03 line.long 0x00 "FGCLUT193,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA193 ,Alpha193" hexmask.long.byte 0x00 16.--23. 1. " RED193 ,Red193" hexmask.long.byte 0x00 8.--15. 1. " GREEN193 ,Green193" hexmask.long.byte 0x00 0.--7. 1. " BLUE193 ,Blue193" group.long 0x708++0x03 line.long 0x00 "FGCLUT194,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA194 ,Alpha194" hexmask.long.byte 0x00 16.--23. 1. " RED194 ,Red194" hexmask.long.byte 0x00 8.--15. 1. " GREEN194 ,Green194" hexmask.long.byte 0x00 0.--7. 1. " BLUE194 ,Blue194" group.long 0x70C++0x03 line.long 0x00 "FGCLUT195,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA195 ,Alpha195" hexmask.long.byte 0x00 16.--23. 1. " RED195 ,Red195" hexmask.long.byte 0x00 8.--15. 1. " GREEN195 ,Green195" hexmask.long.byte 0x00 0.--7. 1. " BLUE195 ,Blue195" group.long 0x710++0x03 line.long 0x00 "FGCLUT196,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA196 ,Alpha196" hexmask.long.byte 0x00 16.--23. 1. " RED196 ,Red196" hexmask.long.byte 0x00 8.--15. 1. " GREEN196 ,Green196" hexmask.long.byte 0x00 0.--7. 1. " BLUE196 ,Blue196" group.long 0x714++0x03 line.long 0x00 "FGCLUT197,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA197 ,Alpha197" hexmask.long.byte 0x00 16.--23. 1. " RED197 ,Red197" hexmask.long.byte 0x00 8.--15. 1. " GREEN197 ,Green197" hexmask.long.byte 0x00 0.--7. 1. " BLUE197 ,Blue197" group.long 0x718++0x03 line.long 0x00 "FGCLUT198,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA198 ,Alpha198" hexmask.long.byte 0x00 16.--23. 1. " RED198 ,Red198" hexmask.long.byte 0x00 8.--15. 1. " GREEN198 ,Green198" hexmask.long.byte 0x00 0.--7. 1. " BLUE198 ,Blue198" group.long 0x71C++0x03 line.long 0x00 "FGCLUT199,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA199 ,Alpha199" hexmask.long.byte 0x00 16.--23. 1. " RED199 ,Red199" hexmask.long.byte 0x00 8.--15. 1. " GREEN199 ,Green199" hexmask.long.byte 0x00 0.--7. 1. " BLUE199 ,Blue199" group.long 0x720++0x03 line.long 0x00 "FGCLUT200,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA200 ,Alpha200" hexmask.long.byte 0x00 16.--23. 1. " RED200 ,Red200" hexmask.long.byte 0x00 8.--15. 1. " GREEN200 ,Green200" hexmask.long.byte 0x00 0.--7. 1. " BLUE200 ,Blue200" group.long 0x724++0x03 line.long 0x00 "FGCLUT201,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA201 ,Alpha201" hexmask.long.byte 0x00 16.--23. 1. " RED201 ,Red201" hexmask.long.byte 0x00 8.--15. 1. " GREEN201 ,Green201" hexmask.long.byte 0x00 0.--7. 1. " BLUE201 ,Blue201" group.long 0x728++0x03 line.long 0x00 "FGCLUT202,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA202 ,Alpha202" hexmask.long.byte 0x00 16.--23. 1. " RED202 ,Red202" hexmask.long.byte 0x00 8.--15. 1. " GREEN202 ,Green202" hexmask.long.byte 0x00 0.--7. 1. " BLUE202 ,Blue202" group.long 0x72C++0x03 line.long 0x00 "FGCLUT203,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA203 ,Alpha203" hexmask.long.byte 0x00 16.--23. 1. " RED203 ,Red203" hexmask.long.byte 0x00 8.--15. 1. " GREEN203 ,Green203" hexmask.long.byte 0x00 0.--7. 1. " BLUE203 ,Blue203" group.long 0x730++0x03 line.long 0x00 "FGCLUT204,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA204 ,Alpha204" hexmask.long.byte 0x00 16.--23. 1. " RED204 ,Red204" hexmask.long.byte 0x00 8.--15. 1. " GREEN204 ,Green204" hexmask.long.byte 0x00 0.--7. 1. " BLUE204 ,Blue204" group.long 0x734++0x03 line.long 0x00 "FGCLUT205,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA205 ,Alpha205" hexmask.long.byte 0x00 16.--23. 1. " RED205 ,Red205" hexmask.long.byte 0x00 8.--15. 1. " GREEN205 ,Green205" hexmask.long.byte 0x00 0.--7. 1. " BLUE205 ,Blue205" group.long 0x738++0x03 line.long 0x00 "FGCLUT206,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA206 ,Alpha206" hexmask.long.byte 0x00 16.--23. 1. " RED206 ,Red206" hexmask.long.byte 0x00 8.--15. 1. " GREEN206 ,Green206" hexmask.long.byte 0x00 0.--7. 1. " BLUE206 ,Blue206" group.long 0x73C++0x03 line.long 0x00 "FGCLUT207,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA207 ,Alpha207" hexmask.long.byte 0x00 16.--23. 1. " RED207 ,Red207" hexmask.long.byte 0x00 8.--15. 1. " GREEN207 ,Green207" hexmask.long.byte 0x00 0.--7. 1. " BLUE207 ,Blue207" group.long 0x740++0x03 line.long 0x00 "FGCLUT208,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA208 ,Alpha208" hexmask.long.byte 0x00 16.--23. 1. " RED208 ,Red208" hexmask.long.byte 0x00 8.--15. 1. " GREEN208 ,Green208" hexmask.long.byte 0x00 0.--7. 1. " BLUE208 ,Blue208" group.long 0x744++0x03 line.long 0x00 "FGCLUT209,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA209 ,Alpha209" hexmask.long.byte 0x00 16.--23. 1. " RED209 ,Red209" hexmask.long.byte 0x00 8.--15. 1. " GREEN209 ,Green209" hexmask.long.byte 0x00 0.--7. 1. " BLUE209 ,Blue209" group.long 0x748++0x03 line.long 0x00 "FGCLUT210,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA210 ,Alpha210" hexmask.long.byte 0x00 16.--23. 1. " RED210 ,Red210" hexmask.long.byte 0x00 8.--15. 1. " GREEN210 ,Green210" hexmask.long.byte 0x00 0.--7. 1. " BLUE210 ,Blue210" group.long 0x74C++0x03 line.long 0x00 "FGCLUT211,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA211 ,Alpha211" hexmask.long.byte 0x00 16.--23. 1. " RED211 ,Red211" hexmask.long.byte 0x00 8.--15. 1. " GREEN211 ,Green211" hexmask.long.byte 0x00 0.--7. 1. " BLUE211 ,Blue211" group.long 0x750++0x03 line.long 0x00 "FGCLUT212,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA212 ,Alpha212" hexmask.long.byte 0x00 16.--23. 1. " RED212 ,Red212" hexmask.long.byte 0x00 8.--15. 1. " GREEN212 ,Green212" hexmask.long.byte 0x00 0.--7. 1. " BLUE212 ,Blue212" group.long 0x754++0x03 line.long 0x00 "FGCLUT213,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA213 ,Alpha213" hexmask.long.byte 0x00 16.--23. 1. " RED213 ,Red213" hexmask.long.byte 0x00 8.--15. 1. " GREEN213 ,Green213" hexmask.long.byte 0x00 0.--7. 1. " BLUE213 ,Blue213" group.long 0x758++0x03 line.long 0x00 "FGCLUT214,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA214 ,Alpha214" hexmask.long.byte 0x00 16.--23. 1. " RED214 ,Red214" hexmask.long.byte 0x00 8.--15. 1. " GREEN214 ,Green214" hexmask.long.byte 0x00 0.--7. 1. " BLUE214 ,Blue214" group.long 0x75C++0x03 line.long 0x00 "FGCLUT215,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA215 ,Alpha215" hexmask.long.byte 0x00 16.--23. 1. " RED215 ,Red215" hexmask.long.byte 0x00 8.--15. 1. " GREEN215 ,Green215" hexmask.long.byte 0x00 0.--7. 1. " BLUE215 ,Blue215" group.long 0x760++0x03 line.long 0x00 "FGCLUT216,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA216 ,Alpha216" hexmask.long.byte 0x00 16.--23. 1. " RED216 ,Red216" hexmask.long.byte 0x00 8.--15. 1. " GREEN216 ,Green216" hexmask.long.byte 0x00 0.--7. 1. " BLUE216 ,Blue216" group.long 0x764++0x03 line.long 0x00 "FGCLUT217,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA217 ,Alpha217" hexmask.long.byte 0x00 16.--23. 1. " RED217 ,Red217" hexmask.long.byte 0x00 8.--15. 1. " GREEN217 ,Green217" hexmask.long.byte 0x00 0.--7. 1. " BLUE217 ,Blue217" group.long 0x768++0x03 line.long 0x00 "FGCLUT218,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA218 ,Alpha218" hexmask.long.byte 0x00 16.--23. 1. " RED218 ,Red218" hexmask.long.byte 0x00 8.--15. 1. " GREEN218 ,Green218" hexmask.long.byte 0x00 0.--7. 1. " BLUE218 ,Blue218" group.long 0x76C++0x03 line.long 0x00 "FGCLUT219,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA219 ,Alpha219" hexmask.long.byte 0x00 16.--23. 1. " RED219 ,Red219" hexmask.long.byte 0x00 8.--15. 1. " GREEN219 ,Green219" hexmask.long.byte 0x00 0.--7. 1. " BLUE219 ,Blue219" group.long 0x770++0x03 line.long 0x00 "FGCLUT220,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA220 ,Alpha220" hexmask.long.byte 0x00 16.--23. 1. " RED220 ,Red220" hexmask.long.byte 0x00 8.--15. 1. " GREEN220 ,Green220" hexmask.long.byte 0x00 0.--7. 1. " BLUE220 ,Blue220" group.long 0x774++0x03 line.long 0x00 "FGCLUT221,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA221 ,Alpha221" hexmask.long.byte 0x00 16.--23. 1. " RED221 ,Red221" hexmask.long.byte 0x00 8.--15. 1. " GREEN221 ,Green221" hexmask.long.byte 0x00 0.--7. 1. " BLUE221 ,Blue221" group.long 0x778++0x03 line.long 0x00 "FGCLUT222,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA222 ,Alpha222" hexmask.long.byte 0x00 16.--23. 1. " RED222 ,Red222" hexmask.long.byte 0x00 8.--15. 1. " GREEN222 ,Green222" hexmask.long.byte 0x00 0.--7. 1. " BLUE222 ,Blue222" group.long 0x77C++0x03 line.long 0x00 "FGCLUT223,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA223 ,Alpha223" hexmask.long.byte 0x00 16.--23. 1. " RED223 ,Red223" hexmask.long.byte 0x00 8.--15. 1. " GREEN223 ,Green223" hexmask.long.byte 0x00 0.--7. 1. " BLUE223 ,Blue223" group.long 0x780++0x03 line.long 0x00 "FGCLUT224,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA224 ,Alpha224" hexmask.long.byte 0x00 16.--23. 1. " RED224 ,Red224" hexmask.long.byte 0x00 8.--15. 1. " GREEN224 ,Green224" hexmask.long.byte 0x00 0.--7. 1. " BLUE224 ,Blue224" group.long 0x784++0x03 line.long 0x00 "FGCLUT225,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA225 ,Alpha225" hexmask.long.byte 0x00 16.--23. 1. " RED225 ,Red225" hexmask.long.byte 0x00 8.--15. 1. " GREEN225 ,Green225" hexmask.long.byte 0x00 0.--7. 1. " BLUE225 ,Blue225" group.long 0x788++0x03 line.long 0x00 "FGCLUT226,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA226 ,Alpha226" hexmask.long.byte 0x00 16.--23. 1. " RED226 ,Red226" hexmask.long.byte 0x00 8.--15. 1. " GREEN226 ,Green226" hexmask.long.byte 0x00 0.--7. 1. " BLUE226 ,Blue226" group.long 0x78C++0x03 line.long 0x00 "FGCLUT227,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA227 ,Alpha227" hexmask.long.byte 0x00 16.--23. 1. " RED227 ,Red227" hexmask.long.byte 0x00 8.--15. 1. " GREEN227 ,Green227" hexmask.long.byte 0x00 0.--7. 1. " BLUE227 ,Blue227" group.long 0x790++0x03 line.long 0x00 "FGCLUT228,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA228 ,Alpha228" hexmask.long.byte 0x00 16.--23. 1. " RED228 ,Red228" hexmask.long.byte 0x00 8.--15. 1. " GREEN228 ,Green228" hexmask.long.byte 0x00 0.--7. 1. " BLUE228 ,Blue228" group.long 0x794++0x03 line.long 0x00 "FGCLUT229,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA229 ,Alpha229" hexmask.long.byte 0x00 16.--23. 1. " RED229 ,Red229" hexmask.long.byte 0x00 8.--15. 1. " GREEN229 ,Green229" hexmask.long.byte 0x00 0.--7. 1. " BLUE229 ,Blue229" group.long 0x798++0x03 line.long 0x00 "FGCLUT230,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA230 ,Alpha230" hexmask.long.byte 0x00 16.--23. 1. " RED230 ,Red230" hexmask.long.byte 0x00 8.--15. 1. " GREEN230 ,Green230" hexmask.long.byte 0x00 0.--7. 1. " BLUE230 ,Blue230" group.long 0x79C++0x03 line.long 0x00 "FGCLUT231,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA231 ,Alpha231" hexmask.long.byte 0x00 16.--23. 1. " RED231 ,Red231" hexmask.long.byte 0x00 8.--15. 1. " GREEN231 ,Green231" hexmask.long.byte 0x00 0.--7. 1. " BLUE231 ,Blue231" group.long 0x7A0++0x03 line.long 0x00 "FGCLUT232,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA232 ,Alpha232" hexmask.long.byte 0x00 16.--23. 1. " RED232 ,Red232" hexmask.long.byte 0x00 8.--15. 1. " GREEN232 ,Green232" hexmask.long.byte 0x00 0.--7. 1. " BLUE232 ,Blue232" group.long 0x7A4++0x03 line.long 0x00 "FGCLUT233,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA233 ,Alpha233" hexmask.long.byte 0x00 16.--23. 1. " RED233 ,Red233" hexmask.long.byte 0x00 8.--15. 1. " GREEN233 ,Green233" hexmask.long.byte 0x00 0.--7. 1. " BLUE233 ,Blue233" group.long 0x7A8++0x03 line.long 0x00 "FGCLUT234,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA234 ,Alpha234" hexmask.long.byte 0x00 16.--23. 1. " RED234 ,Red234" hexmask.long.byte 0x00 8.--15. 1. " GREEN234 ,Green234" hexmask.long.byte 0x00 0.--7. 1. " BLUE234 ,Blue234" group.long 0x7AC++0x03 line.long 0x00 "FGCLUT235,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA235 ,Alpha235" hexmask.long.byte 0x00 16.--23. 1. " RED235 ,Red235" hexmask.long.byte 0x00 8.--15. 1. " GREEN235 ,Green235" hexmask.long.byte 0x00 0.--7. 1. " BLUE235 ,Blue235" group.long 0x7B0++0x03 line.long 0x00 "FGCLUT236,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA236 ,Alpha236" hexmask.long.byte 0x00 16.--23. 1. " RED236 ,Red236" hexmask.long.byte 0x00 8.--15. 1. " GREEN236 ,Green236" hexmask.long.byte 0x00 0.--7. 1. " BLUE236 ,Blue236" group.long 0x7B4++0x03 line.long 0x00 "FGCLUT237,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA237 ,Alpha237" hexmask.long.byte 0x00 16.--23. 1. " RED237 ,Red237" hexmask.long.byte 0x00 8.--15. 1. " GREEN237 ,Green237" hexmask.long.byte 0x00 0.--7. 1. " BLUE237 ,Blue237" group.long 0x7B8++0x03 line.long 0x00 "FGCLUT238,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA238 ,Alpha238" hexmask.long.byte 0x00 16.--23. 1. " RED238 ,Red238" hexmask.long.byte 0x00 8.--15. 1. " GREEN238 ,Green238" hexmask.long.byte 0x00 0.--7. 1. " BLUE238 ,Blue238" group.long 0x7BC++0x03 line.long 0x00 "FGCLUT239,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA239 ,Alpha239" hexmask.long.byte 0x00 16.--23. 1. " RED239 ,Red239" hexmask.long.byte 0x00 8.--15. 1. " GREEN239 ,Green239" hexmask.long.byte 0x00 0.--7. 1. " BLUE239 ,Blue239" group.long 0x7C0++0x03 line.long 0x00 "FGCLUT240,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA240 ,Alpha240" hexmask.long.byte 0x00 16.--23. 1. " RED240 ,Red240" hexmask.long.byte 0x00 8.--15. 1. " GREEN240 ,Green240" hexmask.long.byte 0x00 0.--7. 1. " BLUE240 ,Blue240" group.long 0x7C4++0x03 line.long 0x00 "FGCLUT241,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA241 ,Alpha241" hexmask.long.byte 0x00 16.--23. 1. " RED241 ,Red241" hexmask.long.byte 0x00 8.--15. 1. " GREEN241 ,Green241" hexmask.long.byte 0x00 0.--7. 1. " BLUE241 ,Blue241" group.long 0x7C8++0x03 line.long 0x00 "FGCLUT242,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA242 ,Alpha242" hexmask.long.byte 0x00 16.--23. 1. " RED242 ,Red242" hexmask.long.byte 0x00 8.--15. 1. " GREEN242 ,Green242" hexmask.long.byte 0x00 0.--7. 1. " BLUE242 ,Blue242" group.long 0x7CC++0x03 line.long 0x00 "FGCLUT243,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA243 ,Alpha243" hexmask.long.byte 0x00 16.--23. 1. " RED243 ,Red243" hexmask.long.byte 0x00 8.--15. 1. " GREEN243 ,Green243" hexmask.long.byte 0x00 0.--7. 1. " BLUE243 ,Blue243" group.long 0x7D0++0x03 line.long 0x00 "FGCLUT244,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA244 ,Alpha244" hexmask.long.byte 0x00 16.--23. 1. " RED244 ,Red244" hexmask.long.byte 0x00 8.--15. 1. " GREEN244 ,Green244" hexmask.long.byte 0x00 0.--7. 1. " BLUE244 ,Blue244" group.long 0x7D4++0x03 line.long 0x00 "FGCLUT245,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA245 ,Alpha245" hexmask.long.byte 0x00 16.--23. 1. " RED245 ,Red245" hexmask.long.byte 0x00 8.--15. 1. " GREEN245 ,Green245" hexmask.long.byte 0x00 0.--7. 1. " BLUE245 ,Blue245" group.long 0x7D8++0x03 line.long 0x00 "FGCLUT246,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA246 ,Alpha246" hexmask.long.byte 0x00 16.--23. 1. " RED246 ,Red246" hexmask.long.byte 0x00 8.--15. 1. " GREEN246 ,Green246" hexmask.long.byte 0x00 0.--7. 1. " BLUE246 ,Blue246" group.long 0x7DC++0x03 line.long 0x00 "FGCLUT247,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA247 ,Alpha247" hexmask.long.byte 0x00 16.--23. 1. " RED247 ,Red247" hexmask.long.byte 0x00 8.--15. 1. " GREEN247 ,Green247" hexmask.long.byte 0x00 0.--7. 1. " BLUE247 ,Blue247" group.long 0x7E0++0x03 line.long 0x00 "FGCLUT248,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA248 ,Alpha248" hexmask.long.byte 0x00 16.--23. 1. " RED248 ,Red248" hexmask.long.byte 0x00 8.--15. 1. " GREEN248 ,Green248" hexmask.long.byte 0x00 0.--7. 1. " BLUE248 ,Blue248" group.long 0x7E4++0x03 line.long 0x00 "FGCLUT249,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA249 ,Alpha249" hexmask.long.byte 0x00 16.--23. 1. " RED249 ,Red249" hexmask.long.byte 0x00 8.--15. 1. " GREEN249 ,Green249" hexmask.long.byte 0x00 0.--7. 1. " BLUE249 ,Blue249" group.long 0x7E8++0x03 line.long 0x00 "FGCLUT250,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA250 ,Alpha250" hexmask.long.byte 0x00 16.--23. 1. " RED250 ,Red250" hexmask.long.byte 0x00 8.--15. 1. " GREEN250 ,Green250" hexmask.long.byte 0x00 0.--7. 1. " BLUE250 ,Blue250" group.long 0x7EC++0x03 line.long 0x00 "FGCLUT251,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA251 ,Alpha251" hexmask.long.byte 0x00 16.--23. 1. " RED251 ,Red251" hexmask.long.byte 0x00 8.--15. 1. " GREEN251 ,Green251" hexmask.long.byte 0x00 0.--7. 1. " BLUE251 ,Blue251" group.long 0x7F0++0x03 line.long 0x00 "FGCLUT252,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA252 ,Alpha252" hexmask.long.byte 0x00 16.--23. 1. " RED252 ,Red252" hexmask.long.byte 0x00 8.--15. 1. " GREEN252 ,Green252" hexmask.long.byte 0x00 0.--7. 1. " BLUE252 ,Blue252" group.long 0x7F4++0x03 line.long 0x00 "FGCLUT253,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA253 ,Alpha253" hexmask.long.byte 0x00 16.--23. 1. " RED253 ,Red253" hexmask.long.byte 0x00 8.--15. 1. " GREEN253 ,Green253" hexmask.long.byte 0x00 0.--7. 1. " BLUE253 ,Blue253" group.long 0x7F8++0x03 line.long 0x00 "FGCLUT254,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA254 ,Alpha254" hexmask.long.byte 0x00 16.--23. 1. " RED254 ,Red254" hexmask.long.byte 0x00 8.--15. 1. " GREEN254 ,Green254" hexmask.long.byte 0x00 0.--7. 1. " BLUE254 ,Blue254" group.long 0x7FC++0x03 line.long 0x00 "FGCLUT255,DMA2D Foreground CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA255 ,Alpha255" hexmask.long.byte 0x00 16.--23. 1. " RED255 ,Red255" hexmask.long.byte 0x00 8.--15. 1. " GREEN255 ,Green255" hexmask.long.byte 0x00 0.--7. 1. " BLUE255 ,Blue255" tree.end tree "DMA2D Background CLUT" group.long 0x800++0x03 line.long 0x00 "BGCLUT0 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA0 ,Alpha0 " hexmask.long.byte 0x00 16.--23. 1. " RED0 ,Red0 " hexmask.long.byte 0x00 8.--15. 1. " GREEN0 ,Green0 " hexmask.long.byte 0x00 0.--7. 1. " BLUE0 ,Blue0 " group.long 0x804++0x03 line.long 0x00 "BGCLUT1 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA1 ,Alpha1 " hexmask.long.byte 0x00 16.--23. 1. " RED1 ,Red1 " hexmask.long.byte 0x00 8.--15. 1. " GREEN1 ,Green1 " hexmask.long.byte 0x00 0.--7. 1. " BLUE1 ,Blue1 " group.long 0x808++0x03 line.long 0x00 "BGCLUT2 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA2 ,Alpha2 " hexmask.long.byte 0x00 16.--23. 1. " RED2 ,Red2 " hexmask.long.byte 0x00 8.--15. 1. " GREEN2 ,Green2 " hexmask.long.byte 0x00 0.--7. 1. " BLUE2 ,Blue2 " group.long 0x80C++0x03 line.long 0x00 "BGCLUT3 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA3 ,Alpha3 " hexmask.long.byte 0x00 16.--23. 1. " RED3 ,Red3 " hexmask.long.byte 0x00 8.--15. 1. " GREEN3 ,Green3 " hexmask.long.byte 0x00 0.--7. 1. " BLUE3 ,Blue3 " group.long 0x810++0x03 line.long 0x00 "BGCLUT4 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA4 ,Alpha4 " hexmask.long.byte 0x00 16.--23. 1. " RED4 ,Red4 " hexmask.long.byte 0x00 8.--15. 1. " GREEN4 ,Green4 " hexmask.long.byte 0x00 0.--7. 1. " BLUE4 ,Blue4 " group.long 0x814++0x03 line.long 0x00 "BGCLUT5 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA5 ,Alpha5 " hexmask.long.byte 0x00 16.--23. 1. " RED5 ,Red5 " hexmask.long.byte 0x00 8.--15. 1. " GREEN5 ,Green5 " hexmask.long.byte 0x00 0.--7. 1. " BLUE5 ,Blue5 " group.long 0x818++0x03 line.long 0x00 "BGCLUT6 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA6 ,Alpha6 " hexmask.long.byte 0x00 16.--23. 1. " RED6 ,Red6 " hexmask.long.byte 0x00 8.--15. 1. " GREEN6 ,Green6 " hexmask.long.byte 0x00 0.--7. 1. " BLUE6 ,Blue6 " group.long 0x81C++0x03 line.long 0x00 "BGCLUT7 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA7 ,Alpha7 " hexmask.long.byte 0x00 16.--23. 1. " RED7 ,Red7 " hexmask.long.byte 0x00 8.--15. 1. " GREEN7 ,Green7 " hexmask.long.byte 0x00 0.--7. 1. " BLUE7 ,Blue7 " group.long 0x820++0x03 line.long 0x00 "BGCLUT8 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA8 ,Alpha8 " hexmask.long.byte 0x00 16.--23. 1. " RED8 ,Red8 " hexmask.long.byte 0x00 8.--15. 1. " GREEN8 ,Green8 " hexmask.long.byte 0x00 0.--7. 1. " BLUE8 ,Blue8 " group.long 0x824++0x03 line.long 0x00 "BGCLUT9 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA9 ,Alpha9 " hexmask.long.byte 0x00 16.--23. 1. " RED9 ,Red9 " hexmask.long.byte 0x00 8.--15. 1. " GREEN9 ,Green9 " hexmask.long.byte 0x00 0.--7. 1. " BLUE9 ,Blue9 " group.long 0x828++0x03 line.long 0x00 "BGCLUT10 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA10 ,Alpha10 " hexmask.long.byte 0x00 16.--23. 1. " RED10 ,Red10 " hexmask.long.byte 0x00 8.--15. 1. " GREEN10 ,Green10 " hexmask.long.byte 0x00 0.--7. 1. " BLUE10 ,Blue10 " group.long 0x82C++0x03 line.long 0x00 "BGCLUT11 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA11 ,Alpha11 " hexmask.long.byte 0x00 16.--23. 1. " RED11 ,Red11 " hexmask.long.byte 0x00 8.--15. 1. " GREEN11 ,Green11 " hexmask.long.byte 0x00 0.--7. 1. " BLUE11 ,Blue11 " group.long 0x830++0x03 line.long 0x00 "BGCLUT12 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA12 ,Alpha12 " hexmask.long.byte 0x00 16.--23. 1. " RED12 ,Red12 " hexmask.long.byte 0x00 8.--15. 1. " GREEN12 ,Green12 " hexmask.long.byte 0x00 0.--7. 1. " BLUE12 ,Blue12 " group.long 0x834++0x03 line.long 0x00 "BGCLUT13 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA13 ,Alpha13 " hexmask.long.byte 0x00 16.--23. 1. " RED13 ,Red13 " hexmask.long.byte 0x00 8.--15. 1. " GREEN13 ,Green13 " hexmask.long.byte 0x00 0.--7. 1. " BLUE13 ,Blue13 " group.long 0x838++0x03 line.long 0x00 "BGCLUT14 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA14 ,Alpha14 " hexmask.long.byte 0x00 16.--23. 1. " RED14 ,Red14 " hexmask.long.byte 0x00 8.--15. 1. " GREEN14 ,Green14 " hexmask.long.byte 0x00 0.--7. 1. " BLUE14 ,Blue14 " group.long 0x83C++0x03 line.long 0x00 "BGCLUT15 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA15 ,Alpha15 " hexmask.long.byte 0x00 16.--23. 1. " RED15 ,Red15 " hexmask.long.byte 0x00 8.--15. 1. " GREEN15 ,Green15 " hexmask.long.byte 0x00 0.--7. 1. " BLUE15 ,Blue15 " group.long 0x840++0x03 line.long 0x00 "BGCLUT16 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA16 ,Alpha16 " hexmask.long.byte 0x00 16.--23. 1. " RED16 ,Red16 " hexmask.long.byte 0x00 8.--15. 1. " GREEN16 ,Green16 " hexmask.long.byte 0x00 0.--7. 1. " BLUE16 ,Blue16 " group.long 0x844++0x03 line.long 0x00 "BGCLUT17 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA17 ,Alpha17 " hexmask.long.byte 0x00 16.--23. 1. " RED17 ,Red17 " hexmask.long.byte 0x00 8.--15. 1. " GREEN17 ,Green17 " hexmask.long.byte 0x00 0.--7. 1. " BLUE17 ,Blue17 " group.long 0x848++0x03 line.long 0x00 "BGCLUT18 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA18 ,Alpha18 " hexmask.long.byte 0x00 16.--23. 1. " RED18 ,Red18 " hexmask.long.byte 0x00 8.--15. 1. " GREEN18 ,Green18 " hexmask.long.byte 0x00 0.--7. 1. " BLUE18 ,Blue18 " group.long 0x84C++0x03 line.long 0x00 "BGCLUT19 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA19 ,Alpha19 " hexmask.long.byte 0x00 16.--23. 1. " RED19 ,Red19 " hexmask.long.byte 0x00 8.--15. 1. " GREEN19 ,Green19 " hexmask.long.byte 0x00 0.--7. 1. " BLUE19 ,Blue19 " group.long 0x850++0x03 line.long 0x00 "BGCLUT20 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA20 ,Alpha20 " hexmask.long.byte 0x00 16.--23. 1. " RED20 ,Red20 " hexmask.long.byte 0x00 8.--15. 1. " GREEN20 ,Green20 " hexmask.long.byte 0x00 0.--7. 1. " BLUE20 ,Blue20 " group.long 0x854++0x03 line.long 0x00 "BGCLUT21 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA21 ,Alpha21 " hexmask.long.byte 0x00 16.--23. 1. " RED21 ,Red21 " hexmask.long.byte 0x00 8.--15. 1. " GREEN21 ,Green21 " hexmask.long.byte 0x00 0.--7. 1. " BLUE21 ,Blue21 " group.long 0x858++0x03 line.long 0x00 "BGCLUT22 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA22 ,Alpha22 " hexmask.long.byte 0x00 16.--23. 1. " RED22 ,Red22 " hexmask.long.byte 0x00 8.--15. 1. " GREEN22 ,Green22 " hexmask.long.byte 0x00 0.--7. 1. " BLUE22 ,Blue22 " group.long 0x85C++0x03 line.long 0x00 "BGCLUT23 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA23 ,Alpha23 " hexmask.long.byte 0x00 16.--23. 1. " RED23 ,Red23 " hexmask.long.byte 0x00 8.--15. 1. " GREEN23 ,Green23 " hexmask.long.byte 0x00 0.--7. 1. " BLUE23 ,Blue23 " group.long 0x860++0x03 line.long 0x00 "BGCLUT24 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA24 ,Alpha24 " hexmask.long.byte 0x00 16.--23. 1. " RED24 ,Red24 " hexmask.long.byte 0x00 8.--15. 1. " GREEN24 ,Green24 " hexmask.long.byte 0x00 0.--7. 1. " BLUE24 ,Blue24 " group.long 0x864++0x03 line.long 0x00 "BGCLUT25 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA25 ,Alpha25 " hexmask.long.byte 0x00 16.--23. 1. " RED25 ,Red25 " hexmask.long.byte 0x00 8.--15. 1. " GREEN25 ,Green25 " hexmask.long.byte 0x00 0.--7. 1. " BLUE25 ,Blue25 " group.long 0x868++0x03 line.long 0x00 "BGCLUT26 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA26 ,Alpha26 " hexmask.long.byte 0x00 16.--23. 1. " RED26 ,Red26 " hexmask.long.byte 0x00 8.--15. 1. " GREEN26 ,Green26 " hexmask.long.byte 0x00 0.--7. 1. " BLUE26 ,Blue26 " group.long 0x86C++0x03 line.long 0x00 "BGCLUT27 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA27 ,Alpha27 " hexmask.long.byte 0x00 16.--23. 1. " RED27 ,Red27 " hexmask.long.byte 0x00 8.--15. 1. " GREEN27 ,Green27 " hexmask.long.byte 0x00 0.--7. 1. " BLUE27 ,Blue27 " group.long 0x870++0x03 line.long 0x00 "BGCLUT28 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA28 ,Alpha28 " hexmask.long.byte 0x00 16.--23. 1. " RED28 ,Red28 " hexmask.long.byte 0x00 8.--15. 1. " GREEN28 ,Green28 " hexmask.long.byte 0x00 0.--7. 1. " BLUE28 ,Blue28 " group.long 0x874++0x03 line.long 0x00 "BGCLUT29 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA29 ,Alpha29 " hexmask.long.byte 0x00 16.--23. 1. " RED29 ,Red29 " hexmask.long.byte 0x00 8.--15. 1. " GREEN29 ,Green29 " hexmask.long.byte 0x00 0.--7. 1. " BLUE29 ,Blue29 " group.long 0x878++0x03 line.long 0x00 "BGCLUT30 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA30 ,Alpha30 " hexmask.long.byte 0x00 16.--23. 1. " RED30 ,Red30 " hexmask.long.byte 0x00 8.--15. 1. " GREEN30 ,Green30 " hexmask.long.byte 0x00 0.--7. 1. " BLUE30 ,Blue30 " group.long 0x87C++0x03 line.long 0x00 "BGCLUT31 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA31 ,Alpha31 " hexmask.long.byte 0x00 16.--23. 1. " RED31 ,Red31 " hexmask.long.byte 0x00 8.--15. 1. " GREEN31 ,Green31 " hexmask.long.byte 0x00 0.--7. 1. " BLUE31 ,Blue31 " group.long 0x880++0x03 line.long 0x00 "BGCLUT32 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA32 ,Alpha32 " hexmask.long.byte 0x00 16.--23. 1. " RED32 ,Red32 " hexmask.long.byte 0x00 8.--15. 1. " GREEN32 ,Green32 " hexmask.long.byte 0x00 0.--7. 1. " BLUE32 ,Blue32 " group.long 0x884++0x03 line.long 0x00 "BGCLUT33 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA33 ,Alpha33 " hexmask.long.byte 0x00 16.--23. 1. " RED33 ,Red33 " hexmask.long.byte 0x00 8.--15. 1. " GREEN33 ,Green33 " hexmask.long.byte 0x00 0.--7. 1. " BLUE33 ,Blue33 " group.long 0x888++0x03 line.long 0x00 "BGCLUT34 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA34 ,Alpha34 " hexmask.long.byte 0x00 16.--23. 1. " RED34 ,Red34 " hexmask.long.byte 0x00 8.--15. 1. " GREEN34 ,Green34 " hexmask.long.byte 0x00 0.--7. 1. " BLUE34 ,Blue34 " group.long 0x88C++0x03 line.long 0x00 "BGCLUT35 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA35 ,Alpha35 " hexmask.long.byte 0x00 16.--23. 1. " RED35 ,Red35 " hexmask.long.byte 0x00 8.--15. 1. " GREEN35 ,Green35 " hexmask.long.byte 0x00 0.--7. 1. " BLUE35 ,Blue35 " group.long 0x890++0x03 line.long 0x00 "BGCLUT36 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA36 ,Alpha36 " hexmask.long.byte 0x00 16.--23. 1. " RED36 ,Red36 " hexmask.long.byte 0x00 8.--15. 1. " GREEN36 ,Green36 " hexmask.long.byte 0x00 0.--7. 1. " BLUE36 ,Blue36 " group.long 0x894++0x03 line.long 0x00 "BGCLUT37 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA37 ,Alpha37 " hexmask.long.byte 0x00 16.--23. 1. " RED37 ,Red37 " hexmask.long.byte 0x00 8.--15. 1. " GREEN37 ,Green37 " hexmask.long.byte 0x00 0.--7. 1. " BLUE37 ,Blue37 " group.long 0x898++0x03 line.long 0x00 "BGCLUT38 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA38 ,Alpha38 " hexmask.long.byte 0x00 16.--23. 1. " RED38 ,Red38 " hexmask.long.byte 0x00 8.--15. 1. " GREEN38 ,Green38 " hexmask.long.byte 0x00 0.--7. 1. " BLUE38 ,Blue38 " group.long 0x89C++0x03 line.long 0x00 "BGCLUT39 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA39 ,Alpha39 " hexmask.long.byte 0x00 16.--23. 1. " RED39 ,Red39 " hexmask.long.byte 0x00 8.--15. 1. " GREEN39 ,Green39 " hexmask.long.byte 0x00 0.--7. 1. " BLUE39 ,Blue39 " group.long 0x8A0++0x03 line.long 0x00 "BGCLUT40 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA40 ,Alpha40 " hexmask.long.byte 0x00 16.--23. 1. " RED40 ,Red40 " hexmask.long.byte 0x00 8.--15. 1. " GREEN40 ,Green40 " hexmask.long.byte 0x00 0.--7. 1. " BLUE40 ,Blue40 " group.long 0x8A4++0x03 line.long 0x00 "BGCLUT41 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA41 ,Alpha41 " hexmask.long.byte 0x00 16.--23. 1. " RED41 ,Red41 " hexmask.long.byte 0x00 8.--15. 1. " GREEN41 ,Green41 " hexmask.long.byte 0x00 0.--7. 1. " BLUE41 ,Blue41 " group.long 0x8A8++0x03 line.long 0x00 "BGCLUT42 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA42 ,Alpha42 " hexmask.long.byte 0x00 16.--23. 1. " RED42 ,Red42 " hexmask.long.byte 0x00 8.--15. 1. " GREEN42 ,Green42 " hexmask.long.byte 0x00 0.--7. 1. " BLUE42 ,Blue42 " group.long 0x8AC++0x03 line.long 0x00 "BGCLUT43 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA43 ,Alpha43 " hexmask.long.byte 0x00 16.--23. 1. " RED43 ,Red43 " hexmask.long.byte 0x00 8.--15. 1. " GREEN43 ,Green43 " hexmask.long.byte 0x00 0.--7. 1. " BLUE43 ,Blue43 " group.long 0x8B0++0x03 line.long 0x00 "BGCLUT44 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA44 ,Alpha44 " hexmask.long.byte 0x00 16.--23. 1. " RED44 ,Red44 " hexmask.long.byte 0x00 8.--15. 1. " GREEN44 ,Green44 " hexmask.long.byte 0x00 0.--7. 1. " BLUE44 ,Blue44 " group.long 0x8B4++0x03 line.long 0x00 "BGCLUT45 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA45 ,Alpha45 " hexmask.long.byte 0x00 16.--23. 1. " RED45 ,Red45 " hexmask.long.byte 0x00 8.--15. 1. " GREEN45 ,Green45 " hexmask.long.byte 0x00 0.--7. 1. " BLUE45 ,Blue45 " group.long 0x8B8++0x03 line.long 0x00 "BGCLUT46 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA46 ,Alpha46 " hexmask.long.byte 0x00 16.--23. 1. " RED46 ,Red46 " hexmask.long.byte 0x00 8.--15. 1. " GREEN46 ,Green46 " hexmask.long.byte 0x00 0.--7. 1. " BLUE46 ,Blue46 " group.long 0x8BC++0x03 line.long 0x00 "BGCLUT47 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA47 ,Alpha47 " hexmask.long.byte 0x00 16.--23. 1. " RED47 ,Red47 " hexmask.long.byte 0x00 8.--15. 1. " GREEN47 ,Green47 " hexmask.long.byte 0x00 0.--7. 1. " BLUE47 ,Blue47 " group.long 0x8C0++0x03 line.long 0x00 "BGCLUT48 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA48 ,Alpha48 " hexmask.long.byte 0x00 16.--23. 1. " RED48 ,Red48 " hexmask.long.byte 0x00 8.--15. 1. " GREEN48 ,Green48 " hexmask.long.byte 0x00 0.--7. 1. " BLUE48 ,Blue48 " group.long 0x8C4++0x03 line.long 0x00 "BGCLUT49 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA49 ,Alpha49 " hexmask.long.byte 0x00 16.--23. 1. " RED49 ,Red49 " hexmask.long.byte 0x00 8.--15. 1. " GREEN49 ,Green49 " hexmask.long.byte 0x00 0.--7. 1. " BLUE49 ,Blue49 " group.long 0x8C8++0x03 line.long 0x00 "BGCLUT50 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA50 ,Alpha50 " hexmask.long.byte 0x00 16.--23. 1. " RED50 ,Red50 " hexmask.long.byte 0x00 8.--15. 1. " GREEN50 ,Green50 " hexmask.long.byte 0x00 0.--7. 1. " BLUE50 ,Blue50 " group.long 0x8CC++0x03 line.long 0x00 "BGCLUT51 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA51 ,Alpha51 " hexmask.long.byte 0x00 16.--23. 1. " RED51 ,Red51 " hexmask.long.byte 0x00 8.--15. 1. " GREEN51 ,Green51 " hexmask.long.byte 0x00 0.--7. 1. " BLUE51 ,Blue51 " group.long 0x8D0++0x03 line.long 0x00 "BGCLUT52 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA52 ,Alpha52 " hexmask.long.byte 0x00 16.--23. 1. " RED52 ,Red52 " hexmask.long.byte 0x00 8.--15. 1. " GREEN52 ,Green52 " hexmask.long.byte 0x00 0.--7. 1. " BLUE52 ,Blue52 " group.long 0x8D4++0x03 line.long 0x00 "BGCLUT53 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA53 ,Alpha53 " hexmask.long.byte 0x00 16.--23. 1. " RED53 ,Red53 " hexmask.long.byte 0x00 8.--15. 1. " GREEN53 ,Green53 " hexmask.long.byte 0x00 0.--7. 1. " BLUE53 ,Blue53 " group.long 0x8D8++0x03 line.long 0x00 "BGCLUT54 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA54 ,Alpha54 " hexmask.long.byte 0x00 16.--23. 1. " RED54 ,Red54 " hexmask.long.byte 0x00 8.--15. 1. " GREEN54 ,Green54 " hexmask.long.byte 0x00 0.--7. 1. " BLUE54 ,Blue54 " group.long 0x8DC++0x03 line.long 0x00 "BGCLUT55 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA55 ,Alpha55 " hexmask.long.byte 0x00 16.--23. 1. " RED55 ,Red55 " hexmask.long.byte 0x00 8.--15. 1. " GREEN55 ,Green55 " hexmask.long.byte 0x00 0.--7. 1. " BLUE55 ,Blue55 " group.long 0x8E0++0x03 line.long 0x00 "BGCLUT56 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA56 ,Alpha56 " hexmask.long.byte 0x00 16.--23. 1. " RED56 ,Red56 " hexmask.long.byte 0x00 8.--15. 1. " GREEN56 ,Green56 " hexmask.long.byte 0x00 0.--7. 1. " BLUE56 ,Blue56 " group.long 0x8E4++0x03 line.long 0x00 "BGCLUT57 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA57 ,Alpha57 " hexmask.long.byte 0x00 16.--23. 1. " RED57 ,Red57 " hexmask.long.byte 0x00 8.--15. 1. " GREEN57 ,Green57 " hexmask.long.byte 0x00 0.--7. 1. " BLUE57 ,Blue57 " group.long 0x8E8++0x03 line.long 0x00 "BGCLUT58 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA58 ,Alpha58 " hexmask.long.byte 0x00 16.--23. 1. " RED58 ,Red58 " hexmask.long.byte 0x00 8.--15. 1. " GREEN58 ,Green58 " hexmask.long.byte 0x00 0.--7. 1. " BLUE58 ,Blue58 " group.long 0x8EC++0x03 line.long 0x00 "BGCLUT59 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA59 ,Alpha59 " hexmask.long.byte 0x00 16.--23. 1. " RED59 ,Red59 " hexmask.long.byte 0x00 8.--15. 1. " GREEN59 ,Green59 " hexmask.long.byte 0x00 0.--7. 1. " BLUE59 ,Blue59 " group.long 0x8F0++0x03 line.long 0x00 "BGCLUT60 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA60 ,Alpha60 " hexmask.long.byte 0x00 16.--23. 1. " RED60 ,Red60 " hexmask.long.byte 0x00 8.--15. 1. " GREEN60 ,Green60 " hexmask.long.byte 0x00 0.--7. 1. " BLUE60 ,Blue60 " group.long 0x8F4++0x03 line.long 0x00 "BGCLUT61 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA61 ,Alpha61 " hexmask.long.byte 0x00 16.--23. 1. " RED61 ,Red61 " hexmask.long.byte 0x00 8.--15. 1. " GREEN61 ,Green61 " hexmask.long.byte 0x00 0.--7. 1. " BLUE61 ,Blue61 " group.long 0x8F8++0x03 line.long 0x00 "BGCLUT62 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA62 ,Alpha62 " hexmask.long.byte 0x00 16.--23. 1. " RED62 ,Red62 " hexmask.long.byte 0x00 8.--15. 1. " GREEN62 ,Green62 " hexmask.long.byte 0x00 0.--7. 1. " BLUE62 ,Blue62 " group.long 0x8FC++0x03 line.long 0x00 "BGCLUT63 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA63 ,Alpha63 " hexmask.long.byte 0x00 16.--23. 1. " RED63 ,Red63 " hexmask.long.byte 0x00 8.--15. 1. " GREEN63 ,Green63 " hexmask.long.byte 0x00 0.--7. 1. " BLUE63 ,Blue63 " group.long 0x900++0x03 line.long 0x00 "BGCLUT64 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA64 ,Alpha64 " hexmask.long.byte 0x00 16.--23. 1. " RED64 ,Red64 " hexmask.long.byte 0x00 8.--15. 1. " GREEN64 ,Green64 " hexmask.long.byte 0x00 0.--7. 1. " BLUE64 ,Blue64 " group.long 0x904++0x03 line.long 0x00 "BGCLUT65 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA65 ,Alpha65 " hexmask.long.byte 0x00 16.--23. 1. " RED65 ,Red65 " hexmask.long.byte 0x00 8.--15. 1. " GREEN65 ,Green65 " hexmask.long.byte 0x00 0.--7. 1. " BLUE65 ,Blue65 " group.long 0x908++0x03 line.long 0x00 "BGCLUT66 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA66 ,Alpha66 " hexmask.long.byte 0x00 16.--23. 1. " RED66 ,Red66 " hexmask.long.byte 0x00 8.--15. 1. " GREEN66 ,Green66 " hexmask.long.byte 0x00 0.--7. 1. " BLUE66 ,Blue66 " group.long 0x90C++0x03 line.long 0x00 "BGCLUT67 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA67 ,Alpha67 " hexmask.long.byte 0x00 16.--23. 1. " RED67 ,Red67 " hexmask.long.byte 0x00 8.--15. 1. " GREEN67 ,Green67 " hexmask.long.byte 0x00 0.--7. 1. " BLUE67 ,Blue67 " group.long 0x910++0x03 line.long 0x00 "BGCLUT68 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA68 ,Alpha68 " hexmask.long.byte 0x00 16.--23. 1. " RED68 ,Red68 " hexmask.long.byte 0x00 8.--15. 1. " GREEN68 ,Green68 " hexmask.long.byte 0x00 0.--7. 1. " BLUE68 ,Blue68 " group.long 0x914++0x03 line.long 0x00 "BGCLUT69 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA69 ,Alpha69 " hexmask.long.byte 0x00 16.--23. 1. " RED69 ,Red69 " hexmask.long.byte 0x00 8.--15. 1. " GREEN69 ,Green69 " hexmask.long.byte 0x00 0.--7. 1. " BLUE69 ,Blue69 " group.long 0x918++0x03 line.long 0x00 "BGCLUT70 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA70 ,Alpha70 " hexmask.long.byte 0x00 16.--23. 1. " RED70 ,Red70 " hexmask.long.byte 0x00 8.--15. 1. " GREEN70 ,Green70 " hexmask.long.byte 0x00 0.--7. 1. " BLUE70 ,Blue70 " group.long 0x91C++0x03 line.long 0x00 "BGCLUT71 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA71 ,Alpha71 " hexmask.long.byte 0x00 16.--23. 1. " RED71 ,Red71 " hexmask.long.byte 0x00 8.--15. 1. " GREEN71 ,Green71 " hexmask.long.byte 0x00 0.--7. 1. " BLUE71 ,Blue71 " group.long 0x920++0x03 line.long 0x00 "BGCLUT72 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA72 ,Alpha72 " hexmask.long.byte 0x00 16.--23. 1. " RED72 ,Red72 " hexmask.long.byte 0x00 8.--15. 1. " GREEN72 ,Green72 " hexmask.long.byte 0x00 0.--7. 1. " BLUE72 ,Blue72 " group.long 0x924++0x03 line.long 0x00 "BGCLUT73 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA73 ,Alpha73 " hexmask.long.byte 0x00 16.--23. 1. " RED73 ,Red73 " hexmask.long.byte 0x00 8.--15. 1. " GREEN73 ,Green73 " hexmask.long.byte 0x00 0.--7. 1. " BLUE73 ,Blue73 " group.long 0x928++0x03 line.long 0x00 "BGCLUT74 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA74 ,Alpha74 " hexmask.long.byte 0x00 16.--23. 1. " RED74 ,Red74 " hexmask.long.byte 0x00 8.--15. 1. " GREEN74 ,Green74 " hexmask.long.byte 0x00 0.--7. 1. " BLUE74 ,Blue74 " group.long 0x92C++0x03 line.long 0x00 "BGCLUT75 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA75 ,Alpha75 " hexmask.long.byte 0x00 16.--23. 1. " RED75 ,Red75 " hexmask.long.byte 0x00 8.--15. 1. " GREEN75 ,Green75 " hexmask.long.byte 0x00 0.--7. 1. " BLUE75 ,Blue75 " group.long 0x930++0x03 line.long 0x00 "BGCLUT76 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA76 ,Alpha76 " hexmask.long.byte 0x00 16.--23. 1. " RED76 ,Red76 " hexmask.long.byte 0x00 8.--15. 1. " GREEN76 ,Green76 " hexmask.long.byte 0x00 0.--7. 1. " BLUE76 ,Blue76 " group.long 0x934++0x03 line.long 0x00 "BGCLUT77 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA77 ,Alpha77 " hexmask.long.byte 0x00 16.--23. 1. " RED77 ,Red77 " hexmask.long.byte 0x00 8.--15. 1. " GREEN77 ,Green77 " hexmask.long.byte 0x00 0.--7. 1. " BLUE77 ,Blue77 " group.long 0x938++0x03 line.long 0x00 "BGCLUT78 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA78 ,Alpha78 " hexmask.long.byte 0x00 16.--23. 1. " RED78 ,Red78 " hexmask.long.byte 0x00 8.--15. 1. " GREEN78 ,Green78 " hexmask.long.byte 0x00 0.--7. 1. " BLUE78 ,Blue78 " group.long 0x93C++0x03 line.long 0x00 "BGCLUT79 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA79 ,Alpha79 " hexmask.long.byte 0x00 16.--23. 1. " RED79 ,Red79 " hexmask.long.byte 0x00 8.--15. 1. " GREEN79 ,Green79 " hexmask.long.byte 0x00 0.--7. 1. " BLUE79 ,Blue79 " group.long 0x940++0x03 line.long 0x00 "BGCLUT80 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA80 ,Alpha80 " hexmask.long.byte 0x00 16.--23. 1. " RED80 ,Red80 " hexmask.long.byte 0x00 8.--15. 1. " GREEN80 ,Green80 " hexmask.long.byte 0x00 0.--7. 1. " BLUE80 ,Blue80 " group.long 0x944++0x03 line.long 0x00 "BGCLUT81 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA81 ,Alpha81 " hexmask.long.byte 0x00 16.--23. 1. " RED81 ,Red81 " hexmask.long.byte 0x00 8.--15. 1. " GREEN81 ,Green81 " hexmask.long.byte 0x00 0.--7. 1. " BLUE81 ,Blue81 " group.long 0x948++0x03 line.long 0x00 "BGCLUT82 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA82 ,Alpha82 " hexmask.long.byte 0x00 16.--23. 1. " RED82 ,Red82 " hexmask.long.byte 0x00 8.--15. 1. " GREEN82 ,Green82 " hexmask.long.byte 0x00 0.--7. 1. " BLUE82 ,Blue82 " group.long 0x94C++0x03 line.long 0x00 "BGCLUT83 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA83 ,Alpha83 " hexmask.long.byte 0x00 16.--23. 1. " RED83 ,Red83 " hexmask.long.byte 0x00 8.--15. 1. " GREEN83 ,Green83 " hexmask.long.byte 0x00 0.--7. 1. " BLUE83 ,Blue83 " group.long 0x950++0x03 line.long 0x00 "BGCLUT84 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA84 ,Alpha84 " hexmask.long.byte 0x00 16.--23. 1. " RED84 ,Red84 " hexmask.long.byte 0x00 8.--15. 1. " GREEN84 ,Green84 " hexmask.long.byte 0x00 0.--7. 1. " BLUE84 ,Blue84 " group.long 0x954++0x03 line.long 0x00 "BGCLUT85 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA85 ,Alpha85 " hexmask.long.byte 0x00 16.--23. 1. " RED85 ,Red85 " hexmask.long.byte 0x00 8.--15. 1. " GREEN85 ,Green85 " hexmask.long.byte 0x00 0.--7. 1. " BLUE85 ,Blue85 " group.long 0x958++0x03 line.long 0x00 "BGCLUT86 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA86 ,Alpha86 " hexmask.long.byte 0x00 16.--23. 1. " RED86 ,Red86 " hexmask.long.byte 0x00 8.--15. 1. " GREEN86 ,Green86 " hexmask.long.byte 0x00 0.--7. 1. " BLUE86 ,Blue86 " group.long 0x95C++0x03 line.long 0x00 "BGCLUT87 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA87 ,Alpha87 " hexmask.long.byte 0x00 16.--23. 1. " RED87 ,Red87 " hexmask.long.byte 0x00 8.--15. 1. " GREEN87 ,Green87 " hexmask.long.byte 0x00 0.--7. 1. " BLUE87 ,Blue87 " group.long 0x960++0x03 line.long 0x00 "BGCLUT88 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA88 ,Alpha88 " hexmask.long.byte 0x00 16.--23. 1. " RED88 ,Red88 " hexmask.long.byte 0x00 8.--15. 1. " GREEN88 ,Green88 " hexmask.long.byte 0x00 0.--7. 1. " BLUE88 ,Blue88 " group.long 0x964++0x03 line.long 0x00 "BGCLUT89 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA89 ,Alpha89 " hexmask.long.byte 0x00 16.--23. 1. " RED89 ,Red89 " hexmask.long.byte 0x00 8.--15. 1. " GREEN89 ,Green89 " hexmask.long.byte 0x00 0.--7. 1. " BLUE89 ,Blue89 " group.long 0x968++0x03 line.long 0x00 "BGCLUT90 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA90 ,Alpha90 " hexmask.long.byte 0x00 16.--23. 1. " RED90 ,Red90 " hexmask.long.byte 0x00 8.--15. 1. " GREEN90 ,Green90 " hexmask.long.byte 0x00 0.--7. 1. " BLUE90 ,Blue90 " group.long 0x96C++0x03 line.long 0x00 "BGCLUT91 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA91 ,Alpha91 " hexmask.long.byte 0x00 16.--23. 1. " RED91 ,Red91 " hexmask.long.byte 0x00 8.--15. 1. " GREEN91 ,Green91 " hexmask.long.byte 0x00 0.--7. 1. " BLUE91 ,Blue91 " group.long 0x970++0x03 line.long 0x00 "BGCLUT92 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA92 ,Alpha92 " hexmask.long.byte 0x00 16.--23. 1. " RED92 ,Red92 " hexmask.long.byte 0x00 8.--15. 1. " GREEN92 ,Green92 " hexmask.long.byte 0x00 0.--7. 1. " BLUE92 ,Blue92 " group.long 0x974++0x03 line.long 0x00 "BGCLUT93 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA93 ,Alpha93 " hexmask.long.byte 0x00 16.--23. 1. " RED93 ,Red93 " hexmask.long.byte 0x00 8.--15. 1. " GREEN93 ,Green93 " hexmask.long.byte 0x00 0.--7. 1. " BLUE93 ,Blue93 " group.long 0x978++0x03 line.long 0x00 "BGCLUT94 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA94 ,Alpha94 " hexmask.long.byte 0x00 16.--23. 1. " RED94 ,Red94 " hexmask.long.byte 0x00 8.--15. 1. " GREEN94 ,Green94 " hexmask.long.byte 0x00 0.--7. 1. " BLUE94 ,Blue94 " group.long 0x97C++0x03 line.long 0x00 "BGCLUT95 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA95 ,Alpha95 " hexmask.long.byte 0x00 16.--23. 1. " RED95 ,Red95 " hexmask.long.byte 0x00 8.--15. 1. " GREEN95 ,Green95 " hexmask.long.byte 0x00 0.--7. 1. " BLUE95 ,Blue95 " group.long 0x980++0x03 line.long 0x00 "BGCLUT96 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA96 ,Alpha96 " hexmask.long.byte 0x00 16.--23. 1. " RED96 ,Red96 " hexmask.long.byte 0x00 8.--15. 1. " GREEN96 ,Green96 " hexmask.long.byte 0x00 0.--7. 1. " BLUE96 ,Blue96 " group.long 0x984++0x03 line.long 0x00 "BGCLUT97 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA97 ,Alpha97 " hexmask.long.byte 0x00 16.--23. 1. " RED97 ,Red97 " hexmask.long.byte 0x00 8.--15. 1. " GREEN97 ,Green97 " hexmask.long.byte 0x00 0.--7. 1. " BLUE97 ,Blue97 " group.long 0x988++0x03 line.long 0x00 "BGCLUT98 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA98 ,Alpha98 " hexmask.long.byte 0x00 16.--23. 1. " RED98 ,Red98 " hexmask.long.byte 0x00 8.--15. 1. " GREEN98 ,Green98 " hexmask.long.byte 0x00 0.--7. 1. " BLUE98 ,Blue98 " group.long 0x98C++0x03 line.long 0x00 "BGCLUT99 ,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA99 ,Alpha99 " hexmask.long.byte 0x00 16.--23. 1. " RED99 ,Red99 " hexmask.long.byte 0x00 8.--15. 1. " GREEN99 ,Green99 " hexmask.long.byte 0x00 0.--7. 1. " BLUE99 ,Blue99 " group.long 0x990++0x03 line.long 0x00 "BGCLUT100,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA100 ,Alpha100" hexmask.long.byte 0x00 16.--23. 1. " RED100 ,Red100" hexmask.long.byte 0x00 8.--15. 1. " GREEN100 ,Green100" hexmask.long.byte 0x00 0.--7. 1. " BLUE100 ,Blue100" group.long 0x994++0x03 line.long 0x00 "BGCLUT101,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA101 ,Alpha101" hexmask.long.byte 0x00 16.--23. 1. " RED101 ,Red101" hexmask.long.byte 0x00 8.--15. 1. " GREEN101 ,Green101" hexmask.long.byte 0x00 0.--7. 1. " BLUE101 ,Blue101" group.long 0x998++0x03 line.long 0x00 "BGCLUT102,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA102 ,Alpha102" hexmask.long.byte 0x00 16.--23. 1. " RED102 ,Red102" hexmask.long.byte 0x00 8.--15. 1. " GREEN102 ,Green102" hexmask.long.byte 0x00 0.--7. 1. " BLUE102 ,Blue102" group.long 0x99C++0x03 line.long 0x00 "BGCLUT103,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA103 ,Alpha103" hexmask.long.byte 0x00 16.--23. 1. " RED103 ,Red103" hexmask.long.byte 0x00 8.--15. 1. " GREEN103 ,Green103" hexmask.long.byte 0x00 0.--7. 1. " BLUE103 ,Blue103" group.long 0x9A0++0x03 line.long 0x00 "BGCLUT104,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA104 ,Alpha104" hexmask.long.byte 0x00 16.--23. 1. " RED104 ,Red104" hexmask.long.byte 0x00 8.--15. 1. " GREEN104 ,Green104" hexmask.long.byte 0x00 0.--7. 1. " BLUE104 ,Blue104" group.long 0x9A4++0x03 line.long 0x00 "BGCLUT105,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA105 ,Alpha105" hexmask.long.byte 0x00 16.--23. 1. " RED105 ,Red105" hexmask.long.byte 0x00 8.--15. 1. " GREEN105 ,Green105" hexmask.long.byte 0x00 0.--7. 1. " BLUE105 ,Blue105" group.long 0x9A8++0x03 line.long 0x00 "BGCLUT106,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA106 ,Alpha106" hexmask.long.byte 0x00 16.--23. 1. " RED106 ,Red106" hexmask.long.byte 0x00 8.--15. 1. " GREEN106 ,Green106" hexmask.long.byte 0x00 0.--7. 1. " BLUE106 ,Blue106" group.long 0x9AC++0x03 line.long 0x00 "BGCLUT107,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA107 ,Alpha107" hexmask.long.byte 0x00 16.--23. 1. " RED107 ,Red107" hexmask.long.byte 0x00 8.--15. 1. " GREEN107 ,Green107" hexmask.long.byte 0x00 0.--7. 1. " BLUE107 ,Blue107" group.long 0x9B0++0x03 line.long 0x00 "BGCLUT108,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA108 ,Alpha108" hexmask.long.byte 0x00 16.--23. 1. " RED108 ,Red108" hexmask.long.byte 0x00 8.--15. 1. " GREEN108 ,Green108" hexmask.long.byte 0x00 0.--7. 1. " BLUE108 ,Blue108" group.long 0x9B4++0x03 line.long 0x00 "BGCLUT109,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA109 ,Alpha109" hexmask.long.byte 0x00 16.--23. 1. " RED109 ,Red109" hexmask.long.byte 0x00 8.--15. 1. " GREEN109 ,Green109" hexmask.long.byte 0x00 0.--7. 1. " BLUE109 ,Blue109" group.long 0x9B8++0x03 line.long 0x00 "BGCLUT110,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA110 ,Alpha110" hexmask.long.byte 0x00 16.--23. 1. " RED110 ,Red110" hexmask.long.byte 0x00 8.--15. 1. " GREEN110 ,Green110" hexmask.long.byte 0x00 0.--7. 1. " BLUE110 ,Blue110" group.long 0x9BC++0x03 line.long 0x00 "BGCLUT111,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA111 ,Alpha111" hexmask.long.byte 0x00 16.--23. 1. " RED111 ,Red111" hexmask.long.byte 0x00 8.--15. 1. " GREEN111 ,Green111" hexmask.long.byte 0x00 0.--7. 1. " BLUE111 ,Blue111" group.long 0x9C0++0x03 line.long 0x00 "BGCLUT112,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA112 ,Alpha112" hexmask.long.byte 0x00 16.--23. 1. " RED112 ,Red112" hexmask.long.byte 0x00 8.--15. 1. " GREEN112 ,Green112" hexmask.long.byte 0x00 0.--7. 1. " BLUE112 ,Blue112" group.long 0x9C4++0x03 line.long 0x00 "BGCLUT113,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA113 ,Alpha113" hexmask.long.byte 0x00 16.--23. 1. " RED113 ,Red113" hexmask.long.byte 0x00 8.--15. 1. " GREEN113 ,Green113" hexmask.long.byte 0x00 0.--7. 1. " BLUE113 ,Blue113" group.long 0x9C8++0x03 line.long 0x00 "BGCLUT114,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA114 ,Alpha114" hexmask.long.byte 0x00 16.--23. 1. " RED114 ,Red114" hexmask.long.byte 0x00 8.--15. 1. " GREEN114 ,Green114" hexmask.long.byte 0x00 0.--7. 1. " BLUE114 ,Blue114" group.long 0x9CC++0x03 line.long 0x00 "BGCLUT115,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA115 ,Alpha115" hexmask.long.byte 0x00 16.--23. 1. " RED115 ,Red115" hexmask.long.byte 0x00 8.--15. 1. " GREEN115 ,Green115" hexmask.long.byte 0x00 0.--7. 1. " BLUE115 ,Blue115" group.long 0x9D0++0x03 line.long 0x00 "BGCLUT116,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA116 ,Alpha116" hexmask.long.byte 0x00 16.--23. 1. " RED116 ,Red116" hexmask.long.byte 0x00 8.--15. 1. " GREEN116 ,Green116" hexmask.long.byte 0x00 0.--7. 1. " BLUE116 ,Blue116" group.long 0x9D4++0x03 line.long 0x00 "BGCLUT117,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA117 ,Alpha117" hexmask.long.byte 0x00 16.--23. 1. " RED117 ,Red117" hexmask.long.byte 0x00 8.--15. 1. " GREEN117 ,Green117" hexmask.long.byte 0x00 0.--7. 1. " BLUE117 ,Blue117" group.long 0x9D8++0x03 line.long 0x00 "BGCLUT118,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA118 ,Alpha118" hexmask.long.byte 0x00 16.--23. 1. " RED118 ,Red118" hexmask.long.byte 0x00 8.--15. 1. " GREEN118 ,Green118" hexmask.long.byte 0x00 0.--7. 1. " BLUE118 ,Blue118" group.long 0x9DC++0x03 line.long 0x00 "BGCLUT119,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA119 ,Alpha119" hexmask.long.byte 0x00 16.--23. 1. " RED119 ,Red119" hexmask.long.byte 0x00 8.--15. 1. " GREEN119 ,Green119" hexmask.long.byte 0x00 0.--7. 1. " BLUE119 ,Blue119" group.long 0x9E0++0x03 line.long 0x00 "BGCLUT120,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA120 ,Alpha120" hexmask.long.byte 0x00 16.--23. 1. " RED120 ,Red120" hexmask.long.byte 0x00 8.--15. 1. " GREEN120 ,Green120" hexmask.long.byte 0x00 0.--7. 1. " BLUE120 ,Blue120" group.long 0x9E4++0x03 line.long 0x00 "BGCLUT121,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA121 ,Alpha121" hexmask.long.byte 0x00 16.--23. 1. " RED121 ,Red121" hexmask.long.byte 0x00 8.--15. 1. " GREEN121 ,Green121" hexmask.long.byte 0x00 0.--7. 1. " BLUE121 ,Blue121" group.long 0x9E8++0x03 line.long 0x00 "BGCLUT122,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA122 ,Alpha122" hexmask.long.byte 0x00 16.--23. 1. " RED122 ,Red122" hexmask.long.byte 0x00 8.--15. 1. " GREEN122 ,Green122" hexmask.long.byte 0x00 0.--7. 1. " BLUE122 ,Blue122" group.long 0x9EC++0x03 line.long 0x00 "BGCLUT123,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA123 ,Alpha123" hexmask.long.byte 0x00 16.--23. 1. " RED123 ,Red123" hexmask.long.byte 0x00 8.--15. 1. " GREEN123 ,Green123" hexmask.long.byte 0x00 0.--7. 1. " BLUE123 ,Blue123" group.long 0x9F0++0x03 line.long 0x00 "BGCLUT124,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA124 ,Alpha124" hexmask.long.byte 0x00 16.--23. 1. " RED124 ,Red124" hexmask.long.byte 0x00 8.--15. 1. " GREEN124 ,Green124" hexmask.long.byte 0x00 0.--7. 1. " BLUE124 ,Blue124" group.long 0x9F4++0x03 line.long 0x00 "BGCLUT125,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA125 ,Alpha125" hexmask.long.byte 0x00 16.--23. 1. " RED125 ,Red125" hexmask.long.byte 0x00 8.--15. 1. " GREEN125 ,Green125" hexmask.long.byte 0x00 0.--7. 1. " BLUE125 ,Blue125" group.long 0x9F8++0x03 line.long 0x00 "BGCLUT126,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA126 ,Alpha126" hexmask.long.byte 0x00 16.--23. 1. " RED126 ,Red126" hexmask.long.byte 0x00 8.--15. 1. " GREEN126 ,Green126" hexmask.long.byte 0x00 0.--7. 1. " BLUE126 ,Blue126" group.long 0x9FC++0x03 line.long 0x00 "BGCLUT127,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA127 ,Alpha127" hexmask.long.byte 0x00 16.--23. 1. " RED127 ,Red127" hexmask.long.byte 0x00 8.--15. 1. " GREEN127 ,Green127" hexmask.long.byte 0x00 0.--7. 1. " BLUE127 ,Blue127" group.long 0xA00++0x03 line.long 0x00 "BGCLUT128,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA128 ,Alpha128" hexmask.long.byte 0x00 16.--23. 1. " RED128 ,Red128" hexmask.long.byte 0x00 8.--15. 1. " GREEN128 ,Green128" hexmask.long.byte 0x00 0.--7. 1. " BLUE128 ,Blue128" group.long 0xA04++0x03 line.long 0x00 "BGCLUT129,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA129 ,Alpha129" hexmask.long.byte 0x00 16.--23. 1. " RED129 ,Red129" hexmask.long.byte 0x00 8.--15. 1. " GREEN129 ,Green129" hexmask.long.byte 0x00 0.--7. 1. " BLUE129 ,Blue129" group.long 0xA08++0x03 line.long 0x00 "BGCLUT130,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA130 ,Alpha130" hexmask.long.byte 0x00 16.--23. 1. " RED130 ,Red130" hexmask.long.byte 0x00 8.--15. 1. " GREEN130 ,Green130" hexmask.long.byte 0x00 0.--7. 1. " BLUE130 ,Blue130" group.long 0xA0C++0x03 line.long 0x00 "BGCLUT131,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA131 ,Alpha131" hexmask.long.byte 0x00 16.--23. 1. " RED131 ,Red131" hexmask.long.byte 0x00 8.--15. 1. " GREEN131 ,Green131" hexmask.long.byte 0x00 0.--7. 1. " BLUE131 ,Blue131" group.long 0xA10++0x03 line.long 0x00 "BGCLUT132,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA132 ,Alpha132" hexmask.long.byte 0x00 16.--23. 1. " RED132 ,Red132" hexmask.long.byte 0x00 8.--15. 1. " GREEN132 ,Green132" hexmask.long.byte 0x00 0.--7. 1. " BLUE132 ,Blue132" group.long 0xA14++0x03 line.long 0x00 "BGCLUT133,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA133 ,Alpha133" hexmask.long.byte 0x00 16.--23. 1. " RED133 ,Red133" hexmask.long.byte 0x00 8.--15. 1. " GREEN133 ,Green133" hexmask.long.byte 0x00 0.--7. 1. " BLUE133 ,Blue133" group.long 0xA18++0x03 line.long 0x00 "BGCLUT134,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA134 ,Alpha134" hexmask.long.byte 0x00 16.--23. 1. " RED134 ,Red134" hexmask.long.byte 0x00 8.--15. 1. " GREEN134 ,Green134" hexmask.long.byte 0x00 0.--7. 1. " BLUE134 ,Blue134" group.long 0xA1C++0x03 line.long 0x00 "BGCLUT135,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA135 ,Alpha135" hexmask.long.byte 0x00 16.--23. 1. " RED135 ,Red135" hexmask.long.byte 0x00 8.--15. 1. " GREEN135 ,Green135" hexmask.long.byte 0x00 0.--7. 1. " BLUE135 ,Blue135" group.long 0xA20++0x03 line.long 0x00 "BGCLUT136,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA136 ,Alpha136" hexmask.long.byte 0x00 16.--23. 1. " RED136 ,Red136" hexmask.long.byte 0x00 8.--15. 1. " GREEN136 ,Green136" hexmask.long.byte 0x00 0.--7. 1. " BLUE136 ,Blue136" group.long 0xA24++0x03 line.long 0x00 "BGCLUT137,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA137 ,Alpha137" hexmask.long.byte 0x00 16.--23. 1. " RED137 ,Red137" hexmask.long.byte 0x00 8.--15. 1. " GREEN137 ,Green137" hexmask.long.byte 0x00 0.--7. 1. " BLUE137 ,Blue137" group.long 0xA28++0x03 line.long 0x00 "BGCLUT138,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA138 ,Alpha138" hexmask.long.byte 0x00 16.--23. 1. " RED138 ,Red138" hexmask.long.byte 0x00 8.--15. 1. " GREEN138 ,Green138" hexmask.long.byte 0x00 0.--7. 1. " BLUE138 ,Blue138" group.long 0xA2C++0x03 line.long 0x00 "BGCLUT139,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA139 ,Alpha139" hexmask.long.byte 0x00 16.--23. 1. " RED139 ,Red139" hexmask.long.byte 0x00 8.--15. 1. " GREEN139 ,Green139" hexmask.long.byte 0x00 0.--7. 1. " BLUE139 ,Blue139" group.long 0xA30++0x03 line.long 0x00 "BGCLUT140,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA140 ,Alpha140" hexmask.long.byte 0x00 16.--23. 1. " RED140 ,Red140" hexmask.long.byte 0x00 8.--15. 1. " GREEN140 ,Green140" hexmask.long.byte 0x00 0.--7. 1. " BLUE140 ,Blue140" group.long 0xA34++0x03 line.long 0x00 "BGCLUT141,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA141 ,Alpha141" hexmask.long.byte 0x00 16.--23. 1. " RED141 ,Red141" hexmask.long.byte 0x00 8.--15. 1. " GREEN141 ,Green141" hexmask.long.byte 0x00 0.--7. 1. " BLUE141 ,Blue141" group.long 0xA38++0x03 line.long 0x00 "BGCLUT142,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA142 ,Alpha142" hexmask.long.byte 0x00 16.--23. 1. " RED142 ,Red142" hexmask.long.byte 0x00 8.--15. 1. " GREEN142 ,Green142" hexmask.long.byte 0x00 0.--7. 1. " BLUE142 ,Blue142" group.long 0xA3C++0x03 line.long 0x00 "BGCLUT143,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA143 ,Alpha143" hexmask.long.byte 0x00 16.--23. 1. " RED143 ,Red143" hexmask.long.byte 0x00 8.--15. 1. " GREEN143 ,Green143" hexmask.long.byte 0x00 0.--7. 1. " BLUE143 ,Blue143" group.long 0xA40++0x03 line.long 0x00 "BGCLUT144,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA144 ,Alpha144" hexmask.long.byte 0x00 16.--23. 1. " RED144 ,Red144" hexmask.long.byte 0x00 8.--15. 1. " GREEN144 ,Green144" hexmask.long.byte 0x00 0.--7. 1. " BLUE144 ,Blue144" group.long 0xA44++0x03 line.long 0x00 "BGCLUT145,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA145 ,Alpha145" hexmask.long.byte 0x00 16.--23. 1. " RED145 ,Red145" hexmask.long.byte 0x00 8.--15. 1. " GREEN145 ,Green145" hexmask.long.byte 0x00 0.--7. 1. " BLUE145 ,Blue145" group.long 0xA48++0x03 line.long 0x00 "BGCLUT146,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA146 ,Alpha146" hexmask.long.byte 0x00 16.--23. 1. " RED146 ,Red146" hexmask.long.byte 0x00 8.--15. 1. " GREEN146 ,Green146" hexmask.long.byte 0x00 0.--7. 1. " BLUE146 ,Blue146" group.long 0xA4C++0x03 line.long 0x00 "BGCLUT147,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA147 ,Alpha147" hexmask.long.byte 0x00 16.--23. 1. " RED147 ,Red147" hexmask.long.byte 0x00 8.--15. 1. " GREEN147 ,Green147" hexmask.long.byte 0x00 0.--7. 1. " BLUE147 ,Blue147" group.long 0xA50++0x03 line.long 0x00 "BGCLUT148,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA148 ,Alpha148" hexmask.long.byte 0x00 16.--23. 1. " RED148 ,Red148" hexmask.long.byte 0x00 8.--15. 1. " GREEN148 ,Green148" hexmask.long.byte 0x00 0.--7. 1. " BLUE148 ,Blue148" group.long 0xA54++0x03 line.long 0x00 "BGCLUT149,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA149 ,Alpha149" hexmask.long.byte 0x00 16.--23. 1. " RED149 ,Red149" hexmask.long.byte 0x00 8.--15. 1. " GREEN149 ,Green149" hexmask.long.byte 0x00 0.--7. 1. " BLUE149 ,Blue149" group.long 0xA58++0x03 line.long 0x00 "BGCLUT150,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA150 ,Alpha150" hexmask.long.byte 0x00 16.--23. 1. " RED150 ,Red150" hexmask.long.byte 0x00 8.--15. 1. " GREEN150 ,Green150" hexmask.long.byte 0x00 0.--7. 1. " BLUE150 ,Blue150" group.long 0xA5C++0x03 line.long 0x00 "BGCLUT151,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA151 ,Alpha151" hexmask.long.byte 0x00 16.--23. 1. " RED151 ,Red151" hexmask.long.byte 0x00 8.--15. 1. " GREEN151 ,Green151" hexmask.long.byte 0x00 0.--7. 1. " BLUE151 ,Blue151" group.long 0xA60++0x03 line.long 0x00 "BGCLUT152,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA152 ,Alpha152" hexmask.long.byte 0x00 16.--23. 1. " RED152 ,Red152" hexmask.long.byte 0x00 8.--15. 1. " GREEN152 ,Green152" hexmask.long.byte 0x00 0.--7. 1. " BLUE152 ,Blue152" group.long 0xA64++0x03 line.long 0x00 "BGCLUT153,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA153 ,Alpha153" hexmask.long.byte 0x00 16.--23. 1. " RED153 ,Red153" hexmask.long.byte 0x00 8.--15. 1. " GREEN153 ,Green153" hexmask.long.byte 0x00 0.--7. 1. " BLUE153 ,Blue153" group.long 0xA68++0x03 line.long 0x00 "BGCLUT154,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA154 ,Alpha154" hexmask.long.byte 0x00 16.--23. 1. " RED154 ,Red154" hexmask.long.byte 0x00 8.--15. 1. " GREEN154 ,Green154" hexmask.long.byte 0x00 0.--7. 1. " BLUE154 ,Blue154" group.long 0xA6C++0x03 line.long 0x00 "BGCLUT155,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA155 ,Alpha155" hexmask.long.byte 0x00 16.--23. 1. " RED155 ,Red155" hexmask.long.byte 0x00 8.--15. 1. " GREEN155 ,Green155" hexmask.long.byte 0x00 0.--7. 1. " BLUE155 ,Blue155" group.long 0xA70++0x03 line.long 0x00 "BGCLUT156,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA156 ,Alpha156" hexmask.long.byte 0x00 16.--23. 1. " RED156 ,Red156" hexmask.long.byte 0x00 8.--15. 1. " GREEN156 ,Green156" hexmask.long.byte 0x00 0.--7. 1. " BLUE156 ,Blue156" group.long 0xA74++0x03 line.long 0x00 "BGCLUT157,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA157 ,Alpha157" hexmask.long.byte 0x00 16.--23. 1. " RED157 ,Red157" hexmask.long.byte 0x00 8.--15. 1. " GREEN157 ,Green157" hexmask.long.byte 0x00 0.--7. 1. " BLUE157 ,Blue157" group.long 0xA78++0x03 line.long 0x00 "BGCLUT158,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA158 ,Alpha158" hexmask.long.byte 0x00 16.--23. 1. " RED158 ,Red158" hexmask.long.byte 0x00 8.--15. 1. " GREEN158 ,Green158" hexmask.long.byte 0x00 0.--7. 1. " BLUE158 ,Blue158" group.long 0xA7C++0x03 line.long 0x00 "BGCLUT159,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA159 ,Alpha159" hexmask.long.byte 0x00 16.--23. 1. " RED159 ,Red159" hexmask.long.byte 0x00 8.--15. 1. " GREEN159 ,Green159" hexmask.long.byte 0x00 0.--7. 1. " BLUE159 ,Blue159" group.long 0xA80++0x03 line.long 0x00 "BGCLUT160,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA160 ,Alpha160" hexmask.long.byte 0x00 16.--23. 1. " RED160 ,Red160" hexmask.long.byte 0x00 8.--15. 1. " GREEN160 ,Green160" hexmask.long.byte 0x00 0.--7. 1. " BLUE160 ,Blue160" group.long 0xA84++0x03 line.long 0x00 "BGCLUT161,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA161 ,Alpha161" hexmask.long.byte 0x00 16.--23. 1. " RED161 ,Red161" hexmask.long.byte 0x00 8.--15. 1. " GREEN161 ,Green161" hexmask.long.byte 0x00 0.--7. 1. " BLUE161 ,Blue161" group.long 0xA88++0x03 line.long 0x00 "BGCLUT162,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA162 ,Alpha162" hexmask.long.byte 0x00 16.--23. 1. " RED162 ,Red162" hexmask.long.byte 0x00 8.--15. 1. " GREEN162 ,Green162" hexmask.long.byte 0x00 0.--7. 1. " BLUE162 ,Blue162" group.long 0xA8C++0x03 line.long 0x00 "BGCLUT163,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA163 ,Alpha163" hexmask.long.byte 0x00 16.--23. 1. " RED163 ,Red163" hexmask.long.byte 0x00 8.--15. 1. " GREEN163 ,Green163" hexmask.long.byte 0x00 0.--7. 1. " BLUE163 ,Blue163" group.long 0xA90++0x03 line.long 0x00 "BGCLUT164,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA164 ,Alpha164" hexmask.long.byte 0x00 16.--23. 1. " RED164 ,Red164" hexmask.long.byte 0x00 8.--15. 1. " GREEN164 ,Green164" hexmask.long.byte 0x00 0.--7. 1. " BLUE164 ,Blue164" group.long 0xA94++0x03 line.long 0x00 "BGCLUT165,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA165 ,Alpha165" hexmask.long.byte 0x00 16.--23. 1. " RED165 ,Red165" hexmask.long.byte 0x00 8.--15. 1. " GREEN165 ,Green165" hexmask.long.byte 0x00 0.--7. 1. " BLUE165 ,Blue165" group.long 0xA98++0x03 line.long 0x00 "BGCLUT166,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA166 ,Alpha166" hexmask.long.byte 0x00 16.--23. 1. " RED166 ,Red166" hexmask.long.byte 0x00 8.--15. 1. " GREEN166 ,Green166" hexmask.long.byte 0x00 0.--7. 1. " BLUE166 ,Blue166" group.long 0xA9C++0x03 line.long 0x00 "BGCLUT167,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA167 ,Alpha167" hexmask.long.byte 0x00 16.--23. 1. " RED167 ,Red167" hexmask.long.byte 0x00 8.--15. 1. " GREEN167 ,Green167" hexmask.long.byte 0x00 0.--7. 1. " BLUE167 ,Blue167" group.long 0xAA0++0x03 line.long 0x00 "BGCLUT168,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA168 ,Alpha168" hexmask.long.byte 0x00 16.--23. 1. " RED168 ,Red168" hexmask.long.byte 0x00 8.--15. 1. " GREEN168 ,Green168" hexmask.long.byte 0x00 0.--7. 1. " BLUE168 ,Blue168" group.long 0xAA4++0x03 line.long 0x00 "BGCLUT169,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA169 ,Alpha169" hexmask.long.byte 0x00 16.--23. 1. " RED169 ,Red169" hexmask.long.byte 0x00 8.--15. 1. " GREEN169 ,Green169" hexmask.long.byte 0x00 0.--7. 1. " BLUE169 ,Blue169" group.long 0xAA8++0x03 line.long 0x00 "BGCLUT170,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA170 ,Alpha170" hexmask.long.byte 0x00 16.--23. 1. " RED170 ,Red170" hexmask.long.byte 0x00 8.--15. 1. " GREEN170 ,Green170" hexmask.long.byte 0x00 0.--7. 1. " BLUE170 ,Blue170" group.long 0xAAC++0x03 line.long 0x00 "BGCLUT171,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA171 ,Alpha171" hexmask.long.byte 0x00 16.--23. 1. " RED171 ,Red171" hexmask.long.byte 0x00 8.--15. 1. " GREEN171 ,Green171" hexmask.long.byte 0x00 0.--7. 1. " BLUE171 ,Blue171" group.long 0xAB0++0x03 line.long 0x00 "BGCLUT172,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA172 ,Alpha172" hexmask.long.byte 0x00 16.--23. 1. " RED172 ,Red172" hexmask.long.byte 0x00 8.--15. 1. " GREEN172 ,Green172" hexmask.long.byte 0x00 0.--7. 1. " BLUE172 ,Blue172" group.long 0xAB4++0x03 line.long 0x00 "BGCLUT173,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA173 ,Alpha173" hexmask.long.byte 0x00 16.--23. 1. " RED173 ,Red173" hexmask.long.byte 0x00 8.--15. 1. " GREEN173 ,Green173" hexmask.long.byte 0x00 0.--7. 1. " BLUE173 ,Blue173" group.long 0xAB8++0x03 line.long 0x00 "BGCLUT174,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA174 ,Alpha174" hexmask.long.byte 0x00 16.--23. 1. " RED174 ,Red174" hexmask.long.byte 0x00 8.--15. 1. " GREEN174 ,Green174" hexmask.long.byte 0x00 0.--7. 1. " BLUE174 ,Blue174" group.long 0xABC++0x03 line.long 0x00 "BGCLUT175,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA175 ,Alpha175" hexmask.long.byte 0x00 16.--23. 1. " RED175 ,Red175" hexmask.long.byte 0x00 8.--15. 1. " GREEN175 ,Green175" hexmask.long.byte 0x00 0.--7. 1. " BLUE175 ,Blue175" group.long 0xAC0++0x03 line.long 0x00 "BGCLUT176,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA176 ,Alpha176" hexmask.long.byte 0x00 16.--23. 1. " RED176 ,Red176" hexmask.long.byte 0x00 8.--15. 1. " GREEN176 ,Green176" hexmask.long.byte 0x00 0.--7. 1. " BLUE176 ,Blue176" group.long 0xAC4++0x03 line.long 0x00 "BGCLUT177,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA177 ,Alpha177" hexmask.long.byte 0x00 16.--23. 1. " RED177 ,Red177" hexmask.long.byte 0x00 8.--15. 1. " GREEN177 ,Green177" hexmask.long.byte 0x00 0.--7. 1. " BLUE177 ,Blue177" group.long 0xAC8++0x03 line.long 0x00 "BGCLUT178,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA178 ,Alpha178" hexmask.long.byte 0x00 16.--23. 1. " RED178 ,Red178" hexmask.long.byte 0x00 8.--15. 1. " GREEN178 ,Green178" hexmask.long.byte 0x00 0.--7. 1. " BLUE178 ,Blue178" group.long 0xACC++0x03 line.long 0x00 "BGCLUT179,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA179 ,Alpha179" hexmask.long.byte 0x00 16.--23. 1. " RED179 ,Red179" hexmask.long.byte 0x00 8.--15. 1. " GREEN179 ,Green179" hexmask.long.byte 0x00 0.--7. 1. " BLUE179 ,Blue179" group.long 0xAD0++0x03 line.long 0x00 "BGCLUT180,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA180 ,Alpha180" hexmask.long.byte 0x00 16.--23. 1. " RED180 ,Red180" hexmask.long.byte 0x00 8.--15. 1. " GREEN180 ,Green180" hexmask.long.byte 0x00 0.--7. 1. " BLUE180 ,Blue180" group.long 0xAD4++0x03 line.long 0x00 "BGCLUT181,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA181 ,Alpha181" hexmask.long.byte 0x00 16.--23. 1. " RED181 ,Red181" hexmask.long.byte 0x00 8.--15. 1. " GREEN181 ,Green181" hexmask.long.byte 0x00 0.--7. 1. " BLUE181 ,Blue181" group.long 0xAD8++0x03 line.long 0x00 "BGCLUT182,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA182 ,Alpha182" hexmask.long.byte 0x00 16.--23. 1. " RED182 ,Red182" hexmask.long.byte 0x00 8.--15. 1. " GREEN182 ,Green182" hexmask.long.byte 0x00 0.--7. 1. " BLUE182 ,Blue182" group.long 0xADC++0x03 line.long 0x00 "BGCLUT183,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA183 ,Alpha183" hexmask.long.byte 0x00 16.--23. 1. " RED183 ,Red183" hexmask.long.byte 0x00 8.--15. 1. " GREEN183 ,Green183" hexmask.long.byte 0x00 0.--7. 1. " BLUE183 ,Blue183" group.long 0xAE0++0x03 line.long 0x00 "BGCLUT184,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA184 ,Alpha184" hexmask.long.byte 0x00 16.--23. 1. " RED184 ,Red184" hexmask.long.byte 0x00 8.--15. 1. " GREEN184 ,Green184" hexmask.long.byte 0x00 0.--7. 1. " BLUE184 ,Blue184" group.long 0xAE4++0x03 line.long 0x00 "BGCLUT185,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA185 ,Alpha185" hexmask.long.byte 0x00 16.--23. 1. " RED185 ,Red185" hexmask.long.byte 0x00 8.--15. 1. " GREEN185 ,Green185" hexmask.long.byte 0x00 0.--7. 1. " BLUE185 ,Blue185" group.long 0xAE8++0x03 line.long 0x00 "BGCLUT186,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA186 ,Alpha186" hexmask.long.byte 0x00 16.--23. 1. " RED186 ,Red186" hexmask.long.byte 0x00 8.--15. 1. " GREEN186 ,Green186" hexmask.long.byte 0x00 0.--7. 1. " BLUE186 ,Blue186" group.long 0xAEC++0x03 line.long 0x00 "BGCLUT187,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA187 ,Alpha187" hexmask.long.byte 0x00 16.--23. 1. " RED187 ,Red187" hexmask.long.byte 0x00 8.--15. 1. " GREEN187 ,Green187" hexmask.long.byte 0x00 0.--7. 1. " BLUE187 ,Blue187" group.long 0xAF0++0x03 line.long 0x00 "BGCLUT188,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA188 ,Alpha188" hexmask.long.byte 0x00 16.--23. 1. " RED188 ,Red188" hexmask.long.byte 0x00 8.--15. 1. " GREEN188 ,Green188" hexmask.long.byte 0x00 0.--7. 1. " BLUE188 ,Blue188" group.long 0xAF4++0x03 line.long 0x00 "BGCLUT189,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA189 ,Alpha189" hexmask.long.byte 0x00 16.--23. 1. " RED189 ,Red189" hexmask.long.byte 0x00 8.--15. 1. " GREEN189 ,Green189" hexmask.long.byte 0x00 0.--7. 1. " BLUE189 ,Blue189" group.long 0xAF8++0x03 line.long 0x00 "BGCLUT190,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA190 ,Alpha190" hexmask.long.byte 0x00 16.--23. 1. " RED190 ,Red190" hexmask.long.byte 0x00 8.--15. 1. " GREEN190 ,Green190" hexmask.long.byte 0x00 0.--7. 1. " BLUE190 ,Blue190" group.long 0xAFC++0x03 line.long 0x00 "BGCLUT191,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA191 ,Alpha191" hexmask.long.byte 0x00 16.--23. 1. " RED191 ,Red191" hexmask.long.byte 0x00 8.--15. 1. " GREEN191 ,Green191" hexmask.long.byte 0x00 0.--7. 1. " BLUE191 ,Blue191" group.long 0xB00++0x03 line.long 0x00 "BGCLUT192,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA192 ,Alpha192" hexmask.long.byte 0x00 16.--23. 1. " RED192 ,Red192" hexmask.long.byte 0x00 8.--15. 1. " GREEN192 ,Green192" hexmask.long.byte 0x00 0.--7. 1. " BLUE192 ,Blue192" group.long 0xB04++0x03 line.long 0x00 "BGCLUT193,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA193 ,Alpha193" hexmask.long.byte 0x00 16.--23. 1. " RED193 ,Red193" hexmask.long.byte 0x00 8.--15. 1. " GREEN193 ,Green193" hexmask.long.byte 0x00 0.--7. 1. " BLUE193 ,Blue193" group.long 0xB08++0x03 line.long 0x00 "BGCLUT194,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA194 ,Alpha194" hexmask.long.byte 0x00 16.--23. 1. " RED194 ,Red194" hexmask.long.byte 0x00 8.--15. 1. " GREEN194 ,Green194" hexmask.long.byte 0x00 0.--7. 1. " BLUE194 ,Blue194" group.long 0xB0C++0x03 line.long 0x00 "BGCLUT195,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA195 ,Alpha195" hexmask.long.byte 0x00 16.--23. 1. " RED195 ,Red195" hexmask.long.byte 0x00 8.--15. 1. " GREEN195 ,Green195" hexmask.long.byte 0x00 0.--7. 1. " BLUE195 ,Blue195" group.long 0xB10++0x03 line.long 0x00 "BGCLUT196,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA196 ,Alpha196" hexmask.long.byte 0x00 16.--23. 1. " RED196 ,Red196" hexmask.long.byte 0x00 8.--15. 1. " GREEN196 ,Green196" hexmask.long.byte 0x00 0.--7. 1. " BLUE196 ,Blue196" group.long 0xB14++0x03 line.long 0x00 "BGCLUT197,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA197 ,Alpha197" hexmask.long.byte 0x00 16.--23. 1. " RED197 ,Red197" hexmask.long.byte 0x00 8.--15. 1. " GREEN197 ,Green197" hexmask.long.byte 0x00 0.--7. 1. " BLUE197 ,Blue197" group.long 0xB18++0x03 line.long 0x00 "BGCLUT198,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA198 ,Alpha198" hexmask.long.byte 0x00 16.--23. 1. " RED198 ,Red198" hexmask.long.byte 0x00 8.--15. 1. " GREEN198 ,Green198" hexmask.long.byte 0x00 0.--7. 1. " BLUE198 ,Blue198" group.long 0xB1C++0x03 line.long 0x00 "BGCLUT199,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA199 ,Alpha199" hexmask.long.byte 0x00 16.--23. 1. " RED199 ,Red199" hexmask.long.byte 0x00 8.--15. 1. " GREEN199 ,Green199" hexmask.long.byte 0x00 0.--7. 1. " BLUE199 ,Blue199" group.long 0xB20++0x03 line.long 0x00 "BGCLUT200,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA200 ,Alpha200" hexmask.long.byte 0x00 16.--23. 1. " RED200 ,Red200" hexmask.long.byte 0x00 8.--15. 1. " GREEN200 ,Green200" hexmask.long.byte 0x00 0.--7. 1. " BLUE200 ,Blue200" group.long 0xB24++0x03 line.long 0x00 "BGCLUT201,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA201 ,Alpha201" hexmask.long.byte 0x00 16.--23. 1. " RED201 ,Red201" hexmask.long.byte 0x00 8.--15. 1. " GREEN201 ,Green201" hexmask.long.byte 0x00 0.--7. 1. " BLUE201 ,Blue201" group.long 0xB28++0x03 line.long 0x00 "BGCLUT202,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA202 ,Alpha202" hexmask.long.byte 0x00 16.--23. 1. " RED202 ,Red202" hexmask.long.byte 0x00 8.--15. 1. " GREEN202 ,Green202" hexmask.long.byte 0x00 0.--7. 1. " BLUE202 ,Blue202" group.long 0xB2C++0x03 line.long 0x00 "BGCLUT203,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA203 ,Alpha203" hexmask.long.byte 0x00 16.--23. 1. " RED203 ,Red203" hexmask.long.byte 0x00 8.--15. 1. " GREEN203 ,Green203" hexmask.long.byte 0x00 0.--7. 1. " BLUE203 ,Blue203" group.long 0xB30++0x03 line.long 0x00 "BGCLUT204,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA204 ,Alpha204" hexmask.long.byte 0x00 16.--23. 1. " RED204 ,Red204" hexmask.long.byte 0x00 8.--15. 1. " GREEN204 ,Green204" hexmask.long.byte 0x00 0.--7. 1. " BLUE204 ,Blue204" group.long 0xB34++0x03 line.long 0x00 "BGCLUT205,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA205 ,Alpha205" hexmask.long.byte 0x00 16.--23. 1. " RED205 ,Red205" hexmask.long.byte 0x00 8.--15. 1. " GREEN205 ,Green205" hexmask.long.byte 0x00 0.--7. 1. " BLUE205 ,Blue205" group.long 0xB38++0x03 line.long 0x00 "BGCLUT206,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA206 ,Alpha206" hexmask.long.byte 0x00 16.--23. 1. " RED206 ,Red206" hexmask.long.byte 0x00 8.--15. 1. " GREEN206 ,Green206" hexmask.long.byte 0x00 0.--7. 1. " BLUE206 ,Blue206" group.long 0xB3C++0x03 line.long 0x00 "BGCLUT207,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA207 ,Alpha207" hexmask.long.byte 0x00 16.--23. 1. " RED207 ,Red207" hexmask.long.byte 0x00 8.--15. 1. " GREEN207 ,Green207" hexmask.long.byte 0x00 0.--7. 1. " BLUE207 ,Blue207" group.long 0xB40++0x03 line.long 0x00 "BGCLUT208,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA208 ,Alpha208" hexmask.long.byte 0x00 16.--23. 1. " RED208 ,Red208" hexmask.long.byte 0x00 8.--15. 1. " GREEN208 ,Green208" hexmask.long.byte 0x00 0.--7. 1. " BLUE208 ,Blue208" group.long 0xB44++0x03 line.long 0x00 "BGCLUT209,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA209 ,Alpha209" hexmask.long.byte 0x00 16.--23. 1. " RED209 ,Red209" hexmask.long.byte 0x00 8.--15. 1. " GREEN209 ,Green209" hexmask.long.byte 0x00 0.--7. 1. " BLUE209 ,Blue209" group.long 0xB48++0x03 line.long 0x00 "BGCLUT210,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA210 ,Alpha210" hexmask.long.byte 0x00 16.--23. 1. " RED210 ,Red210" hexmask.long.byte 0x00 8.--15. 1. " GREEN210 ,Green210" hexmask.long.byte 0x00 0.--7. 1. " BLUE210 ,Blue210" group.long 0xB4C++0x03 line.long 0x00 "BGCLUT211,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA211 ,Alpha211" hexmask.long.byte 0x00 16.--23. 1. " RED211 ,Red211" hexmask.long.byte 0x00 8.--15. 1. " GREEN211 ,Green211" hexmask.long.byte 0x00 0.--7. 1. " BLUE211 ,Blue211" group.long 0xB50++0x03 line.long 0x00 "BGCLUT212,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA212 ,Alpha212" hexmask.long.byte 0x00 16.--23. 1. " RED212 ,Red212" hexmask.long.byte 0x00 8.--15. 1. " GREEN212 ,Green212" hexmask.long.byte 0x00 0.--7. 1. " BLUE212 ,Blue212" group.long 0xB54++0x03 line.long 0x00 "BGCLUT213,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA213 ,Alpha213" hexmask.long.byte 0x00 16.--23. 1. " RED213 ,Red213" hexmask.long.byte 0x00 8.--15. 1. " GREEN213 ,Green213" hexmask.long.byte 0x00 0.--7. 1. " BLUE213 ,Blue213" group.long 0xB58++0x03 line.long 0x00 "BGCLUT214,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA214 ,Alpha214" hexmask.long.byte 0x00 16.--23. 1. " RED214 ,Red214" hexmask.long.byte 0x00 8.--15. 1. " GREEN214 ,Green214" hexmask.long.byte 0x00 0.--7. 1. " BLUE214 ,Blue214" group.long 0xB5C++0x03 line.long 0x00 "BGCLUT215,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA215 ,Alpha215" hexmask.long.byte 0x00 16.--23. 1. " RED215 ,Red215" hexmask.long.byte 0x00 8.--15. 1. " GREEN215 ,Green215" hexmask.long.byte 0x00 0.--7. 1. " BLUE215 ,Blue215" group.long 0xB60++0x03 line.long 0x00 "BGCLUT216,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA216 ,Alpha216" hexmask.long.byte 0x00 16.--23. 1. " RED216 ,Red216" hexmask.long.byte 0x00 8.--15. 1. " GREEN216 ,Green216" hexmask.long.byte 0x00 0.--7. 1. " BLUE216 ,Blue216" group.long 0xB64++0x03 line.long 0x00 "BGCLUT217,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA217 ,Alpha217" hexmask.long.byte 0x00 16.--23. 1. " RED217 ,Red217" hexmask.long.byte 0x00 8.--15. 1. " GREEN217 ,Green217" hexmask.long.byte 0x00 0.--7. 1. " BLUE217 ,Blue217" group.long 0xB68++0x03 line.long 0x00 "BGCLUT218,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA218 ,Alpha218" hexmask.long.byte 0x00 16.--23. 1. " RED218 ,Red218" hexmask.long.byte 0x00 8.--15. 1. " GREEN218 ,Green218" hexmask.long.byte 0x00 0.--7. 1. " BLUE218 ,Blue218" group.long 0xB6C++0x03 line.long 0x00 "BGCLUT219,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA219 ,Alpha219" hexmask.long.byte 0x00 16.--23. 1. " RED219 ,Red219" hexmask.long.byte 0x00 8.--15. 1. " GREEN219 ,Green219" hexmask.long.byte 0x00 0.--7. 1. " BLUE219 ,Blue219" group.long 0xB70++0x03 line.long 0x00 "BGCLUT220,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA220 ,Alpha220" hexmask.long.byte 0x00 16.--23. 1. " RED220 ,Red220" hexmask.long.byte 0x00 8.--15. 1. " GREEN220 ,Green220" hexmask.long.byte 0x00 0.--7. 1. " BLUE220 ,Blue220" group.long 0xB74++0x03 line.long 0x00 "BGCLUT221,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA221 ,Alpha221" hexmask.long.byte 0x00 16.--23. 1. " RED221 ,Red221" hexmask.long.byte 0x00 8.--15. 1. " GREEN221 ,Green221" hexmask.long.byte 0x00 0.--7. 1. " BLUE221 ,Blue221" group.long 0xB78++0x03 line.long 0x00 "BGCLUT222,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA222 ,Alpha222" hexmask.long.byte 0x00 16.--23. 1. " RED222 ,Red222" hexmask.long.byte 0x00 8.--15. 1. " GREEN222 ,Green222" hexmask.long.byte 0x00 0.--7. 1. " BLUE222 ,Blue222" group.long 0xB7C++0x03 line.long 0x00 "BGCLUT223,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA223 ,Alpha223" hexmask.long.byte 0x00 16.--23. 1. " RED223 ,Red223" hexmask.long.byte 0x00 8.--15. 1. " GREEN223 ,Green223" hexmask.long.byte 0x00 0.--7. 1. " BLUE223 ,Blue223" group.long 0xB80++0x03 line.long 0x00 "BGCLUT224,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA224 ,Alpha224" hexmask.long.byte 0x00 16.--23. 1. " RED224 ,Red224" hexmask.long.byte 0x00 8.--15. 1. " GREEN224 ,Green224" hexmask.long.byte 0x00 0.--7. 1. " BLUE224 ,Blue224" group.long 0xB84++0x03 line.long 0x00 "BGCLUT225,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA225 ,Alpha225" hexmask.long.byte 0x00 16.--23. 1. " RED225 ,Red225" hexmask.long.byte 0x00 8.--15. 1. " GREEN225 ,Green225" hexmask.long.byte 0x00 0.--7. 1. " BLUE225 ,Blue225" group.long 0xB88++0x03 line.long 0x00 "BGCLUT226,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA226 ,Alpha226" hexmask.long.byte 0x00 16.--23. 1. " RED226 ,Red226" hexmask.long.byte 0x00 8.--15. 1. " GREEN226 ,Green226" hexmask.long.byte 0x00 0.--7. 1. " BLUE226 ,Blue226" group.long 0xB8C++0x03 line.long 0x00 "BGCLUT227,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA227 ,Alpha227" hexmask.long.byte 0x00 16.--23. 1. " RED227 ,Red227" hexmask.long.byte 0x00 8.--15. 1. " GREEN227 ,Green227" hexmask.long.byte 0x00 0.--7. 1. " BLUE227 ,Blue227" group.long 0xB90++0x03 line.long 0x00 "BGCLUT228,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA228 ,Alpha228" hexmask.long.byte 0x00 16.--23. 1. " RED228 ,Red228" hexmask.long.byte 0x00 8.--15. 1. " GREEN228 ,Green228" hexmask.long.byte 0x00 0.--7. 1. " BLUE228 ,Blue228" group.long 0xB94++0x03 line.long 0x00 "BGCLUT229,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA229 ,Alpha229" hexmask.long.byte 0x00 16.--23. 1. " RED229 ,Red229" hexmask.long.byte 0x00 8.--15. 1. " GREEN229 ,Green229" hexmask.long.byte 0x00 0.--7. 1. " BLUE229 ,Blue229" group.long 0xB98++0x03 line.long 0x00 "BGCLUT230,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA230 ,Alpha230" hexmask.long.byte 0x00 16.--23. 1. " RED230 ,Red230" hexmask.long.byte 0x00 8.--15. 1. " GREEN230 ,Green230" hexmask.long.byte 0x00 0.--7. 1. " BLUE230 ,Blue230" group.long 0xB9C++0x03 line.long 0x00 "BGCLUT231,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA231 ,Alpha231" hexmask.long.byte 0x00 16.--23. 1. " RED231 ,Red231" hexmask.long.byte 0x00 8.--15. 1. " GREEN231 ,Green231" hexmask.long.byte 0x00 0.--7. 1. " BLUE231 ,Blue231" group.long 0xBA0++0x03 line.long 0x00 "BGCLUT232,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA232 ,Alpha232" hexmask.long.byte 0x00 16.--23. 1. " RED232 ,Red232" hexmask.long.byte 0x00 8.--15. 1. " GREEN232 ,Green232" hexmask.long.byte 0x00 0.--7. 1. " BLUE232 ,Blue232" group.long 0xBA4++0x03 line.long 0x00 "BGCLUT233,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA233 ,Alpha233" hexmask.long.byte 0x00 16.--23. 1. " RED233 ,Red233" hexmask.long.byte 0x00 8.--15. 1. " GREEN233 ,Green233" hexmask.long.byte 0x00 0.--7. 1. " BLUE233 ,Blue233" group.long 0xBA8++0x03 line.long 0x00 "BGCLUT234,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA234 ,Alpha234" hexmask.long.byte 0x00 16.--23. 1. " RED234 ,Red234" hexmask.long.byte 0x00 8.--15. 1. " GREEN234 ,Green234" hexmask.long.byte 0x00 0.--7. 1. " BLUE234 ,Blue234" group.long 0xBAC++0x03 line.long 0x00 "BGCLUT235,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA235 ,Alpha235" hexmask.long.byte 0x00 16.--23. 1. " RED235 ,Red235" hexmask.long.byte 0x00 8.--15. 1. " GREEN235 ,Green235" hexmask.long.byte 0x00 0.--7. 1. " BLUE235 ,Blue235" group.long 0xBB0++0x03 line.long 0x00 "BGCLUT236,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA236 ,Alpha236" hexmask.long.byte 0x00 16.--23. 1. " RED236 ,Red236" hexmask.long.byte 0x00 8.--15. 1. " GREEN236 ,Green236" hexmask.long.byte 0x00 0.--7. 1. " BLUE236 ,Blue236" group.long 0xBB4++0x03 line.long 0x00 "BGCLUT237,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA237 ,Alpha237" hexmask.long.byte 0x00 16.--23. 1. " RED237 ,Red237" hexmask.long.byte 0x00 8.--15. 1. " GREEN237 ,Green237" hexmask.long.byte 0x00 0.--7. 1. " BLUE237 ,Blue237" group.long 0xBB8++0x03 line.long 0x00 "BGCLUT238,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA238 ,Alpha238" hexmask.long.byte 0x00 16.--23. 1. " RED238 ,Red238" hexmask.long.byte 0x00 8.--15. 1. " GREEN238 ,Green238" hexmask.long.byte 0x00 0.--7. 1. " BLUE238 ,Blue238" group.long 0xBBC++0x03 line.long 0x00 "BGCLUT239,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA239 ,Alpha239" hexmask.long.byte 0x00 16.--23. 1. " RED239 ,Red239" hexmask.long.byte 0x00 8.--15. 1. " GREEN239 ,Green239" hexmask.long.byte 0x00 0.--7. 1. " BLUE239 ,Blue239" group.long 0xBC0++0x03 line.long 0x00 "BGCLUT240,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA240 ,Alpha240" hexmask.long.byte 0x00 16.--23. 1. " RED240 ,Red240" hexmask.long.byte 0x00 8.--15. 1. " GREEN240 ,Green240" hexmask.long.byte 0x00 0.--7. 1. " BLUE240 ,Blue240" group.long 0xBC4++0x03 line.long 0x00 "BGCLUT241,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA241 ,Alpha241" hexmask.long.byte 0x00 16.--23. 1. " RED241 ,Red241" hexmask.long.byte 0x00 8.--15. 1. " GREEN241 ,Green241" hexmask.long.byte 0x00 0.--7. 1. " BLUE241 ,Blue241" group.long 0xBC8++0x03 line.long 0x00 "BGCLUT242,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA242 ,Alpha242" hexmask.long.byte 0x00 16.--23. 1. " RED242 ,Red242" hexmask.long.byte 0x00 8.--15. 1. " GREEN242 ,Green242" hexmask.long.byte 0x00 0.--7. 1. " BLUE242 ,Blue242" group.long 0xBCC++0x03 line.long 0x00 "BGCLUT243,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA243 ,Alpha243" hexmask.long.byte 0x00 16.--23. 1. " RED243 ,Red243" hexmask.long.byte 0x00 8.--15. 1. " GREEN243 ,Green243" hexmask.long.byte 0x00 0.--7. 1. " BLUE243 ,Blue243" group.long 0xBD0++0x03 line.long 0x00 "BGCLUT244,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA244 ,Alpha244" hexmask.long.byte 0x00 16.--23. 1. " RED244 ,Red244" hexmask.long.byte 0x00 8.--15. 1. " GREEN244 ,Green244" hexmask.long.byte 0x00 0.--7. 1. " BLUE244 ,Blue244" group.long 0xBD4++0x03 line.long 0x00 "BGCLUT245,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA245 ,Alpha245" hexmask.long.byte 0x00 16.--23. 1. " RED245 ,Red245" hexmask.long.byte 0x00 8.--15. 1. " GREEN245 ,Green245" hexmask.long.byte 0x00 0.--7. 1. " BLUE245 ,Blue245" group.long 0xBD8++0x03 line.long 0x00 "BGCLUT246,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA246 ,Alpha246" hexmask.long.byte 0x00 16.--23. 1. " RED246 ,Red246" hexmask.long.byte 0x00 8.--15. 1. " GREEN246 ,Green246" hexmask.long.byte 0x00 0.--7. 1. " BLUE246 ,Blue246" group.long 0xBDC++0x03 line.long 0x00 "BGCLUT247,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA247 ,Alpha247" hexmask.long.byte 0x00 16.--23. 1. " RED247 ,Red247" hexmask.long.byte 0x00 8.--15. 1. " GREEN247 ,Green247" hexmask.long.byte 0x00 0.--7. 1. " BLUE247 ,Blue247" group.long 0xBE0++0x03 line.long 0x00 "BGCLUT248,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA248 ,Alpha248" hexmask.long.byte 0x00 16.--23. 1. " RED248 ,Red248" hexmask.long.byte 0x00 8.--15. 1. " GREEN248 ,Green248" hexmask.long.byte 0x00 0.--7. 1. " BLUE248 ,Blue248" group.long 0xBE4++0x03 line.long 0x00 "BGCLUT249,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA249 ,Alpha249" hexmask.long.byte 0x00 16.--23. 1. " RED249 ,Red249" hexmask.long.byte 0x00 8.--15. 1. " GREEN249 ,Green249" hexmask.long.byte 0x00 0.--7. 1. " BLUE249 ,Blue249" group.long 0xBE8++0x03 line.long 0x00 "BGCLUT250,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA250 ,Alpha250" hexmask.long.byte 0x00 16.--23. 1. " RED250 ,Red250" hexmask.long.byte 0x00 8.--15. 1. " GREEN250 ,Green250" hexmask.long.byte 0x00 0.--7. 1. " BLUE250 ,Blue250" group.long 0xBEC++0x03 line.long 0x00 "BGCLUT251,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA251 ,Alpha251" hexmask.long.byte 0x00 16.--23. 1. " RED251 ,Red251" hexmask.long.byte 0x00 8.--15. 1. " GREEN251 ,Green251" hexmask.long.byte 0x00 0.--7. 1. " BLUE251 ,Blue251" group.long 0xBF0++0x03 line.long 0x00 "BGCLUT252,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA252 ,Alpha252" hexmask.long.byte 0x00 16.--23. 1. " RED252 ,Red252" hexmask.long.byte 0x00 8.--15. 1. " GREEN252 ,Green252" hexmask.long.byte 0x00 0.--7. 1. " BLUE252 ,Blue252" group.long 0xBF4++0x03 line.long 0x00 "BGCLUT253,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA253 ,Alpha253" hexmask.long.byte 0x00 16.--23. 1. " RED253 ,Red253" hexmask.long.byte 0x00 8.--15. 1. " GREEN253 ,Green253" hexmask.long.byte 0x00 0.--7. 1. " BLUE253 ,Blue253" group.long 0xBF8++0x03 line.long 0x00 "BGCLUT254,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA254 ,Alpha254" hexmask.long.byte 0x00 16.--23. 1. " RED254 ,Red254" hexmask.long.byte 0x00 8.--15. 1. " GREEN254 ,Green254" hexmask.long.byte 0x00 0.--7. 1. " BLUE254 ,Blue254" group.long 0xBFC++0x03 line.long 0x00 "BGCLUT255,DMA2D Background CLUT" hexmask.long.byte 0x00 24.--31. 1. " ALPHA255 ,Alpha255" hexmask.long.byte 0x00 16.--23. 1. " RED255 ,Red255" hexmask.long.byte 0x00 8.--15. 1. " GREEN255 ,Green255" hexmask.long.byte 0x00 0.--7. 1. " BLUE255 ,Blue255" tree.end endif sif cpuis("STM32L496*")||cpuis("STM32L4A6*") rgroup.long 0x3F4++0x0B line.long 0x00 "VERR,DMA2D IP Version Register" bitfld.long 0x00 4.--7. " MAJREV ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MINREV ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "IPIDR,DMA2D IP Identification Register" line.long 0x08 "SIDR,DMA2D IP Size Identification Register" endif width 0x0B tree.end endif tree "EXTI (Extended interrupts and events controller)" base ad:0x40010400 width 13. group.long 0x00++0x17 line.long 0x00 "EXTI_IMR1,Interrupt Mask Register 1" bitfld.long 0x00 31. " IM[31] ,Interrupt mask on line 31" "Masked,Not masked" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 30. " [30] ,Interrupt mask on line 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Interrupt mask on line 29" "Masked,Not masked" textline " " endif bitfld.long 0x00 28. " [28] ,Interrupt mask on line 28" "Masked,Not masked" bitfld.long 0x00 27. " [27] ,Interrupt mask on line 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Interrupt mask on line 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Interrupt mask on line 25" "Masked,Not masked" textline " " bitfld.long 0x00 24. " [24] ,Interrupt mask on line 24" "Masked,Not masked" bitfld.long 0x00 23. " [23] ,Interrupt mask on line 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Interrupt mask on line 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Interrupt mask on line 21" "Masked,Not masked" textline " " bitfld.long 0x00 20. " [20] ,Interrupt mask on line 20" "Masked,Not masked" bitfld.long 0x00 19. " [19] ,Interrupt mask on line 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Interrupt mask on line 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Interrupt mask on line 17" "Masked,Not masked" textline " " bitfld.long 0x00 16. " [16] ,Interrupt mask on line 16" "Masked,Not masked" bitfld.long 0x00 15. " [15] ,Interrupt mask on line 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Interrupt mask on line 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Interrupt mask on line 13" "Masked,Not masked" textline " " bitfld.long 0x00 12. " [12] ,Interrupt mask on line 12" "Masked,Not masked" bitfld.long 0x00 11. " [11] ,Interrupt mask on line 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Interrupt mask on line 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Interrupt mask on line 9" "Masked,Not masked" textline " " bitfld.long 0x00 8. " [8] ,Interrupt mask on line 8" "Masked,Not masked" bitfld.long 0x00 7. " [7] ,Interrupt mask on line 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Interrupt mask on line 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Interrupt mask on line 5" "Masked,Not masked" textline " " bitfld.long 0x00 4. " [4] ,Interrupt mask on line 4" "Masked,Not masked" bitfld.long 0x00 3. " [3] ,Interrupt mask on line 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Interrupt mask on line 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Interrupt mask on line 1" "Masked,Not masked" textline " " bitfld.long 0x00 0. " [0] ,Interrupt mask on line 0" "Masked,Not masked" line.long 0x04 "EXTI_EMR1,Event Mask Register 1" bitfld.long 0x04 31. " EM[31] ,Event mask on line 31" "Masked,Not masked" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x04 30. " [30] ,Event mask on line 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Event mask on line 29" "Masked,Not masked" textline " " endif bitfld.long 0x04 28. " [28] ,Event mask on line 28" "Masked,Not masked" bitfld.long 0x04 27. " [27] ,Event mask on line 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Event mask on line 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Event mask on line 25" "Masked,Not masked" textline " " bitfld.long 0x04 24. " [24] ,Event mask on line 24" "Masked,Not masked" bitfld.long 0x04 23. " [23] ,Event mask on line 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Event mask on line 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Event mask on line 21" "Masked,Not masked" textline " " bitfld.long 0x04 20. " [20] ,Event mask on line 20" "Masked,Not masked" bitfld.long 0x04 19. " [19] ,Event mask on line 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Event mask on line 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Event mask on line 17" "Masked,Not masked" textline " " bitfld.long 0x04 16. " [16] ,Event mask on line 16" "Masked,Not masked" bitfld.long 0x04 15. " [15] ,Event mask on line 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Event mask on line 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Event mask on line 13" "Masked,Not masked" textline " " bitfld.long 0x04 12. " [12] ,Event mask on line 12" "Masked,Not masked" bitfld.long 0x04 11. " [11] ,Event mask on line 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Event mask on line 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Event mask on line 9" "Masked,Not masked" textline " " bitfld.long 0x04 8. " [8] ,Event mask on line 8" "Masked,Not masked" bitfld.long 0x04 7. " [7] ,Event mask on line 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Event mask on line 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Event mask on line 5" "Masked,Not masked" textline " " bitfld.long 0x04 4. " [4] ,Event mask on line 4" "Masked,Not masked" bitfld.long 0x04 3. " [3] ,Event mask on line 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Event mask on line 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Event mask on line 1" "Masked,Not masked" textline " " bitfld.long 0x04 0. " [0] ,Event mask on line 0" "Masked,Not masked" line.long 0x08 "EXTI_RTSR1,Rising Trigger Selection Register 1" bitfld.long 0x08 22. " RT[22] ,Rising trigger event configuration bit of line 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Rising trigger event configuration bit of line 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Rising trigger event configuration bit of line 20" "Disabled,Enabled" bitfld.long 0x08 19. " [19] ,Rising trigger event configuration bit of line 19" "Disabled,Enabled" textline " " bitfld.long 0x08 18. " [18] ,Rising trigger event configuration bit of line 18" "Disabled,Enabled" bitfld.long 0x08 16. " [16] ,Rising trigger event configuration bit of line 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Rising trigger event configuration bit of line 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Rising trigger event configuration bit of line 14" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " [13] ,Rising trigger event configuration bit of line 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Rising trigger event configuration bit of line 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Rising trigger event configuration bit of line 11" "Disabled,Enabled" bitfld.long 0x08 10. " [10] ,Rising trigger event configuration bit of line 10" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " [9] ,Rising trigger event configuration bit of line 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Rising trigger event configuration bit of line 8" "Disabled,Enabled" bitfld.long 0x08 7. " [7] ,Rising trigger event configuration bit of line 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Rising trigger event configuration bit of line 6" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " [5] ,Rising trigger event configuration bit of line 5" "Disabled,Enabled" bitfld.long 0x08 4. " [4] ,Rising trigger event configuration bit of line 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Rising trigger event configuration bit of line 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Rising trigger event configuration bit of line 2" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " [1] ,Rising trigger event configuration bit of line 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Rising trigger event configuration bit of line 0" "Disabled,Enabled" line.long 0x0C "EXTI_FTSR1,Falling Trigger Selection Register 1" bitfld.long 0x0C 22. " FT[22] ,Falling trigger event configuration bit of line 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Falling trigger event configuration bit of line 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Falling trigger event configuration bit of line 20" "Disabled,Enabled" bitfld.long 0x0C 19. " [19] ,Falling trigger event configuration bit of line 19" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " [18] ,Falling trigger event configuration bit of line 18" "Disabled,Enabled" bitfld.long 0x0C 16. " [16] ,Falling trigger event configuration bit of line 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Falling trigger event configuration bit of line 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Falling trigger event configuration bit of line 14" "Disabled,Enabled" textline " " bitfld.long 0x0C 13. " [13] ,Falling trigger event configuration bit of line 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Falling trigger event configuration bit of line 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Falling trigger event configuration bit of line 11" "Disabled,Enabled" bitfld.long 0x0C 10. " [10] ,Falling trigger event configuration bit of line 10" "Disabled,Enabled" textline " " bitfld.long 0x0C 9. " [9] ,Falling trigger event configuration bit of line 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Falling trigger event configuration bit of line 8" "Disabled,Enabled" bitfld.long 0x0C 7. " [7] ,Falling trigger event configuration bit of line 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Falling trigger event configuration bit of line 6" "Disabled,Enabled" textline " " bitfld.long 0x0C 5. " [5] ,Falling trigger event configuration bit of line 5" "Disabled,Enabled" bitfld.long 0x0C 4. " [4] ,Falling trigger event configuration bit of line 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Falling trigger event configuration bit of line 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Falling trigger event configuration bit of line 2" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " [1] ,Falling trigger event configuration bit of line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Falling trigger event configuration bit of line 0" "Disabled,Enabled" line.long 0x10 "EXTI_SWIER1,Software Interrupt Event Register 1" bitfld.long 0x10 22. " SWI[22] ,Software interrupt on line 22" "No interrupt,Interrupt" bitfld.long 0x10 21. " [21] ,Software interrupt on line 21" "No interrupt,Interrupt" bitfld.long 0x10 20. " [20] ,Software interrupt on line 20" "No interrupt,Interrupt" bitfld.long 0x10 19. " [19] ,Software interrupt on line 19" "No interrupt,Interrupt" textline " " bitfld.long 0x10 18. " [18] ,Software interrupt on line 18" "No interrupt,Interrupt" bitfld.long 0x10 16. " [16] ,Software interrupt on line 16" "No interrupt,Interrupt" bitfld.long 0x10 15. " [15] ,Software interrupt on line 15" "No interrupt,Interrupt" bitfld.long 0x10 14. " [14] ,Software interrupt on line 14" "No interrupt,Interrupt" textline " " bitfld.long 0x10 13. " [13] ,Software interrupt on line 13" "No interrupt,Interrupt" bitfld.long 0x10 12. " [12] ,Software interrupt on line 12" "No interrupt,Interrupt" bitfld.long 0x10 11. " [11] ,Software interrupt on line 11" "No interrupt,Interrupt" bitfld.long 0x10 10. " [10] ,Software interrupt on line 10" "No interrupt,Interrupt" textline " " bitfld.long 0x10 9. " [9] ,Software interrupt on line 9" "No interrupt,Interrupt" bitfld.long 0x10 8. " [8] ,Software interrupt on line 8" "No interrupt,Interrupt" bitfld.long 0x10 7. " [7] ,Software interrupt on line 7" "No interrupt,Interrupt" bitfld.long 0x10 6. " [6] ,Software interrupt on line 6" "No interrupt,Interrupt" textline " " bitfld.long 0x10 5. " [5] ,Software interrupt on line 5" "No interrupt,Interrupt" bitfld.long 0x10 4. " [4] ,Software interrupt on line 4" "No interrupt,Interrupt" bitfld.long 0x10 3. " [3] ,Software interrupt on line 3" "No interrupt,Interrupt" bitfld.long 0x10 2. " [2] ,Software interrupt on line 2" "No interrupt,Interrupt" textline " " bitfld.long 0x10 1. " [1] ,Software interrupt on line 1" "No interrupt,Interrupt" bitfld.long 0x10 0. " [0] ,Software interrupt on line 0" "No interrupt,Interrupt" line.long 0x14 "EXTI_PR1,Pending Register 1" eventfld.long 0x14 22. " PIF[22] ,Pending interrupt flag on line 22" "Not requested,Requested" eventfld.long 0x14 21. " [21] ,Pending interrupt flag on line 21" "Not requested,Requested" eventfld.long 0x14 20. " [20] ,Pending interrupt flag on line 20" "Not requested,Requested" eventfld.long 0x14 19. " [19] ,Pending interrupt flag on line 19" "Not requested,Requested" textline " " eventfld.long 0x14 18. " [18] ,Pending interrupt flag on line 18" "Not requested,Requested" eventfld.long 0x14 16. " [16] ,Pending interrupt flag on line 16" "Not requested,Requested" eventfld.long 0x14 15. " [15] ,Pending interrupt flag on line 15" "Not requested,Requested" eventfld.long 0x14 14. " [14] ,Pending interrupt flag on line 14" "Not requested,Requested" textline " " eventfld.long 0x14 13. " [13] ,Pending interrupt flag on line 13" "Not requested,Requested" eventfld.long 0x14 12. " [12] ,Pending interrupt flag on line 12" "Not requested,Requested" eventfld.long 0x14 11. " [11] ,Pending interrupt flag on line 11" "Not requested,Requested" eventfld.long 0x14 10. " [10] ,Pending interrupt flag on line 10" "Not requested,Requested" textline " " eventfld.long 0x14 9. " [9] ,Pending interrupt flag on line 9" "Not requested,Requested" eventfld.long 0x14 8. " [8] ,Pending interrupt flag on line 8" "Not requested,Requested" eventfld.long 0x14 7. " [7] ,Pending interrupt flag on line 7" "Not requested,Requested" eventfld.long 0x14 6. " [6] ,Pending interrupt flag on line 6" "Not requested,Requested" textline " " eventfld.long 0x14 5. " [5] ,Pending interrupt flag on line 5" "Not requested,Requested" eventfld.long 0x14 4. " [4] ,Pending interrupt flag on line 4" "Not requested,Requested" eventfld.long 0x14 3. " [3] ,Pending interrupt flag on line 3" "Not requested,Requested" eventfld.long 0x14 2. " [2] ,Pending interrupt flag on line 2" "Not requested,Requested" textline " " eventfld.long 0x14 1. " [1] ,Pending interrupt flag on line 1" "Not requested,Requested" eventfld.long 0x14 0. " [0] ,Pending interrupt flag on line 0" "Not requested,Requested" group.long 0x20++0x17 line.long 0x00 "EXTI_IMR2,Interrupt Mask Register 2" sif cpuis("STM32L496*")||cpuis("STM32L4A6*") bitfld.long 0x00 8. " IM[40] ,Interrupt mask on line 40" "Masked,Not masked" textline " " endif bitfld.long 0x00 7. " IM[39] ,Interrupt mask on line 39" "Masked,Not masked" bitfld.long 0x00 6. " [38] ,Interrupt mask on line 38" "Masked,Not masked" bitfld.long 0x00 5. " [37] ,Interrupt mask on line 37" "Masked,Not masked" bitfld.long 0x00 4. " [36] ,Interrupt mask on line 36" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [35] ,Interrupt mask on line 35" "Masked,Not masked" bitfld.long 0x00 2. " [34] ,Interrupt mask on line 34" "Masked,Not masked" bitfld.long 0x00 1. " [33] ,Interrupt mask on line 33" "Masked,Not masked" bitfld.long 0x00 0. " [32] ,Interrupt mask on line 32" "Masked,Not masked" line.long 0x04 "EXTI_EMR2,Event Mask Register 2" sif cpuis("STM32L496*")||cpuis("STM32L4A6*") bitfld.long 0x04 8. " EM[40] ,Event mask on line 40" "Masked,Not masked" textline " " endif bitfld.long 0x04 7. " EM[39] ,Event mask on line 39" "Masked,Not masked" bitfld.long 0x04 6. " [38] ,Event mask on line 38" "Masked,Not masked" bitfld.long 0x04 5. " [37] ,Event mask on line 37" "Masked,Not masked" bitfld.long 0x04 4. " [36] ,Event mask on line 36" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [35] ,Event mask on line 35" "Masked,Not masked" bitfld.long 0x04 2. " [34] ,Event mask on line 34" "Masked,Not masked" bitfld.long 0x04 1. " [33] ,Event mask on line 33" "Masked,Not masked" bitfld.long 0x04 0. " [32] ,Event mask on line 32" "Masked,Not masked" line.long 0x08 "EXTI_RTSR2,Rising Trigger Selection Register 2" bitfld.long 0x08 6. " RT[38] ,Rising trigger event configuration bit of line 38" "Disabled,Enabled" bitfld.long 0x08 5. " [37] ,Rising trigger event configuration bit of line 37" "Disabled,Enabled" bitfld.long 0x08 4. " [36] ,Rising trigger event configuration bit of line 36" "Disabled,Enabled" bitfld.long 0x08 3. " [35] ,Rising trigger event configuration bit of line 35" "Disabled,Enabled" line.long 0x0C "EXTI_FTSR2,Falling Trigger Selection Register 2" bitfld.long 0x0C 6. " FT[38] ,Falling trigger event configuration bit of line 38" "Disabled,Enabled" bitfld.long 0x0C 5. " [37] ,Falling trigger event configuration bit of line 37" "Disabled,Enabled" bitfld.long 0x0C 4. " [36] ,Falling trigger event configuration bit of line 36" "Disabled,Enabled" bitfld.long 0x0C 3. " [35] ,Falling trigger event configuration bit of line 35" "Disabled,Enabled" line.long 0x10 "EXTI_SWIER2,Software Interrupt Event Register 2" bitfld.long 0x10 6. " SWI[38] ,Software interrupt on line 38" "No interrupt,Interrupt" bitfld.long 0x10 5. " [37] ,Software interrupt on line 37" "No interrupt,Interrupt" bitfld.long 0x10 4. " [36] ,Software interrupt on line 36" "No interrupt,Interrupt" bitfld.long 0x10 3. " [35] ,Software interrupt on line 35" "No interrupt,Interrupt" line.long 0x14 "EXTI_PR2,Pending Register 2" eventfld.long 0x14 6. " PIF[38] ,Pending interrupt flag on line 38" "Not requested,Requested" eventfld.long 0x14 5. " [37] ,Pending interrupt flag on line 37" "Not requested,Requested" eventfld.long 0x14 4. " [36] ,Pending interrupt flag on line 36" "Not requested,Requested" eventfld.long 0x14 3. " [35] ,Pending interrupt flag on line 35" "Not requested,Requested" width 0x0B tree.end tree "CRC (Cyclic redundancy check calculation unit)" base ad:0x40023000 width 10. group.long 0x00++0x03 line.long 0x00 "CRC_DR,Data Register" sif (cpuis("STM32L4?3*"))||(cpuis("STM32L4?6*"))||(cpuis("STM32L431*"))||(cpuis("STM32L4?5*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L451*")) group.long 0x04++0x03 line.long 0x00 "CRC_IDR,Independent Data Register" hexmask.long.byte 0x00 0.--7. 1. " IDR ,General-purpose 8-bit data register bits" elif (cpuis("STM32L471*")) group.long 0x04++0x03 line.long 0x00 "CRC_IDR,Independent Data Register" endif group.long 0x08++0x03 line.long 0x00 "CRC_CR,Control Register" bitfld.long 0x00 7. " REV_OUT ,Reverse output data" "Normal,Reversed" bitfld.long 0x00 5.--6. " REV_IN ,Reverse input data" "Normal,Rev by byte,Rev by half-word,Rev by word" bitfld.long 0x00 3.--4. " POLYSIZE ,Polynomial size" "32 bit,16 bit,8 bit,7 bit" bitfld.long 0x00 0. " RESET ,RESET bit" "No reset,Reset" group.long 0x10++0x07 line.long 0x00 "CRC_INIT,Initial CRC Value" line.long 0x04 "CRC_POL,CRC Polynomial" width 0x0B tree.end sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) tree "FSMC (Flexible static memory controller)" base ad:0xA0000000 width 11. tree "NOR/PSRAM" group.long 0x0++0x03 line.long 0x00 "FMC_BCR1,SRAM/NOR-Flash Chip-Select Control Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 21. " WFDIS ,Write FIFO disable" "No,Yes" textline " " endif bitfld.long 0x00 20. " CCLKEN ,Continuous clock enable" "Disabled,Enabled" bitfld.long 0x00 19. " CBURSTRW ,Write burst enable. Enabled synchronous write access" "Asynchronous,Synchronous" bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst split,128B,256B,1024B,?..." textline " " bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "No NWAIT,NWAIT" bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "NWAIT disabled,NWAIT enabled" bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "1cycle before wait state,During wait state" bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high" bitfld.long 0x00 8. " BURSTEN ,Burst enable bit. Enabled synchronous read access" "Disabled,Enabled" bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8b,16b,?..." bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR flash/onenand,?..." bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled" if (((per.l(ad:0xA0000000+0x0))&0x4000)==0x4000) group.long (0x0+0x04)++0x03 line.long 0x00 "FMC_BTR1,SRAM/NOR-Flash Chip-Select Timing Register 1(Read Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x0+0x104)++0x03 line.long 0x00 "FMC_BWTR1,SRAM/NOR-Flash Write Timing Register 1(Write Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x0+0x04)++0x03 line.long 0x00 "FMC_BTR1,SRAM/NOR-Flash Chip-Select Timing Register 1" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long (0x0+0x104)++0x03 hide.long 0x00 "FMC_BWTR1,SRAM/NOR-Flash Write Timing Register 1" endif group.long 0x8++0x03 line.long 0x00 "FMC_BCR2,SRAM/NOR-Flash Chip-Select Control Register 2" bitfld.long 0x00 19. " CBURSTRW ,Write burst enable. Enabled synchronous write access" "Asynchronous,Synchronous" bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst split,128B,256b,1024B,?..." bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "No NWAIT,NWAIT" textline " " bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "NWAIT disabled,NWAIT enabled" bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "1cycle before wait state,During wait state" textline " " bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high" bitfld.long 0x00 8. " BURSTEN ,Burst enable bit. Enabled synchronous read access" "Disabled,Enabled" bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8b,16b,?..." textline " " bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR flash/onenand,?..." bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled" if (((per.l(ad:0xA0000000+0x8))&0x4000)==0x4000) group.long (0x8+0x04)++0x03 line.long 0x00 "FMC_BTR2,SRAM/NOR-Flash Chip-Select Timing Register 2(Read Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x8+0x104)++0x03 line.long 0x00 "FMC_BWTR2,SRAM/NOR-Flash Write Timing Register 2(Write Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x8+0x04)++0x03 line.long 0x00 "FMC_BTR2,SRAM/NOR-Flash Chip-Select Timing Register 2" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long (0x8+0x104)++0x03 hide.long 0x00 "FMC_BWTR2,SRAM/NOR-Flash Write Timing Register 2" endif group.long 0x10++0x03 line.long 0x00 "FMC_BCR3,SRAM/NOR-Flash Chip-Select Control Register 3" bitfld.long 0x00 19. " CBURSTRW ,Write burst enable. Enabled synchronous write access" "Asynchronous,Synchronous" bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst split,128B,256b,1024B,?..." bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "No NWAIT,NWAIT" textline " " bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "NWAIT disabled,NWAIT enabled" bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "1cycle before wait state,During wait state" textline " " bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high" bitfld.long 0x00 8. " BURSTEN ,Burst enable bit. Enabled synchronous read access" "Disabled,Enabled" bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8b,16b,?..." textline " " bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR flash/onenand,?..." bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled" if (((per.l(ad:0xA0000000+0x10))&0x4000)==0x4000) group.long (0x10+0x04)++0x03 line.long 0x00 "FMC_BTR3,SRAM/NOR-Flash Chip-Select Timing Register 3(Read Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x10+0x104)++0x03 line.long 0x00 "FMC_BWTR3,SRAM/NOR-Flash Write Timing Register 3(Write Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x10+0x04)++0x03 line.long 0x00 "FMC_BTR3,SRAM/NOR-Flash Chip-Select Timing Register 3" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long (0x10+0x104)++0x03 hide.long 0x00 "FMC_BWTR3,SRAM/NOR-Flash Write Timing Register 3" endif group.long 0x18++0x03 line.long 0x00 "FMC_BCR4,SRAM/NOR-Flash Chip-Select Control Register 4" bitfld.long 0x00 19. " CBURSTRW ,Write burst enable. Enabled synchronous write access" "Asynchronous,Synchronous" bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst split,128B,256b,1024B,?..." bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "No NWAIT,NWAIT" textline " " bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled" bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "NWAIT disabled,NWAIT enabled" bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "1cycle before wait state,During wait state" textline " " bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Active low,Active high" bitfld.long 0x00 8. " BURSTEN ,Burst enable bit. Enabled synchronous read access" "Disabled,Enabled" bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MWID ,Memory data bus width" "8b,16b,?..." textline " " bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR flash/onenand,?..." bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled" if (((per.l(ad:0xA0000000+0x18))&0x4000)==0x4000) group.long (0x18+0x04)++0x03 line.long 0x00 "FMC_BTR4,SRAM/NOR-Flash Chip-Select Timing Register 4(Read Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x18+0x104)++0x03 line.long 0x00 "FMC_BWTR4,SRAM/NOR-Flash Write Timing Register 4(Write Access)" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x18+0x04)++0x03 line.long 0x00 "FMC_BTR4,SRAM/NOR-Flash Chip-Select Timing Register 4" bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "Mode A,Mode B,Mode C,Mode D" bitfld.long 0x00 24.--27. " DATLAT ,Data latency for synchronous memory" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio (For FMC_CLK signal)" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration" bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long (0x18+0x104)++0x03 hide.long 0x00 "FMC_BWTR4,SRAM/NOR-Flash Write Timing Register 4" endif tree.end tree "NAND Flash" group.long 0x80++0x0F line.long 0x00 "FMC_PCR,NAND Flash Control Register" bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256B,512B,1024B,2048B,4096B,8192B,?..." bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1hclkcyc,2hclkcyc,3hclkcyc,4hclkcyc,5hclkcyc,6hclkcyc,7hclkcyc,8hclkcyc,9hclkcyc,10hclkcyc,11hclkcyc,12hclkcyc,13hclkcyc,14hclkcyc,15hclkcyc,16hclkcyc" bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1hclkcyc,2hclkcyc,3hclkcyc,4hclkcyc,5hclkcyc,6hclkcyc,7hclkcyc,8hclkcyc,9hclkcyc,10hclkcyc,11hclkcyc,12hclkcyc,13hclkcyc,14hclkcyc,15hclkcyc,16hclkcyc" bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--5. " PWID ,Data bus width" "8b,16b,?..." bitfld.long 0x00 3. " PTYP ,Memory type" ",NAND flash" bitfld.long 0x00 2. " PBKEN ,NAND flash memory bank enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled" line.long 0x04 "FMC_SR,FIFO Status And Interrupt Register" rbitfld.long 0x04 6. " FEMPT ,FIFO empty" "Not empty,Empty" bitfld.long 0x04 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled" bitfld.long 0x04 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled" bitfld.long 0x04 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " IFS ,Interrupt falling edge status" "No interrupt,Interrupt" bitfld.long 0x04 1. " ILS ,Interrupt high-level status" "No interrupt,Interrupt" bitfld.long 0x04 0. " IRS ,Interrupt rising edge status" "No interrupt,Interrupt" line.long 0x08 "FMC_PMEM,Common Memory Space Timing Register 2..4" hexmask.long.byte 0x08 24.--31. 1. " MEMHIZ ,Common memory x data bus Hi-Z time" hexmask.long.byte 0x08 16.--23. 1. " MEMHOLD ,Common memory hold time" hexmask.long.byte 0x08 8.--15. 1. " MEMWAIT ,Common memory wait time" hexmask.long.byte 0x08 0.--7. 1. " MEMSET ,Common memory x setup time" line.long 0x0C "FMC_PATT,Attribute Memory Space Timing Register 2..4" hexmask.long.byte 0x0C 24.--31. 1. " ATTHIZ ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0x0C 16.--23. 1. " ATTHOLD ,Attribute memory hold time" hexmask.long.byte 0x0C 8.--15. 1. " ATTWAIT ,Attribute memory wait time" hexmask.long.byte 0x0C 0.--7. 1. " ATTSET ,Attribute memory x setup time" if (((per.l(ad:0xA0000000+0x80))&0xE0000)==0xA0000) rgroup.long 0x94++0x03 line.long 0x00 "FMC_ECCR,ECC Result Register" elif (((per.l(ad:0xA0000000+0x80))&0xE0000)==0x80000) rgroup.long 0x94++0x03 line.long 0x00 "FMC_ECCR,ECC Result Register" hexmask.long 0x00 0.--29. 1. " ECC ,ECC result" elif (((per.l(ad:0xA0000000+0x80))&0xE0000)==0x60000) rgroup.long 0x94++0x03 line.long 0x00 "FMC_ECCR,ECC Result Register" hexmask.long 0x00 0.--27. 1. " ECC ,ECC result" elif (((per.l(ad:0xA0000000+0x80))&0xE0000)==0x40000) rgroup.long 0x94++0x03 line.long 0x00 "FMC_ECCR,ECC Result Register" hexmask.long 0x00 0.--25. 1. " ECC ,ECC result" elif (((per.l(ad:0xA0000000+0x80))&0xE0000)==0x20000) rgroup.long 0x94++0x03 line.long 0x00 "FMC_ECCR,ECC Result Register" hexmask.long.tbyte 0x00 0.--23. 1. " ECC ,ECC result" elif (((per.l(ad:0xA0000000+0x80))&0xE0000)==0x00) rgroup.long 0x94++0x03 line.long 0x00 "FMC_ECCR,ECC Result Register" hexmask.long.tbyte 0x00 0.--21. 1. " ECC ,ECC result" endif tree.end width 0x0B tree.end endif tree "QUADSPI (Quad serial peripheral interface)" base ad:0xA0001000 width 15. if (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x00)&&(((per.l(ad:0xA0001000+0x008)&0x20)==0x00)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x00)&&(((per.l(ad:0xA0001000+0x008)&0x20)==0x20)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Free>=1,Free>=2,Free>=3,Free>=4,Free>=5,Free>=6,Free>=7,Free>=8,Free>=9,Free>=10,Free>=11,Free>=12,Free>=13,Free>=14,Free>=15,Free>=16" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)&&(((per.l(ad:0xA0001000+0x008)&0x20)==0x00)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)&&(((per.l(ad:0xA0001000+0x08)&0x20)==0x20)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "Valid>=1,Valid>=2,Valid>=3,Valid>=4,Valid>=5,Valid>=6,Valid>=7,Valid>=8,Valid>=9,Valid>=10,Valid>=11,Valid>=12,Valid>=13,Valid>=14,Valid>=15,Valid>=16" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)&&(((per.l(ad:0xA0001000+0x008)&0x20)==0x00)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)&&(((per.l(ad:0xA0001000+0x08)&0x20)==0x20)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" rbitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" rbitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x8000000)&&(((per.l(ad:0xA0001000+0x008)&0x20)==0x00)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x8000000)&&(((per.l(ad:0xA0001000+0x08)&0x20)==0x20)) if (((per.l(ad:0xA0001000))&0x40)==0x00) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) rbitfld.long 0x00 6. " DFM ,Dual-flash mode" "Disabled,Enabled" endif textline " " rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif endif if (((per.l(ad:0xA0001000+0x008)&0x20)==0x00)&&((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)||(((per.l(ad:0xA0001000+0x14))&0xC000000)==0x00))) group.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" elif (((per.l(ad:0xA0001000+0x008)&0x20)==0x00)&&(((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)) group.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..." bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" elif (((per.l(ad:0xA0001000+0x008)&0x20)==0x20)&&((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)||(((per.l(ad:0xA0001000+0x14))&0xC000000)==0x00))) rgroup.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" elif (((per.l(ad:0xA0001000+0x08)&0x20)==0x20)&&(((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)) rgroup.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..." bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" endif if ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x00)||(((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)) rgroup.long 0x08++0x03 line.long 0x00 "QUADSPI_SR,QUADSPI Status Register" bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..." bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy" bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout" bitfld.long 0x00 3. " SMF ,Status match flag" "No match,Match" textline " " bitfld.long 0x00 2. " FTF ,FIFO threshold flag" "Thr not reached,Thr reached" bitfld.long 0x00 1. " TCF ,Transfer complete flag" "Not transferred,Transferred" bitfld.long 0x00 0. " TEF ,Transfer error flag" "No error,Error" else rgroup.long 0x08++0x03 line.long 0x00 "QUADSPI_SR,QUADSPI Status Register" bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,?..." bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy" bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout" bitfld.long 0x00 3. " SMF ,Status match flag" "No match,Match" textline " " bitfld.long 0x00 2. " FTF ,Set every time the status register is read" "Clear,Set" bitfld.long 0x00 1. " TCF ,Transfer has been aborted" "Not aborted,Aborted" bitfld.long 0x00 0. " TEF ,Transfer error flag" "No error,Error" endif wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 3. " CSMF ,Clear status match flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" bitfld.long 0x00 0. " CTEF ,Clear transfer error flag" "No effect,Clear" if ((per.l(ad:0xA0001000+0x008)&0x20)==0x00) group.long 0x10++0x03 line.long 0x00 "QUADSPI_DLR,QUADSPI Data Length Register" if (((per.l(ad:0xA0001000+0x14))&0x80000000)==0x80000000) group.long 0x14++0x03 line.long 0x00 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x00 31. " DDRM ,Double data rate mode" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 30. " DHHC ,DDR hold" "Analog delay,1/4 of a QUADSPI output clock cycle" endif textline " " bitfld.long 0x00 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x00 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" textline " " bitfld.long 0x00 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" bitfld.long 0x00 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x00 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" textline " " bitfld.long 0x00 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" bitfld.long 0x00 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" bitfld.long 0x00 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x00 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" else group.long 0x14++0x03 line.long 0x00 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x00 31. " DDRM ,Double data rate mode" "Disabled,Enabled" bitfld.long 0x00 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x00 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" bitfld.long 0x00 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" textline " " bitfld.long 0x00 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x00 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" bitfld.long 0x00 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" textline " " bitfld.long 0x00 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" bitfld.long 0x00 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x00 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" endif else rgroup.long 0x10++0x03 line.long 0x00 "QUADSPI_DLR,QUADSPI Data Length Register" if (((per.l(ad:0xA0001000+0x14))&0x80000000)==0x80000000) rgroup.long 0x14++0x03 line.long 0x00 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x00 31. " DDRM ,Double data rate mode" "Disabled,Enabled" textline " " sif (!cpuis("STM32L471*")) bitfld.long 0x00 30. " DHHC ,DDR hold" "Analog delay,1/4 of a QUADSPI output clock cycle" endif textline " " bitfld.long 0x00 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x00 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" textline " " bitfld.long 0x00 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" bitfld.long 0x00 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x00 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" textline " " bitfld.long 0x00 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" bitfld.long 0x00 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" bitfld.long 0x00 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x00 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" else rgroup.long 0x14++0x03 line.long 0x00 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x00 31. " DDRM ,Double data rate mode" "Disabled,Enabled" bitfld.long 0x00 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x00 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" bitfld.long 0x00 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" textline " " bitfld.long 0x00 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x00 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" bitfld.long 0x00 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" textline " " bitfld.long 0x00 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" bitfld.long 0x00 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x00 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" endif endif if (((per.l(ad:0xA0001000+0x008)&0x20)==0x00)||(((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)) rgroup.long 0x18++0x03 line.long 0x00 "QUADSPI_AR,QUADSPI Address Register" else group.long 0x18++0x03 line.long 0x00 "QUADSPI_AR,QUADSPI Address Register" endif if ((per.l(ad:0xA0001000+0x008)&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "QUADSPI_ABR,QUADSPI Alternate Bytes Register" else rgroup.long 0x1C++0x03 line.long 0x00 "QUADSPI_ABR,QUADSPI Alternate Bytes Register" endif group.long 0x20++0x03 line.long 0x00 "QUADSPI_DR,QUADSPI Data Register" if ((per.l(ad:0xA0001000+0x008)&0x20)==0x00) group.long 0x24++0x0F line.long 0x00 "QUADSPI_PSMKR,QUADSPI Polling Status Mask Register" bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MASK[30] ,Status mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MASK[29] ,Status mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MASK[28] ,Status mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MASK[27] ,Status mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MASK[26] ,Status mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MASK[25] ,Status mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MASK[24] ,Status mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MASK[23] ,Status mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MASK[22] ,Status mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MASK[21] ,Status mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MASK[20] ,Status mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MASK[19] ,Status mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MASK[18] ,Status mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MASK[17] ,Status mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MASK[16] ,Status mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MASK[15] ,Status mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MASK[14] ,Status mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MASK[13] ,Status mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MASK[12] ,Status mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MASK[11] ,Status mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MASK[10] ,Status mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MASK[9] ,Status mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MASK[8] ,Status mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MASK[7] ,Status mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MASK[6] ,Status mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MASK[5] ,Status mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MASK[4] ,Status mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MASK[3] ,Status mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MASK[2] ,Status mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MASK[1] ,Status mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MASK[0] ,Status mask bit 0" "Masked,Not masked" line.long 0x04 "QUADSPI_PSMAR,QUADSPI Polling Status Match Register" line.long 0x08 "QUADSPI_PIR,QUADSPI Polling Interval Register" hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval" line.long 0x0C "QUADSPI_LPTR,QUADSPI low-power Timeout Register" hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period" else rgroup.long 0x24++0x0F line.long 0x00 "QUADSPI_PSMKR,QUADSPI Polling Status Mask Register" bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MASK[30] ,Status mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MASK[29] ,Status mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MASK[28] ,Status mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MASK[27] ,Status mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MASK[26] ,Status mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MASK[25] ,Status mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MASK[24] ,Status mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MASK[23] ,Status mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MASK[22] ,Status mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MASK[21] ,Status mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MASK[20] ,Status mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MASK[19] ,Status mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MASK[18] ,Status mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MASK[17] ,Status mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MASK[16] ,Status mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MASK[15] ,Status mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MASK[14] ,Status mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MASK[13] ,Status mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MASK[12] ,Status mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MASK[11] ,Status mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MASK[10] ,Status mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MASK[9] ,Status mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MASK[8] ,Status mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MASK[7] ,Status mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MASK[6] ,Status mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MASK[5] ,Status mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MASK[4] ,Status mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MASK[3] ,Status mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MASK[2] ,Status mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MASK[1] ,Status mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MASK[0] ,Status mask bit 0" "Masked,Not masked" line.long 0x04 "QUADSPI_PSMAR,QUADSPI Polling Status Match Register" line.long 0x08 "QUADSPI_PIR,QUADSPI Polling Interval Register" hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval" line.long 0x0C "QUADSPI_LPTR,QUADSPI Low-Power Timeout Register" hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period" endif width 0x0B tree.end sif (cpuis("STM32L432*"))||(cpuis("STM32L433*"))||(cpuis("STM32L431*"))||(cpuis("STM32L443*"))||(cpuis("STM32L442KC"))||(cpuis("STM32L462*"))||(cpuis("STM32L452*"))||(cpuis("STM32L451*")) tree "ADC (Analog-to-digital converters)" base ad:0x50040000 width 15. tree "Master ADC1" group.long 0x00++0x03 line.long 0x00 "ADC1_ISR,ADC interrupt and status register" eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not injected,Injected" eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred" eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred" eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed" eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed" eventfld.long 0x00 4. " OVR ,ADC overrun" "No overrun,Overrun" eventfld.long 0x00 3. " EOS ,End of regular sequence flag" "Not completed,Completed" textline " " eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed" eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not ended,Ended" eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready" if (((per.l(ad:0x50040000+0x08))&0xC)==0x00) group.long 0x04++0x03 line.long 0x00 "ADC1_IER,ADC interrupt enable register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x08))&0xC)==0x8) group.long 0x04++0x03 line.long 0x00 "ADC1_IER,ADC interrupt enable register" rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x08))&0xC)==0x4) group.long 0x04++0x03 line.long 0x00 "ADC1_IER,ADC interrupt enable register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" else rgroup.long 0x04++0x03 line.long 0x00 "ADC1_IER,ADC interrupt enable register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" endif group.long 0x08++0x03 line.long 0x00 "ADC1_CR,ADC control register" bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Complete,In progress" bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended inputs,Differential inputs" bitfld.long 0x00 29. " DEEPPWD ,Deep-power-down enable" "Not deep-power-down,Deep-power-down" bitfld.long 0x00 28. " ADVREGEN ,ADC voltage regulator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No stop,Stop" bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No stop,Stop" bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No ongoing,Start" bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion" "No ongoing,Start" textline " " bitfld.long 0x00 1. " ADDIS ,ADC disable command" "Enabled,Disabled" bitfld.long 0x00 0. " ADEN ,ADC enable control" "Disabled,Enabled" if (((per.l(ad:0x50040000+0x08))&0xC)==0x00) group.long 0x0C++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" bitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" bitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x08))&0xC)==0x8) group.long 0x0C++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x08))&0xC)==0x4) group.long 0x0C++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x08))&0xC)==0x00) group.long 0x10++0x03 line.long 0x00 "ADC1_CFGR2,ADC configuration register 2" bitfld.long 0x00 10. " ROVSM ,Regular Oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered Regular Oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2,4,8,16,32,64,128,256" textline " " bitfld.long 0x00 1. " JOVSE ,Injected Oversampling Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular Oversampling Enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x08))&0xC)==0x8) group.long 0x10++0x03 line.long 0x00 "ADC1_CFGR2,ADC configuration register 2" bitfld.long 0x00 10. " ROVSM ,Regular Oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered Regular Oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2,4,8,16,32,64,128,256" textline " " rbitfld.long 0x00 1. " JOVSE ,Injected Oversampling Enable" "Disabled,Enabled" rbitfld.long 0x00 0. " ROVSE ,Regular Oversampling Enable" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "ADC1_CFGR2,ADC configuration register 2" bitfld.long 0x00 10. " ROVSM ,Regular Oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered Regular Oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2,4,8,16,32,64,128,256" textline " " bitfld.long 0x00 1. " JOVSE ,Injected Oversampling Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular Oversampling Enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x08))&0xC)==0x00) group.long 0x14++0x07 line.long 0x00 "ADC1_SMPR1,ADC sample time register 1" bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " SMP[8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " SMP[7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " SMP[6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " SMP[5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " SMP[4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " SMP[3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " SMP[2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " SMP[1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " SMP[0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC1_SMPR2,ADC sample time register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " SMP[17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " SMP[16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " SMP[15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " SMP[14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " SMP[13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " SMP[12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " SMP[11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " SMP[10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" group.long 0x20++0x0b line.long 0x00 "ADC1_TR1,ADC watchdog threshold register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC1_TR2,ADC watchdog threshold register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC1_TR3,ADC watchdog threshold register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" else rgroup.long 0x14++0x07 line.long 0x00 "ADC1_SMPR1,ADC sample time register 1" bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " SMP[8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " SMP[7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " SMP[6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " SMP[5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " SMP[4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " SMP[3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " SMP[2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " SMP[1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " SMP[0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC1_SMPR2,ADC sample time register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " SMP[17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " SMP[16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " SMP[15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " SMP[14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " SMP[13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " SMP[12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " SMP[11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " SMP[10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" rgroup.long 0x20++0x0b line.long 0x00 "ADC1_TR1,ADC watchdog threshold register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC1_TR2,ADC watchdog threshold register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC1_TR3,ADC watchdog threshold register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" endif if (((per.l(ad:0x50040000+0x08))&0x04)==0x00) sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) group.long 0x30++0x0f line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." line.long 0x0c "ADC1_SQR4,ADC regular sequence register 4" bitfld.long 0x0c 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x0c 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." elif (cpuis("STM32L432*")) group.long 0x30++0x0f line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." line.long 0x0c "ADC1_SQR4,ADC regular sequence register 4" bitfld.long 0x0c 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x0c 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." else group.long 0x30++0x0f line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0c "ADC1_SQR4,ADC regular sequence register 4" bitfld.long 0x0c 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0c 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif else sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) rgroup.long 0x30++0x0f line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." line.long 0x0c "ADC1_SQR4,ADC regular sequence register 4" bitfld.long 0x0c 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x0c 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." elif (cpuis("STM32L432*")) rgroup.long 0x30++0x0f line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." line.long 0x0c "ADC1_SQR4,ADC regular sequence register 4" bitfld.long 0x0c 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x0c 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." else rgroup.long 0x30++0x0f line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0c "ADC1_SQR4,ADC regular sequence register 4" bitfld.long 0x0c 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0c 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif endif rgroup.long 0x40++0x03 line.long 0x00 "ADC1_DR,ADC regular Data Register" hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular Data converted" if (((per.l(ad:0x50040000+0x0c))&0x80000000)==0x0)&&(((per.l(ad:0x50040000+0x08))&0x01)==0x01) group.long 0x4c++0x03 line.long 0x00 "ADC1_JSQR,ADC injected sequence register" sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " elif (cpuis("STM32L432*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" elif (((per.l(ad:0x50040000+0x0c))&0x80000000)==0x0)&&(((per.l(ad:0x50040000+0x08))&0x01)==0x00) rgroup.long 0x4c++0x03 line.long 0x00 "ADC1_JSQR,ADC injected sequence register" sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " elif (cpuis("STM32L432*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" elif (((per.l(ad:0x50040000+0x0c))&0x80000000)==0x80000000)&&(((per.l(ad:0x50040000+0x08))&0x01)==0x01) group.long 0x4c++0x03 line.long 0x00 "ADC1_JSQR,ADC injected sequence register" sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " elif (cpuis("STM32L432*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Software,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" else rgroup.long 0x4c++0x03 line.long 0x00 "ADC1_JSQR,ADC injected sequence register" sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." textline " " elif (cpuis("STM32L432*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Software,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" endif if (((per.l(ad:0x50040000+0x08))&0xC)==0x00) sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) group.long 0x60++0x0f line.long 0x00 "ADC1_OFR1,ADC offset register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC offset register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC offset register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC offset register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" elif (cpuis("STM32L432*")) group.long 0x60++0x0f line.long 0x00 "ADC1_OFR1,ADC offset register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC offset register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC offset register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC offset register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" else group.long 0x60++0x0f line.long 0x00 "ADC1_OFR1,ADC offset register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC offset register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC offset register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC offset register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" endif else sif (cpuis("STM32L433C*"))||(cpuis("STM32L431C*")) rgroup.long 0x60++0x0f line.long 0x00 "ADC1_OFR1,ADC offset register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC offset register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC offset register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC offset register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,18,?..." hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" elif (cpuis("STM32L432*")) rgroup.long 0x60++0x0f line.long 0x00 "ADC1_OFR1,ADC offset register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC offset register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC offset register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC offset register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,,,,,,,17,?..." hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" else rgroup.long 0x60++0x0f line.long 0x00 "ADC1_OFR1,ADC offset register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC offset register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC offset register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC offset register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" endif endif rgroup.long 0x80++0x0f line.long 0x00 "ADC1_JDR1,ADC injected data register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" line.long 0x04 "ADC1_JDR2,ADC injected data register 2" hexmask.long.word 0x04 0.--15. 1. " JDATA ,Injected data" line.long 0x08 "ADC1_JDR3,ADC injected data register 3" hexmask.long.word 0x08 0.--15. 1. " JDATA ,Injected data" line.long 0x0C "ADC1_JDR4,ADC injected data register 4" hexmask.long.word 0x0C 0.--15. 1. " JDATA ,Injected data" if (((per.l(ad:0x50040000+0x08))&0xC)==0x00) group.long 0xA0++0x07 line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 18. " AWD2CH[18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " AWD2CH[17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " AWD2CH[16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " AWD2CH[15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 14. " AWD2CH[14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " AWD2CH[13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " AWD2CH[12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " AWD2CH[11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 10. " AWD2CH[10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " AWD2CH[9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " AWD2CH[8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " AWD2CH[7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 6. " AWD2CH[6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " AWD2CH[5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " AWD2CH[4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " AWD2CH[3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 2. " AWD2CH[2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " AWD2CH[1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x00 0. " AWD2CH[0] ,Analog watchdog 2 channel 0 selection" "Not monitored,Monitored" line.long 0x04 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 18. " AWD3CH[18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " AWD3CH[17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " AWD3CH[16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " AWD3CH[15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 14. " AWD3CH[14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " AWD3CH[13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " AWD3CH[12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " AWD3CH[11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 10. " AWD3CH[10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " AWD3CH[9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " AWD3CH[8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " AWD3CH[7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 6. " AWD3CH[6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " AWD3CH[5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " AWD3CH[4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " AWD3CH[3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 2. " AWD3CH[2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " AWD3CH[1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x04 0. " AWD3CH[0] ,Analog watchdog 3 channel 0 selection" "Not monitored,Monitored" else rgroup.long 0xA0++0x07 line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 18. " AWD2CH[18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " AWD2CH[17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " AWD2CH[16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " AWD2CH[15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 14. " AWD2CH[14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " AWD2CH[13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " AWD2CH[12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " AWD2CH[11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 10. " AWD2CH[10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " AWD2CH[9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " AWD2CH[8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " AWD2CH[7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 6. " AWD2CH[6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " AWD2CH[5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " AWD2CH[4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " AWD2CH[3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 2. " AWD2CH[2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " AWD2CH[1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x00 0. " AWD2CH[0] ,Analog watchdog 2 channel 0 selection" "Not monitored,Monitored" line.long 0x04 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 18. " AWD3CH[18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " AWD3CH[17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " AWD3CH[16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " AWD3CH[15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 14. " AWD3CH[14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " AWD3CH[13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " AWD3CH[12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " AWD3CH[11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 10. " AWD3CH[10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " AWD3CH[9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " AWD3CH[8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " AWD3CH[7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 6. " AWD3CH[6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " AWD3CH[5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " AWD3CH[4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " AWD3CH[3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 2. " AWD3CH[2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " AWD3CH[1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x04 0. " AWD3CH[0] ,Analog watchdog 3 channel 0 selection" "Not monitored,Monitored" endif group.long 0xb0++0x03 line.long 0x00 "ADC1_DIFSEL,ADC Differential Mode Selection Register" sif (!cpuis("STM32L432*")) rbitfld.long 0x00 18. " DIFSEL[18] ,Differential mode for channel 18" "Single-ended,?..." textline " " endif rbitfld.long 0x00 17. " DIFSEL[17] ,Differential mode for channel 17" "Single-ended,?..." textline " " sif (!cpuis("STM32L433C*"))&&(!cpuis("STM32L431C*"))&&(!cpuis("STM32L432*")) rbitfld.long 0x00 16. " DIFSEL[16] ,Differential mode for channel 16" "Single-ended,?..." bitfld.long 0x00 15. " DIFSEL[15] ,Differential mode for channel 15" "Single-ended,Differential" bitfld.long 0x00 14. " DIFSEL[14] ,Differential mode for channel 14" "Single-ended,Differential" bitfld.long 0x00 13. " DIFSEL[13] ,Differential mode for channel 13" "Single-ended,Differential" textline " " bitfld.long 0x00 12. " DIFSEL[12] ,Differential mode for channel 12" "Single-ended,Differential" bitfld.long 0x00 11. " DIFSEL[11] ,Differential mode for channel 11" "Single-ended,Differential" textline " " endif bitfld.long 0x00 10. " DIFSEL[10] ,Differential mode for channel 10" "Single-ended,Differential" bitfld.long 0x00 9. " DIFSEL[9] ,Differential mode for channel 9" "Single-ended,Differential" bitfld.long 0x00 8. " DIFSEL[8] ,Differential mode for channel 8" "Single-ended,Differential" bitfld.long 0x00 7. " DIFSEL[7] ,Differential mode for channel 7" "Single-ended,Differential" textline " " bitfld.long 0x00 6. " DIFSEL[6] ,Differential mode for channel 6" "Single-ended,Differential" bitfld.long 0x00 5. " DIFSEL[5] ,Differential mode for channel 5" "Single-ended,Differential" bitfld.long 0x00 4. " DIFSEl[4] ,Differential mode for channel 4" "Single-ended,Differential" bitfld.long 0x00 3. " DIFSEL[3] ,Differential mode for channel 3" "Single-ended,Differential" textline " " bitfld.long 0x00 2. " DIFSEL[2] ,Differential mode for channel 2" "Single-ended,Differential" bitfld.long 0x00 1. " DIFSEL[1] ,Differential mode for channel 1" "Single-ended,Differential" rbitfld.long 0x00 0. " DIFSEL[0] ,Differential mode for channel 0" "Single-ended,?..." if (((per.l(ad:0x50040000+0x08))&0xD)==0x01) group.long 0xb4++0x03 line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors" hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D[6:0] ,Calibration Factors in differential mode" hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S[6:0] ,Calibration Factors in Single-Ended mode" else rgroup.long 0xb4++0x03 line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors" hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D[6:0] ,Calibration Factors in differential mode" hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S[6:0] ,Calibration Factors in Single-Ended mode" endif tree.end width 12. tree "ADC common registers" rgroup.long 0x300++0x03 line.long 0x00 "ADC1_CSR,ADC Common status register" bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "Not overflowed,Overflowed" bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Not occurred,Occurred" bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Not occurred,Occurred" bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Not ended,Ended" bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Not ended,Ended" bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun" bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Not ended,Ended" textline " " bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Not ended,Ended" bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Not ended,Ended" bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready" if (((per.l(ad:0x50040000+0x08))&0x1000001F)==0x00) group.long 0x308++0x03 line.long 0x00 "ADC1_CCR,ADC common control register" sif (!cpuis("STM32L4?2*")) bitfld.long 0x00 24. " CH18SEL ,CH18 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " CH17SEL ,CH17 selection" "Disabled,Enabled" bitfld.long 0x00 22. " VREFEN ,VREFINT enable" "Disabled,Enabled" bitfld.long 0x00 18.--21. " PRESC ,ADC prescaler" "Not div,2,4,6,8,10,12,16,32,64,128,256,?..." bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "CK_ADC,HCLK/1,HCLK/2,HCLK/4" else group.long 0x308++0x03 line.long 0x00 "ADC1_CCR,ADC common control register" sif (!cpuis("STM32L4?2*")) bitfld.long 0x00 24. " CH18SEL ,CH18 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " CH17SEL ,CH17 selection" "Disabled,Enabled" bitfld.long 0x00 22. " VREFEN ,VREFINT enable" "Disabled,Enabled" rbitfld.long 0x00 18.--21. " PRESC ,ADC prescaler" "Not div,2,4,6,8,10,12,16,32,64,128,256,?..." rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "CK_ADC,HCLK/1,HCLK/2,HCLK/4" endif sif (!cpuis("STM32L43*"))&&(!cpuis("STM32L44*"))&&(!cpuis("STM32L45*"))&&(!cpuis("STM32L46*")) rgroup.long 0x30c++0x03 line.long 0x00 "ADC1_CDR,ADC common regular data register for dual mode" hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC" hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC" endif tree.end width 0x0B tree.end else tree "ADC (Analog-to-digital converters)" base ad:0x50040000 width 15. tree "Master ADC1" group.long 0x0++0x03 line.long 0x00 "ADC1_ISR,ADC Interrupt and Status Register" eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not injected,Injected" eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred" eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred" eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed" eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed" eventfld.long 0x00 4. " OVR ,ADC overrun" "No overrun,Overrun" eventfld.long 0x00 3. " EOS ,End of regular sequence flag" "Not complete,Completed" textline " " eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not complete,Completed" eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not ended,Ended" eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready" if (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x00) group.long (0x0+0x04)++0x03 line.long 0x00 "ADC1_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x8) group.long (0x0+0x04)++0x03 line.long 0x00 "ADC1_IER,ADC Interrupt Enable Register" rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x4) group.long (0x0+0x04)++0x03 line.long 0x00 "ADC1_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" else rgroup.long (0x0+0x04)++0x03 line.long 0x00 "ADC1_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" endif group.long (0x0+0x08)++0x03 line.long 0x00 "ADC1_CR,ADC Control Register" bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Complete,In progress" bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended inputs,Differential inputs" bitfld.long 0x00 29. " DEEPPWD ,Deep-power-down enable" "Not deep-power-down,Deep-power-down" bitfld.long 0x00 28. " ADVREGEN ,ADC voltage regulator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No stop,Stop" bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No stop,Stop" bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No ongoing,Start" bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion" "No ongoing,Start" textline " " bitfld.long 0x00 1. " ADDIS ,ADC disable command" "Enabled,Disabled" bitfld.long 0x00 0. " ADEN ,ADC enable control" "Disabled,Enabled" if (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x00) group.long (0x0+0x0C)++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" bitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x8) group.long (0x0+0x0C)++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x4) group.long (0x0+0x0C)++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" else group.long (0x0+0x0C)++0x03 line.long 0x00 "ADC1_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " a " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" "ADC ch-0,ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "ADC1_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " bitfld.long 0x00 1. " JOVSE ,Injected oversampling enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x8) group.long (0x0+0x10)++0x03 line.long 0x00 "ADC1_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " rbitfld.long 0x00 1. " JOVSE ,Injected oversampling Enable" "Disabled,Enabled" rbitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "ADC1_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " bitfld.long 0x00 1. " JOVSE ,Injected oversampling enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x00) group.long (0x0+0x14)++0x07 line.long 0x00 "ADC1_SMPR1,ADC Sample Time Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 31. " SMPPLUS ,Addition of one clock cycle to the sampling time" "2.5cc,3.5cc" textline " " endif bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " [8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " [7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " [6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " [5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " [4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " [3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " [2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " [1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " [0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC1_SMPR2,ADC Sample Time Register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " [17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " [16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " [15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " [14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " [13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " [12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " [11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " [10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" group.long (0x0+0x20)++0x0B line.long 0x00 "ADC1_TR1,ADC Watchdog Threshold Register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC1_TR2,ADC Watchdog Threshold Register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC1_TR3,ADC Watchdog Threshold Register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" else rgroup.long (0x0+0x14)++0x07 line.long 0x00 "ADC1_SMPR1,ADC Sample Time Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 31. " SMPPLUS ,Addition of one clock cycle to the sampling time" "2.5cc,3.5cc" textline " " endif bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " [8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " [7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " [6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " [5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " [4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " [3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " [2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " [1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " [0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC1_SMPR2,ADC Sample Time Register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " [17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " [16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " [15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " [14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " [13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " [12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " [11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " [10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" rgroup.long (0x0+0x20)++0x0B line.long 0x00 "ADC1_TR1,ADC Watchdog Threshold Register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC1_TR2,ADC Watchdog Threshold Register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC1_TR3,ADC Watchdog Threshold Register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" endif if (((per.l(ad:0x50040000+0x0+0x08))&0x04)==0x00) group.long (0x0+0x30)++0x0F line.long 0x00 "ADC1_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC1_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC1_SQR4,ADC Regular Sequence Register 4" bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." else rgroup.long (0x0+0x30)++0x0F line.long 0x00 "ADC1_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC1_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC1_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC1_SQR4,ADC Regular Sequence Register 4" bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif rgroup.long (0x0+0x40)++0x03 line.long 0x00 "ADC1_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular data converted" if (((per.l(ad:0x50040000+0x0+0x0C))&0x80000000)==0x0) group.long (0x0+0x4C)++0x03 line.long 0x00 "ADC1_JSQR,ADC Injected Sequence Register" sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " elif (cpuis("STM32L476Z*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External trigger enable and polarity selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External trigger selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" else group.long (0x0+0x4C)++0x03 line.long 0x00 "ADC1_JSQR,ADC Injected Sequence Register" sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " elif (cpuis("STM32L476Z*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Software,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" endif if (((per.l(ad:0x50040000+0x0+0x08))&0xC)==0x00) group.long (0x0+0x60)++0x0F line.long 0x00 "ADC1_OFR1,ADC Offset Register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC Offset Register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC Offset Register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC1_OFR4,ADC Offset Register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" else rgroup.long (0x0+0x60)++0x0F line.long 0x00 "ADC1_OFR1,ADC Offset Register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC1_OFR2,ADC Offset Register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC1_OFR3,ADC Offset Register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC$_OFR4,ADC Offset Register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" endif rgroup.long (0x0+0x80)++0x0F line.long 0x00 "ADC1_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" line.long 0x04 "ADC1_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x04 0.--15. 1. " JDATA ,Injected data" line.long 0x08 "ADC1_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x08 0.--15. 1. " JDATA ,Injected data" line.long 0x0C "ADC1_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x0C 0.--15. 1. " JDATA ,Injected data" textline " " sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long (0x0+0xA0)++0x07 line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 18. " AWD2CH[18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " [17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " [16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x00 0. " [0] ,Analog watchdog 2 channel 0 selection" "Not monitored,Monitored" line.long 0x04 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 18. " AWD3CR[18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " [17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " [16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x04 0. " [0] ,Analog watchdog 3 channel 0 selection" "Not monitored,Monitored" elif (CPUIS("STM32L476Z*")) group.long (0x0+0xA0)++0x07 line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 23. " AWD2CH[23] ,Analog watchdog 2 channel 23 selection" "Not monitored,Monitored" bitfld.long 0x00 22. " [22] ,Analog watchdog 2 channel 22 selection" "Not monitored,Monitored" bitfld.long 0x00 21. " [21] ,Analog watchdog 2 channel 21 selection" "Not monitored,Monitored" bitfld.long 0x00 20. " [20] ,Analog watchdog 2 channel 20 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 19. " [19] ,Analog watchdog 2 channel 19 selection" "Not monitored,Monitored" bitfld.long 0x00 18. " [18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " [17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " [16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" line.long 0x04 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 23. " AWD3CH[23] ,Analog watchdog 3 channel 23 selection" "Not monitored,Monitored" bitfld.long 0x04 22. " [22] ,Analog watchdog 3 channel 22 selection" "Not monitored,Monitored" bitfld.long 0x04 21. " [21] ,Analog watchdog 3 channel 21 selection" "Not monitored,Monitored" bitfld.long 0x04 20. " [20] ,Analog watchdog 3 channel 20 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 19. " [19] ,Analog watchdog 3 channel 19 selection" "Not monitored,Monitored" bitfld.long 0x04 18. " [18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " [17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " [16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" else group.long (0x0+0xA0)++0x07 line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 16. " AWD2CH[16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" line.long 0x04 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 16. " AWD3CR[16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" endif group.long (0x0+0xB0)++0x03 line.long 0x00 "ADC1_DIFSEL,ADC Differential Mode Selection Register" sif (CPUIS("STM32L476Q*")) bitfld.long 0x00 23. " DIFSEL[23] ,Differential mode for channel 23" "Single-ended,Differential" bitfld.long 0x00 22. " [22] ,Differential mode for channel 22" "Single-ended,Differential" bitfld.long 0x00 21. " [21] ,Differential mode for channel 21" "Single-ended,Differential" bitfld.long 0x00 20. " [20] ,Differential mode for channel 20" "Single-ended,Differential" textline " " bitfld.long 0x00 19. " [19] ,Differential mode for channel 19" "Single-ended,Differential" rbitfld.long 0x00 18. " [18] ,Differential mode for channel 18" "Single-ended," rbitfld.long 0x00 17. " [17] ,Differential mode for channel 17" "Single-ended," rbitfld.long 0x00 16. " [16] ,Differential mode for channel 16" "Single-ended," textline " " elif (cpuis("STM32L476Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 18. " DIFSEL[18] ,Differential mode for channel 18" "Single-ended,?..." rbitfld.long 0x00 17. " [17] ,Differential mode for channel 17" "Single-ended,?..." rbitfld.long 0x00 16. " [16] ,Differential mode for channel 16" "Single-ended,?..." textline " " endif bitfld.long 0x00 15. " [15] ,Differential mode for channel 15" "Single-ended,Differential" bitfld.long 0x00 14. " [14] ,Differential mode for channel 14" "Single-ended,Differential" bitfld.long 0x00 13. " [13] ,Differential mode for channel 13" "Single-ended,Differential" bitfld.long 0x00 12. " [12] ,Differential mode for channel 12" "Single-ended,Differential" textline " " bitfld.long 0x00 11. " [11] ,Differential mode for channel 11" "Single-ended,Differential" bitfld.long 0x00 10. " [10] ,Differential mode for channel 10" "Single-ended,Differential" bitfld.long 0x00 9. " [9] ,Differential mode for channel 9" "Single-ended,Differential" bitfld.long 0x00 8. " [8] ,Differential mode for channel 8" "Single-ended,Differential" textline " " bitfld.long 0x00 7. " [7] ,Differential mode for channel 7" "Single-ended,Differential" bitfld.long 0x00 6. " [6] ,Differential mode for channel 6" "Single-ended,Differential" bitfld.long 0x00 5. " [5] ,Differential mode for channel 5" "Single-ended,Differential" bitfld.long 0x00 4. " [4] ,Differential mode for channel 4" "Single-ended,Differential" textline " " bitfld.long 0x00 3. " [3] ,Differential mode for channel 3" "Single-ended,Differential" bitfld.long 0x00 2. " [2] ,Differential mode for channel 2" "Single-ended,Differential" bitfld.long 0x00 1. " [1] ,Differential mode for channel 1" "Single-ended,Differential" rbitfld.long 0x00 0. " [0] ,Differential mode for channel 0" "Single-ended,?..." if (((per.l(ad:0x50040000+0x0+0x08))&0xD)==0x01) group.long (0x0+0xB4)++0x03 line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors" bitfld.long 0x00 22. " CALFACT_D[6] ,Calibration factor 6 in differential mode" "0,1" bitfld.long 0x00 21. " [5] ,Calibration factor 5 in differential mode" "0,1" bitfld.long 0x00 20. " [4] ,Calibration factor 4 in differential mode" "0,1" bitfld.long 0x00 19. " [3] ,Calibration factor 3 in differential mode" "0,1" textline " " bitfld.long 0x00 18. " [2] ,Calibration factor 2 in differential mode" "0,1" bitfld.long 0x00 17. " [1] ,Calibration factor 1 in differential mode" "0,1" bitfld.long 0x00 16. " [0] ,Calibration factor 0 in differential mode" "0,1" bitfld.long 0x00 6. " CALFACT_S[6] ,Calibration factor 6 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Calibration factor 5 in Single-Ended mode" "0,1" bitfld.long 0x00 4. " [4] ,Calibration factor 4 in Single-Ended mode" "0,1" bitfld.long 0x00 3. " [3] ,Calibration factor 3 in Single-Ended mode" "0,1" bitfld.long 0x00 2. " [2] ,Calibration factor 2 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 1. " [1] ,Calibration factor 1 in Single-Ended mode" "0,1" bitfld.long 0x00 0. " [0] ,Calibration factor 0 in Single-Ended mode" "0,1" else rgroup.long (0x0+0xb4)++0x03 line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors" bitfld.long 0x00 22. " CALFACT_D[6] ,Calibration factor 6 in differential mode" "0,1" bitfld.long 0x00 21. " [5] ,Calibration factor 5 in differential mode" "0,1" bitfld.long 0x00 20. " [4] ,Calibration factor 4 in differential mode" "0,1" bitfld.long 0x00 19. " [3] ,Calibration factor 3 in differential mode" "0,1" textline " " bitfld.long 0x00 18. " [2] ,Calibration factor 2 in differential mode" "0,1" bitfld.long 0x00 17. " [1] ,Calibration factor 1 in differential mode" "0,1" bitfld.long 0x00 16. " [0] ,Calibration factor 0 in differential mode" "0,1" textline " " bitfld.long 0x00 6. " CALFACT_S[6] ,Calibration factor 6 in Single-Ended mode" "0,1" bitfld.long 0x00 5. " [5] ,Calibration factor 5 in Single-Ended mode" "0,1" bitfld.long 0x00 4. " [4] ,Calibration factor 4 in Single-Ended mode" "0,1" bitfld.long 0x00 3. " [3] ,Calibration factor 3 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Calibration factor 2 in Single-Ended mode" "0,1" bitfld.long 0x00 1. " [1] ,Calibration factor 1 in Single-Ended mode" "0,1" bitfld.long 0x00 0. " [0] ,Calibration factor 0 in Single-Ended mode" "0,1" endif tree.end tree "Slave ADC2" group.long 0x100++0x03 line.long 0x00 "ADC2_ISR,ADC Interrupt and Status Register" eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not injected,Injected" eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred" eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred" eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed" eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed" eventfld.long 0x00 4. " OVR ,ADC overrun" "No overrun,Overrun" eventfld.long 0x00 3. " EOS ,End of regular sequence flag" "Not complete,Completed" textline " " eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not complete,Completed" eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not ended,Ended" eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready" if (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x00) group.long (0x100+0x04)++0x03 line.long 0x00 "ADC2_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x8) group.long (0x100+0x04)++0x03 line.long 0x00 "ADC2_IER,ADC Interrupt Enable Register" rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x4) group.long (0x100+0x04)++0x03 line.long 0x00 "ADC2_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" else rgroup.long (0x100+0x04)++0x03 line.long 0x00 "ADC2_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" endif group.long (0x100+0x08)++0x03 line.long 0x00 "ADC2_CR,ADC Control Register" bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Complete,In progress" bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended inputs,Differential inputs" bitfld.long 0x00 29. " DEEPPWD ,Deep-power-down enable" "Not deep-power-down,Deep-power-down" bitfld.long 0x00 28. " ADVREGEN ,ADC voltage regulator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No stop,Stop" bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No stop,Stop" bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No ongoing,Start" bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion" "No ongoing,Start" textline " " bitfld.long 0x00 1. " ADDIS ,ADC disable command" "Enabled,Disabled" bitfld.long 0x00 0. " ADEN ,ADC enable control" "Disabled,Enabled" if (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x00) group.long (0x100+0x0C)++0x03 line.long 0x00 "ADC2_CFGR,ADC configuration register" bitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x8) group.long (0x100+0x0C)++0x03 line.long 0x00 "ADC2_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x4) group.long (0x100+0x0C)++0x03 line.long 0x00 "ADC2_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" else group.long (0x100+0x0C)++0x03 line.long 0x00 "ADC2_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " a " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x00) group.long (0x100+0x10)++0x03 line.long 0x00 "ADC2_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " bitfld.long 0x00 1. " JOVSE ,Injected oversampling enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x8) group.long (0x100+0x10)++0x03 line.long 0x00 "ADC2_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " rbitfld.long 0x00 1. " JOVSE ,Injected oversampling Enable" "Disabled,Enabled" rbitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" else rgroup.long (0x100+0x10)++0x03 line.long 0x00 "ADC2_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " bitfld.long 0x00 1. " JOVSE ,Injected oversampling enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x00) group.long (0x100+0x14)++0x07 line.long 0x00 "ADC2_SMPR1,ADC Sample Time Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 31. " SMPPLUS ,Addition of one clock cycle to the sampling time" "2.5cc,3.5cc" textline " " endif bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " [8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " [7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " [6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " [5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " [4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " [3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " [2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " [1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " [0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC2_SMPR2,ADC Sample Time Register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " [17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " [16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " [15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " [14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " [13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " [12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " [11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " [10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" group.long (0x100+0x20)++0x0B line.long 0x00 "ADC2_TR1,ADC Watchdog Threshold Register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC2_TR2,ADC Watchdog Threshold Register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC2_TR3,ADC Watchdog Threshold Register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" else rgroup.long (0x100+0x14)++0x07 line.long 0x00 "ADC2_SMPR1,ADC Sample Time Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 31. " SMPPLUS ,Addition of one clock cycle to the sampling time" "2.5cc,3.5cc" textline " " endif bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " [8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " [7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " [6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " [5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " [4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " [3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " [2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " [1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " [0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC2_SMPR2,ADC Sample Time Register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " [17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " [16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " [15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " [14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " [13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " [12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " [11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " [10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" rgroup.long (0x100+0x20)++0x0B line.long 0x00 "ADC2_TR1,ADC Watchdog Threshold Register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC2_TR2,ADC Watchdog Threshold Register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC2_TR3,ADC Watchdog Threshold Register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" endif if (((per.l(ad:0x50040000+0x100+0x08))&0x04)==0x00) group.long (0x100+0x30)++0x0F line.long 0x00 "ADC2_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC2_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC2_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC2_SQR4,ADC Regular Sequence Register 4" bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." else rgroup.long (0x100+0x30)++0x0F line.long 0x00 "ADC2_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC2_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC2_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC2_SQR4,ADC Regular Sequence Register 4" bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif rgroup.long (0x100+0x40)++0x03 line.long 0x00 "ADC2_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular data converted" if (((per.l(ad:0x50040000+0x100+0x0C))&0x80000000)==0x0) group.long (0x100+0x4C)++0x03 line.long 0x00 "ADC2_JSQR,ADC Injected Sequence Register" sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " elif (cpuis("STM32L476Z*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External trigger enable and polarity selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External trigger selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" else group.long (0x100+0x4C)++0x03 line.long 0x00 "ADC2_JSQR,ADC Injected Sequence Register" sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " elif (cpuis("STM32L476Z*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Software,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" endif if (((per.l(ad:0x50040000+0x100+0x08))&0xC)==0x00) group.long (0x100+0x60)++0x0F line.long 0x00 "ADC2_OFR1,ADC Offset Register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC2_OFR2,ADC Offset Register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC2_OFR3,ADC Offset Register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC2_OFR4,ADC Offset Register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" else rgroup.long (0x100+0x60)++0x0F line.long 0x00 "ADC2_OFR1,ADC Offset Register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC2_OFR2,ADC Offset Register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC2_OFR3,ADC Offset Register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC$_OFR4,ADC Offset Register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" endif rgroup.long (0x100+0x80)++0x0F line.long 0x00 "ADC2_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" line.long 0x04 "ADC2_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x04 0.--15. 1. " JDATA ,Injected data" line.long 0x08 "ADC2_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x08 0.--15. 1. " JDATA ,Injected data" line.long 0x0C "ADC2_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x0C 0.--15. 1. " JDATA ,Injected data" textline " " sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long (0x100+0xA0)++0x07 line.long 0x00 "ADC2_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 18. " AWD2CH[18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " [17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " [16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x00 0. " [0] ,Analog watchdog 2 channel 0 selection" "Not monitored,Monitored" line.long 0x04 "ADC2_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 18. " AWD3CR[18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " [17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " [16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x04 0. " [0] ,Analog watchdog 3 channel 0 selection" "Not monitored,Monitored" elif (CPUIS("STM32L476Z*")) group.long (0x100+0xA0)++0x07 line.long 0x00 "ADC2_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 23. " AWD2CH[23] ,Analog watchdog 2 channel 23 selection" "Not monitored,Monitored" bitfld.long 0x00 22. " [22] ,Analog watchdog 2 channel 22 selection" "Not monitored,Monitored" bitfld.long 0x00 21. " [21] ,Analog watchdog 2 channel 21 selection" "Not monitored,Monitored" bitfld.long 0x00 20. " [20] ,Analog watchdog 2 channel 20 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 19. " [19] ,Analog watchdog 2 channel 19 selection" "Not monitored,Monitored" bitfld.long 0x00 18. " [18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " [17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " [16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" line.long 0x04 "ADC2_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 23. " AWD3CH[23] ,Analog watchdog 3 channel 23 selection" "Not monitored,Monitored" bitfld.long 0x04 22. " [22] ,Analog watchdog 3 channel 22 selection" "Not monitored,Monitored" bitfld.long 0x04 21. " [21] ,Analog watchdog 3 channel 21 selection" "Not monitored,Monitored" bitfld.long 0x04 20. " [20] ,Analog watchdog 3 channel 20 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 19. " [19] ,Analog watchdog 3 channel 19 selection" "Not monitored,Monitored" bitfld.long 0x04 18. " [18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " [17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " [16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" else group.long (0x100+0xA0)++0x07 line.long 0x00 "ADC2_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 16. " AWD2CH[16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" line.long 0x04 "ADC2_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 16. " AWD3CR[16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" endif group.long (0x100+0xB0)++0x03 line.long 0x00 "ADC2_DIFSEL,ADC Differential Mode Selection Register" sif (CPUIS("STM32L476Q*")) bitfld.long 0x00 23. " DIFSEL[23] ,Differential mode for channel 23" "Single-ended,Differential" bitfld.long 0x00 22. " [22] ,Differential mode for channel 22" "Single-ended,Differential" bitfld.long 0x00 21. " [21] ,Differential mode for channel 21" "Single-ended,Differential" bitfld.long 0x00 20. " [20] ,Differential mode for channel 20" "Single-ended,Differential" textline " " bitfld.long 0x00 19. " [19] ,Differential mode for channel 19" "Single-ended,Differential" rbitfld.long 0x00 18. " [18] ,Differential mode for channel 18" "Single-ended," rbitfld.long 0x00 17. " [17] ,Differential mode for channel 17" "Single-ended," rbitfld.long 0x00 16. " [16] ,Differential mode for channel 16" "Single-ended," textline " " elif (cpuis("STM32L476Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 18. " DIFSEL[18] ,Differential mode for channel 18" "Single-ended,?..." rbitfld.long 0x00 17. " [17] ,Differential mode for channel 17" "Single-ended,?..." rbitfld.long 0x00 16. " [16] ,Differential mode for channel 16" "Single-ended,?..." textline " " endif bitfld.long 0x00 15. " [15] ,Differential mode for channel 15" "Single-ended,Differential" bitfld.long 0x00 14. " [14] ,Differential mode for channel 14" "Single-ended,Differential" bitfld.long 0x00 13. " [13] ,Differential mode for channel 13" "Single-ended,Differential" bitfld.long 0x00 12. " [12] ,Differential mode for channel 12" "Single-ended,Differential" textline " " bitfld.long 0x00 11. " [11] ,Differential mode for channel 11" "Single-ended,Differential" bitfld.long 0x00 10. " [10] ,Differential mode for channel 10" "Single-ended,Differential" bitfld.long 0x00 9. " [9] ,Differential mode for channel 9" "Single-ended,Differential" bitfld.long 0x00 8. " [8] ,Differential mode for channel 8" "Single-ended,Differential" textline " " bitfld.long 0x00 7. " [7] ,Differential mode for channel 7" "Single-ended,Differential" bitfld.long 0x00 6. " [6] ,Differential mode for channel 6" "Single-ended,Differential" bitfld.long 0x00 5. " [5] ,Differential mode for channel 5" "Single-ended,Differential" bitfld.long 0x00 4. " [4] ,Differential mode for channel 4" "Single-ended,Differential" textline " " bitfld.long 0x00 3. " [3] ,Differential mode for channel 3" "Single-ended,Differential" bitfld.long 0x00 2. " [2] ,Differential mode for channel 2" "Single-ended,Differential" bitfld.long 0x00 1. " [1] ,Differential mode for channel 1" "Single-ended,Differential" rbitfld.long 0x00 0. " [0] ,Differential mode for channel 0" "Single-ended,?..." if (((per.l(ad:0x50040000+0x100+0x08))&0xD)==0x01) group.long (0x100+0xB4)++0x03 line.long 0x00 "ADC2_CALFACT,ADC Calibration Factors" bitfld.long 0x00 22. " CALFACT_D[6] ,Calibration factor 6 in differential mode" "0,1" bitfld.long 0x00 21. " [5] ,Calibration factor 5 in differential mode" "0,1" bitfld.long 0x00 20. " [4] ,Calibration factor 4 in differential mode" "0,1" bitfld.long 0x00 19. " [3] ,Calibration factor 3 in differential mode" "0,1" textline " " bitfld.long 0x00 18. " [2] ,Calibration factor 2 in differential mode" "0,1" bitfld.long 0x00 17. " [1] ,Calibration factor 1 in differential mode" "0,1" bitfld.long 0x00 16. " [0] ,Calibration factor 0 in differential mode" "0,1" bitfld.long 0x00 6. " CALFACT_S[6] ,Calibration factor 6 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Calibration factor 5 in Single-Ended mode" "0,1" bitfld.long 0x00 4. " [4] ,Calibration factor 4 in Single-Ended mode" "0,1" bitfld.long 0x00 3. " [3] ,Calibration factor 3 in Single-Ended mode" "0,1" bitfld.long 0x00 2. " [2] ,Calibration factor 2 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 1. " [1] ,Calibration factor 1 in Single-Ended mode" "0,1" bitfld.long 0x00 0. " [0] ,Calibration factor 0 in Single-Ended mode" "0,1" else rgroup.long (0x100+0xb4)++0x03 line.long 0x00 "ADC2_CALFACT,ADC Calibration Factors" bitfld.long 0x00 22. " CALFACT_D[6] ,Calibration factor 6 in differential mode" "0,1" bitfld.long 0x00 21. " [5] ,Calibration factor 5 in differential mode" "0,1" bitfld.long 0x00 20. " [4] ,Calibration factor 4 in differential mode" "0,1" bitfld.long 0x00 19. " [3] ,Calibration factor 3 in differential mode" "0,1" textline " " bitfld.long 0x00 18. " [2] ,Calibration factor 2 in differential mode" "0,1" bitfld.long 0x00 17. " [1] ,Calibration factor 1 in differential mode" "0,1" bitfld.long 0x00 16. " [0] ,Calibration factor 0 in differential mode" "0,1" textline " " bitfld.long 0x00 6. " CALFACT_S[6] ,Calibration factor 6 in Single-Ended mode" "0,1" bitfld.long 0x00 5. " [5] ,Calibration factor 5 in Single-Ended mode" "0,1" bitfld.long 0x00 4. " [4] ,Calibration factor 4 in Single-Ended mode" "0,1" bitfld.long 0x00 3. " [3] ,Calibration factor 3 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Calibration factor 2 in Single-Ended mode" "0,1" bitfld.long 0x00 1. " [1] ,Calibration factor 1 in Single-Ended mode" "0,1" bitfld.long 0x00 0. " [0] ,Calibration factor 0 in Single-Ended mode" "0,1" endif tree.end tree "Slave ADC3" group.long 0x200++0x03 line.long 0x00 "ADC3_ISR,ADC Interrupt and Status Register" eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not injected,Injected" eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred" eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred" eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed" eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed" eventfld.long 0x00 4. " OVR ,ADC overrun" "No overrun,Overrun" eventfld.long 0x00 3. " EOS ,End of regular sequence flag" "Not complete,Completed" textline " " eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not complete,Completed" eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not ended,Ended" eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready" if (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x00) group.long (0x200+0x04)++0x03 line.long 0x00 "ADC3_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x8) group.long (0x200+0x04)++0x03 line.long 0x00 "ADC3_IER,ADC Interrupt Enable Register" rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x4) group.long (0x200+0x04)++0x03 line.long 0x00 "ADC3_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" else rgroup.long (0x200+0x04)++0x03 line.long 0x00 "ADC3_IER,ADC Interrupt Enable Register" bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " EOSIE ,End of regular sequence of conversions interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EOCIE ,End of regular conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable for regular conversions" "Disabled,Enabled" bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled" endif group.long (0x200+0x08)++0x03 line.long 0x00 "ADC3_CR,ADC Control Register" bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Complete,In progress" bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended inputs,Differential inputs" bitfld.long 0x00 29. " DEEPPWD ,Deep-power-down enable" "Not deep-power-down,Deep-power-down" bitfld.long 0x00 28. " ADVREGEN ,ADC voltage regulator enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No stop,Stop" bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No stop,Stop" bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No ongoing,Start" bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion" "No ongoing,Start" textline " " bitfld.long 0x00 1. " ADDIS ,ADC disable command" "Enabled,Disabled" bitfld.long 0x00 0. " ADEN ,ADC enable control" "Disabled,Enabled" if (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x00) group.long (0x200+0x0C)++0x03 line.long 0x00 "ADC3_CFGR,ADC configuration register" bitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else bitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x8) group.long (0x200+0x0C)++0x03 line.long 0x00 "ADC3_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" bitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" bitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" bitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x4) group.long (0x200+0x0C)++0x03 line.long 0x00 "ADC3_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" else group.long (0x200+0x0C)++0x03 line.long 0x00 "ADC3_CFGR,ADC configuration register" rbitfld.long 0x00 31. " JQDIS ,Injected Queue disable" "Enabled,Disabled" textline " a " sif (CPUIS("STM32L476Q*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " elif (CPUIS("STM32L476Z*")) rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,,ADC ch-19,ADC ch-20,ADC ch-21,ADC ch-22,ADC ch-23,?..." textline " " else rbitfld.long 0x00 26.--30. " AWD1CH ,Analog watchdog 1 channel selection" ",ADC ch-1,ADC ch-2,ADC ch-3,ADC ch-4,ADC ch-5,ADC ch-6,ADC ch-7,ADC ch-8,ADC ch-9,ADC ch-10,ADC ch-11,ADC ch-12,ADC ch-13,ADC ch-14,ADC ch-15,ADC ch-16,ADC ch-17,ADC ch-18,?..." textline " " endif rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled" rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled" rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog 1 enable on regular channels" "Disabled,Enabled" rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog 1 on a single channel or on all channels" "All channels,Single channel" textline " " rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode0,Mode1" rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1,2,3,4,5,6,7,8" rbitfld.long 0x00 16. " DISCEN ,Discontinuous mode for regular channels" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " AUTDLY ,Auto-delayed conversion mode" "Disabled,Enabled" rbitfld.long 0x00 13. " CONT ,Single / continuous conversion mode for regular conversions" "Single,Continuous" rbitfld.long 0x00 12. " OVRMOD ,Overrun Mode" "Preserved,Overwritten" rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection for regular channels" "Disabled,Rising edge,Falling edge,Both edges" textline " " rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection for regular group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left" rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12b,10b,8b,6b" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 2. " DFSDMCFG ,DFSDM mode configuration" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One Shot,Circular" rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x00) group.long (0x200+0x10)++0x03 line.long 0x00 "ADC3_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " bitfld.long 0x00 1. " JOVSE ,Injected oversampling enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" elif (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x8) group.long (0x200+0x10)++0x03 line.long 0x00 "ADC3_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " rbitfld.long 0x00 1. " JOVSE ,Injected oversampling Enable" "Disabled,Enabled" rbitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" else rgroup.long (0x200+0x10)++0x03 line.long 0x00 "ADC3_CFGR2,ADC Configuration Register 2" bitfld.long 0x00 10. " ROVSM ,Regular oversampling mode" "Continued,Resumed" bitfld.long 0x00 9. " TROVS ,Triggered regular oversampling" "1 trigger for all,1 trigger for 1" bitfld.long 0x00 5.--8. " OVSS ,Oversampling shift" "No shift,1b,2b,3b,4b,5b,6b,7b,8b,?..." bitfld.long 0x00 2.--4. " OVSR ,Oversampling ratio" "2x,4x,8x,16x,32x,64x,128x,256x" textline " " bitfld.long 0x00 1. " JOVSE ,Injected oversampling enable" "Disabled,Enabled" bitfld.long 0x00 0. " ROVSE ,Regular oversampling enable" "Disabled,Enabled" endif if (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x00) group.long (0x200+0x14)++0x07 line.long 0x00 "ADC3_SMPR1,ADC Sample Time Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 31. " SMPPLUS ,Addition of one clock cycle to the sampling time" "2.5cc,3.5cc" textline " " endif bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " [8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " [7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " [6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " [5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " [4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " [3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " [2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " [1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " [0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC3_SMPR2,ADC Sample Time Register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " [17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " [16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " [15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " [14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " [13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " [12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " [11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " [10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" group.long (0x200+0x20)++0x0B line.long 0x00 "ADC3_TR1,ADC Watchdog Threshold Register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC3_TR2,ADC Watchdog Threshold Register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC3_TR3,ADC Watchdog Threshold Register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" else rgroup.long (0x200+0x14)++0x07 line.long 0x00 "ADC3_SMPR1,ADC Sample Time Register 1" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 31. " SMPPLUS ,Addition of one clock cycle to the sampling time" "2.5cc,3.5cc" textline " " endif bitfld.long 0x00 27.--29. " SMP[9] ,Channel 9 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 24.--26. " [8] ,Channel 8 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 21.--23. " [7] ,Channel 7 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 18.--20. " [6] ,Channel 6 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 15.--17. " [5] ,Channel 5 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 12.--14. " [4] ,Channel 4 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 9.--11. " [3] ,Channel 3 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 6.--8. " [2] ,Channel 2 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x00 3.--5. " [1] ,Channel 1 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x00 0.--2. " [0] ,Channel 0 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" line.long 0x04 "ADC3_SMPR2,ADC Sample Time Register 2" bitfld.long 0x04 24.--26. " SMP[18] ,Channel 18 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 21.--23. " [17] ,Channel 17 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 18.--20. " [16] ,Channel 16 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 15.--17. " [15] ,Channel 15 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 12.--14. " [14] ,Channel 14 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 9.--11. " [13] ,Channel 13 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 6.--8. " [12] ,Channel 12 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" bitfld.long 0x04 3.--5. " [11] ,Channel 11 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" textline " " bitfld.long 0x04 0.--2. " [10] ,Channel 10 sampling time selection" "2.5cc,6.5cc,12.5cc,24.5cc,47.5cc,92.5cc,247.5cc,640.5cc" rgroup.long (0x200+0x20)++0x0B line.long 0x00 "ADC3_TR1,ADC Watchdog Threshold Register 1" hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog 1 higher threshold" hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog 1 lower threshold" line.long 0x04 "ADC3_TR2,ADC Watchdog Threshold Register 2" hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog 2 higher threshold" hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog 2 lower threshold" line.long 0x08 "ADC3_TR3,ADC Watchdog Threshold Register 3" hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog 3 higher threshold" hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog 3 lower threshold" endif if (((per.l(ad:0x50040000+0x200+0x08))&0x04)==0x00) group.long (0x200+0x30)++0x0F line.long 0x00 "ADC3_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC3_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC3_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC3_SQR4,ADC Regular Sequence Register 4" bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." else rgroup.long (0x200+0x30)++0x0F line.long 0x00 "ADC3_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1conv,2conv,3conv,4conv,5conv,6conv,7conv,8conv,9conv,10conv,11conv,12conv,13conv,14conv,15conv,16conv" line.long 0x04 "ADC3_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC3_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC3_SQR4,ADC Regular Sequence Register 4" bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif rgroup.long (0x200+0x40)++0x03 line.long 0x00 "ADC3_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular data converted" if (((per.l(ad:0x50040000+0x200+0x0C))&0x80000000)==0x0) group.long (0x200+0x4C)++0x03 line.long 0x00 "ADC3_JSQR,ADC Injected Sequence Register" sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " elif (cpuis("STM32L476Z*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External trigger enable and polarity selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External trigger selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" else group.long (0x200+0x4C)++0x03 line.long 0x00 "ADC3_JSQR,ADC Injected Sequence Register" sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " elif (cpuis("STM32L476Z*")) bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " else bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " endif bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Software,Rising edge,Falling edge,Both edges" bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1conv,2conv,3conv,4conv" endif if (((per.l(ad:0x50040000+0x200+0x08))&0xC)==0x00) group.long (0x200+0x60)++0x0F line.long 0x00 "ADC3_OFR1,ADC Offset Register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC3_OFR2,ADC Offset Register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC3_OFR3,ADC Offset Register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC3_OFR4,ADC Offset Register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" else rgroup.long (0x200+0x60)++0x0F line.long 0x00 "ADC3_OFR1,ADC Offset Register 1" bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 enable" "Disabled,Enabled" bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 0x01 " OFFSET1 ,Data offset 1 for the channel programmed into bits OFFSET1_CH" line.long 0x04 "ADC3_OFR2,ADC Offset Register 2" bitfld.long 0x04 31. " OFFSET2_EN ,Offset 2 enable" "Disabled,Enabled" bitfld.long 0x04 26.--30. " OFFSET2_CH ,Channel selection for the data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x04 0.--11. 0x01 " OFFSET2 ,Data offset 2 for the channel programmed into bits OFFSET2_CH" line.long 0x08 "ADC3_OFR3,ADC Offset Register 3" bitfld.long 0x08 31. " OFFSET3_EN ,Offset 3 enable" "Disabled,Enabled" bitfld.long 0x08 26.--30. " OFFSET3_CH ,Channel selection for the data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 0.--11. 0x01 " OFFSET3 ,Data offset 3 for the channel programmed into bits OFFSET3_CH" line.long 0x0c "ADC$_OFR4,ADC Offset Register 4" bitfld.long 0x0c 31. " OFFSET4_EN ,Offset 4 enable" "Disabled,Enabled" bitfld.long 0x0c 26.--30. " OFFSET4_CH ,Channel selection for the data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0c 0.--11. 0x01 " OFFSET4 ,Data offset 4 for the channel programmed into bits OFFSET4_CH" endif rgroup.long (0x200+0x80)++0x0F line.long 0x00 "ADC3_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" line.long 0x04 "ADC3_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x04 0.--15. 1. " JDATA ,Injected data" line.long 0x08 "ADC3_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x08 0.--15. 1. " JDATA ,Injected data" line.long 0x0C "ADC3_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x0C 0.--15. 1. " JDATA ,Injected data" textline " " sif (cpuis("STM32L476Q*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) group.long (0x200+0xA0)++0x07 line.long 0x00 "ADC3_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 18. " AWD2CH[18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " [17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " [16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x00 0. " [0] ,Analog watchdog 2 channel 0 selection" "Not monitored,Monitored" line.long 0x04 "ADC3_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 18. " AWD3CR[18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " [17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " [16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" bitfld.long 0x04 0. " [0] ,Analog watchdog 3 channel 0 selection" "Not monitored,Monitored" elif (CPUIS("STM32L476Z*")) group.long (0x200+0xA0)++0x07 line.long 0x00 "ADC3_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 23. " AWD2CH[23] ,Analog watchdog 2 channel 23 selection" "Not monitored,Monitored" bitfld.long 0x00 22. " [22] ,Analog watchdog 2 channel 22 selection" "Not monitored,Monitored" bitfld.long 0x00 21. " [21] ,Analog watchdog 2 channel 21 selection" "Not monitored,Monitored" bitfld.long 0x00 20. " [20] ,Analog watchdog 2 channel 20 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 19. " [19] ,Analog watchdog 2 channel 19 selection" "Not monitored,Monitored" bitfld.long 0x00 18. " [18] ,Analog watchdog 2 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x00 17. " [17] ,Analog watchdog 2 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x00 16. " [16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" line.long 0x04 "ADC3_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 23. " AWD3CH[23] ,Analog watchdog 3 channel 23 selection" "Not monitored,Monitored" bitfld.long 0x04 22. " [22] ,Analog watchdog 3 channel 22 selection" "Not monitored,Monitored" bitfld.long 0x04 21. " [21] ,Analog watchdog 3 channel 21 selection" "Not monitored,Monitored" bitfld.long 0x04 20. " [20] ,Analog watchdog 3 channel 20 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 19. " [19] ,Analog watchdog 3 channel 19 selection" "Not monitored,Monitored" bitfld.long 0x04 18. " [18] ,Analog watchdog 3 channel 18 selection" "Not monitored,Monitored" bitfld.long 0x04 17. " [17] ,Analog watchdog 3 channel 17 selection" "Not monitored,Monitored" bitfld.long 0x04 16. " [16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" else group.long (0x200+0xA0)++0x07 line.long 0x00 "ADC3_AWD2CR,ADC Analog Watchdog 2 Configuration Register" bitfld.long 0x00 16. " AWD2CH[16] ,Analog watchdog 2 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x00 15. " [15] ,Analog watchdog 2 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x00 14. " [14] ,Analog watchdog 2 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x00 13. " [13] ,Analog watchdog 2 channel 13 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 12. " [12] ,Analog watchdog 2 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x00 11. " [11] ,Analog watchdog 2 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x00 10. " [10] ,Analog watchdog 2 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x00 9. " [9] ,Analog watchdog 2 channel 9 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 8. " [8] ,Analog watchdog 2 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x00 7. " [7] ,Analog watchdog 2 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x00 6. " [6] ,Analog watchdog 2 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x00 5. " [5] ,Analog watchdog 2 channel 5 selection" "Not monitored,Monitored" textline " " bitfld.long 0x00 4. " [4] ,Analog watchdog 2 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x00 3. " [3] ,Analog watchdog 2 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x00 2. " [2] ,Analog watchdog 2 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x00 1. " [1] ,Analog watchdog 2 channel 1 selection" "Not monitored,Monitored" line.long 0x04 "ADC3_AWD3CR,ADC Analog Watchdog 3 Configuration Register" bitfld.long 0x04 16. " AWD3CR[16] ,Analog watchdog 3 channel 16 selection" "Not monitored,Monitored" bitfld.long 0x04 15. " [15] ,Analog watchdog 3 channel 15 selection" "Not monitored,Monitored" bitfld.long 0x04 14. " [14] ,Analog watchdog 3 channel 14 selection" "Not monitored,Monitored" bitfld.long 0x04 13. " [13] ,Analog watchdog 3 channel 13 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 12. " [12] ,Analog watchdog 3 channel 12 selection" "Not monitored,Monitored" bitfld.long 0x04 11. " [11] ,Analog watchdog 3 channel 11 selection" "Not monitored,Monitored" bitfld.long 0x04 10. " [10] ,Analog watchdog 3 channel 10 selection" "Not monitored,Monitored" bitfld.long 0x04 9. " [9] ,Analog watchdog 3 channel 9 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 8. " [8] ,Analog watchdog 3 channel 8 selection" "Not monitored,Monitored" bitfld.long 0x04 7. " [7] ,Analog watchdog 3 channel 7 selection" "Not monitored,Monitored" bitfld.long 0x04 6. " [6] ,Analog watchdog 3 channel 6 selection" "Not monitored,Monitored" bitfld.long 0x04 5. " [5] ,Analog watchdog 3 channel 5 selection" "Not monitored,Monitored" textline " " bitfld.long 0x04 4. " [4] ,Analog watchdog 3 channel 4 selection" "Not monitored,Monitored" bitfld.long 0x04 3. " [3] ,Analog watchdog 3 channel 3 selection" "Not monitored,Monitored" bitfld.long 0x04 2. " [2] ,Analog watchdog 3 channel 2 selection" "Not monitored,Monitored" bitfld.long 0x04 1. " [1] ,Analog watchdog 3 channel 1 selection" "Not monitored,Monitored" endif group.long (0x200+0xB0)++0x03 line.long 0x00 "ADC3_DIFSEL,ADC Differential Mode Selection Register" sif (CPUIS("STM32L476Q*")) bitfld.long 0x00 23. " DIFSEL[23] ,Differential mode for channel 23" "Single-ended,Differential" bitfld.long 0x00 22. " [22] ,Differential mode for channel 22" "Single-ended,Differential" bitfld.long 0x00 21. " [21] ,Differential mode for channel 21" "Single-ended,Differential" bitfld.long 0x00 20. " [20] ,Differential mode for channel 20" "Single-ended,Differential" textline " " bitfld.long 0x00 19. " [19] ,Differential mode for channel 19" "Single-ended,Differential" rbitfld.long 0x00 18. " [18] ,Differential mode for channel 18" "Single-ended," rbitfld.long 0x00 17. " [17] ,Differential mode for channel 17" "Single-ended," rbitfld.long 0x00 16. " [16] ,Differential mode for channel 16" "Single-ended," textline " " elif (cpuis("STM32L476Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) rbitfld.long 0x00 18. " DIFSEL[18] ,Differential mode for channel 18" "Single-ended,?..." rbitfld.long 0x00 17. " [17] ,Differential mode for channel 17" "Single-ended,?..." rbitfld.long 0x00 16. " [16] ,Differential mode for channel 16" "Single-ended,?..." textline " " endif bitfld.long 0x00 15. " [15] ,Differential mode for channel 15" "Single-ended,Differential" bitfld.long 0x00 14. " [14] ,Differential mode for channel 14" "Single-ended,Differential" bitfld.long 0x00 13. " [13] ,Differential mode for channel 13" "Single-ended,Differential" bitfld.long 0x00 12. " [12] ,Differential mode for channel 12" "Single-ended,Differential" textline " " bitfld.long 0x00 11. " [11] ,Differential mode for channel 11" "Single-ended,Differential" bitfld.long 0x00 10. " [10] ,Differential mode for channel 10" "Single-ended,Differential" bitfld.long 0x00 9. " [9] ,Differential mode for channel 9" "Single-ended,Differential" bitfld.long 0x00 8. " [8] ,Differential mode for channel 8" "Single-ended,Differential" textline " " bitfld.long 0x00 7. " [7] ,Differential mode for channel 7" "Single-ended,Differential" bitfld.long 0x00 6. " [6] ,Differential mode for channel 6" "Single-ended,Differential" bitfld.long 0x00 5. " [5] ,Differential mode for channel 5" "Single-ended,Differential" bitfld.long 0x00 4. " [4] ,Differential mode for channel 4" "Single-ended,Differential" textline " " bitfld.long 0x00 3. " [3] ,Differential mode for channel 3" "Single-ended,Differential" bitfld.long 0x00 2. " [2] ,Differential mode for channel 2" "Single-ended,Differential" bitfld.long 0x00 1. " [1] ,Differential mode for channel 1" "Single-ended,Differential" rbitfld.long 0x00 0. " [0] ,Differential mode for channel 0" "Single-ended,?..." if (((per.l(ad:0x50040000+0x200+0x08))&0xD)==0x01) group.long (0x200+0xB4)++0x03 line.long 0x00 "ADC3_CALFACT,ADC Calibration Factors" bitfld.long 0x00 22. " CALFACT_D[6] ,Calibration factor 6 in differential mode" "0,1" bitfld.long 0x00 21. " [5] ,Calibration factor 5 in differential mode" "0,1" bitfld.long 0x00 20. " [4] ,Calibration factor 4 in differential mode" "0,1" bitfld.long 0x00 19. " [3] ,Calibration factor 3 in differential mode" "0,1" textline " " bitfld.long 0x00 18. " [2] ,Calibration factor 2 in differential mode" "0,1" bitfld.long 0x00 17. " [1] ,Calibration factor 1 in differential mode" "0,1" bitfld.long 0x00 16. " [0] ,Calibration factor 0 in differential mode" "0,1" bitfld.long 0x00 6. " CALFACT_S[6] ,Calibration factor 6 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 5. " [5] ,Calibration factor 5 in Single-Ended mode" "0,1" bitfld.long 0x00 4. " [4] ,Calibration factor 4 in Single-Ended mode" "0,1" bitfld.long 0x00 3. " [3] ,Calibration factor 3 in Single-Ended mode" "0,1" bitfld.long 0x00 2. " [2] ,Calibration factor 2 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 1. " [1] ,Calibration factor 1 in Single-Ended mode" "0,1" bitfld.long 0x00 0. " [0] ,Calibration factor 0 in Single-Ended mode" "0,1" else rgroup.long (0x200+0xb4)++0x03 line.long 0x00 "ADC3_CALFACT,ADC Calibration Factors" bitfld.long 0x00 22. " CALFACT_D[6] ,Calibration factor 6 in differential mode" "0,1" bitfld.long 0x00 21. " [5] ,Calibration factor 5 in differential mode" "0,1" bitfld.long 0x00 20. " [4] ,Calibration factor 4 in differential mode" "0,1" bitfld.long 0x00 19. " [3] ,Calibration factor 3 in differential mode" "0,1" textline " " bitfld.long 0x00 18. " [2] ,Calibration factor 2 in differential mode" "0,1" bitfld.long 0x00 17. " [1] ,Calibration factor 1 in differential mode" "0,1" bitfld.long 0x00 16. " [0] ,Calibration factor 0 in differential mode" "0,1" textline " " bitfld.long 0x00 6. " CALFACT_S[6] ,Calibration factor 6 in Single-Ended mode" "0,1" bitfld.long 0x00 5. " [5] ,Calibration factor 5 in Single-Ended mode" "0,1" bitfld.long 0x00 4. " [4] ,Calibration factor 4 in Single-Ended mode" "0,1" bitfld.long 0x00 3. " [3] ,Calibration factor 3 in Single-Ended mode" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Calibration factor 2 in Single-Ended mode" "0,1" bitfld.long 0x00 1. " [1] ,Calibration factor 1 in Single-Ended mode" "0,1" bitfld.long 0x00 0. " [0] ,Calibration factor 0 in Single-Ended mode" "0,1" endif tree.end width 9. tree "ADC common registers" rgroup.long 0x300++0x03 line.long 0x00 "ADC_CSR,ADC Common Status Register" bitfld.long 0x00 26. " JQOVF_SLV ,Injected context queue overflow flag of the slave ADC" "Not occurred,Occurred" bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Not occurred,Occurred" bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Not occurred,Occurred" bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Not ended,Ended" bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Not ended,Ended" bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun" bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Not ended,Ended" textline " " bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Not ended,Ended" bitfld.long 0x00 17. " EOSMP_SLV ,End of sampling phase flag of the slave ADC" "Not ended,Ended" bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready" bitfld.long 0x00 10. " JQOVF_MST ,Injected context queue overflow flag of the master ADC" "Not overflowed,Overflowed" textline " " bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Not occurred,Occurred" bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Not occurred,Occurred" bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Not occurred,Occurred" bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Not ended,Ended" textline " " bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Not ended,Ended" bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun" bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Not ended,Ended" bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Not ended,Ended" textline " " bitfld.long 0x00 1. " EOSMP_MST ,End of sampling phase flag of the master ADC" "Not ended,Ended" bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready" group.long 0x308++0x03 line.long 0x00 "ADC_CCR,ADC Common Control Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 24. " CH18SEL ,CH18 selection" "VBAT disabled,VBAT enabled" bitfld.long 0x00 23. " CH17SEL ,CH17 selection" "Disabled,Enabled" bitfld.long 0x00 22. " VREFEN ,VREFINT enable" "Disabled,Enabled" bitfld.long 0x00 18.--21. " PRESC ,ADC prescaler" "Not div,2,4,6,8,10,12,16,32,64,128,256,?..." textline " " bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "CK_ADC,HCLK/1,HCLK/2,HCLK/4" bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,Dual interleaved,12&10b resolution,8&6b resolution" bitfld.long 0x00 13. " DMACFG ,DMA configuration (for dual ADC mode)" "One Shot,Circular" bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent,Regular+Injected,Regular+Alternate,Interleaved+Injected,,Injected,Regular,Interleaved,Alternate,?..." else bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled" bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled" bitfld.long 0x00 22. " VREFEN ,VREFINT enable" "Disabled,Enabled" bitfld.long 0x00 18.--21. " PRESC ,ADC prescaler" "Not div,2,4,6,8,10,12,16,32,64,128,256,?..." textline " " bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "CK_ADC,HCLK/1,HCLK/2,HCLK/4" bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,Dual interleaved,12&10b resolution,8&6b resolution" bitfld.long 0x00 13. " DMACFG ,DMA configuration (for dual ADC mode)" "One Shot,Circular" bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent,Regular+Injected,Regular+Alternate,Interleaved+Injected,,Injected,Regular,Interleaved,Alternate,?..." endif rgroup.long 0x30C++0x03 line.long 0x00 "ADC_CDR,ADC Common Regular Data Register for Dual Mode" hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC" hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC" tree.end width 0x0B tree.end endif tree "DAC (Digital-to-analog converter)" base ad:0x40007400 width 13. sif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*"))||(cpuis("STM32L451*")) if ((per.l(ad:0x40007400)&0x40004)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x40004)==0x04) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" textline " " else bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,,7TRGO,,2TRGO,,External line9,Software" textline " " endif bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x40004)==0x40000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" textline " " else bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,,7TRGO,,2TRGO,,External line9,Software" textline " " endif bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x40004)==0x40004) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" textline " " else bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,,7TRGO,,2TRGO,,External line9,Software" textline " " endif bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*")) bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" textline " " else bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,,7TRGO,,2TRGO,,External line9,Software" textline " " endif bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" endif elif cpuis("STM32H743*")||cpuis("STM32H753*") if ((per.l(ad:0x40007400)&0x40004)==0x00) if ((per.l(ad:0x40007400)&0x10001)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x01) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x10000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" endif elif ((per.l(ad:0x40007400)&0x40004)==0x04) if ((per.l(ad:0x40007400)&0x10001)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x01) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x10000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" textline " " bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" endif elif ((per.l(ad:0x40007400)&0x40004)==0x40000) if ((per.l(ad:0x40007400)&0x10001)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x01) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x10000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" endif elif ((per.l(ad:0x40007400)&0x40004)==0x40004) if ((per.l(ad:0x40007400)&0x10001)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x01) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x10001)==0x10000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" rbitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 18.--21. " TSEL2 ,DAC channel2 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 17. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,11:0/4095,11:0/4095,11:0/4095,11:0/4095" textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 2.--5. " TSEL1 ,DAC channel1 trigger selection" "SWTRIG,TIM1_TRGO,TIM2_TRGO,TIM4_TRGO,TIM5_TRGO,TIM6_TRGO,TIM7_TRGO,TIM8_TRGO,TIM15_TRGO,HRTIM1_DACTRG1,HRTIM1_DACTRG2,LPTIM1_OUT,LPTIM2_OUT,EXTI9,?..." bitfld.long 0x00 1. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" endif endif else if (((per.l(ad:0x40007400))&0x10001)==0x00000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0x10001)==0x10000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,?..." bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,Calibration" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0x10001)==0x01) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,Calibration" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,?..." bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0x10000)==0x10001) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 30. " CEN2 ,DAC Channel 2 calibration enable" "Normal,?..." bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 18. " TEN2 ,DAC channel2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CEN1 ,DAC Channel 1 calibration enable" "Normal,?..." bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 mask/amplitude selector. Unmask bits / Triangle amplitude" "0/1,1:0/3,2:0/7,3:0/15,4:0/31,5:0/63,6:0/127,7:0/255,8:0/511,9:0/1023,10:0/2047,11:0/4095,?..." textline " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise enabled,Triangle enabled,Triangle enabled" bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "6TRGO,8TRGO,7TRGO,5TRGO,2TRGO,4TRGO,External line9,Software" bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled" endif endif textline " " wgroup.long 0x04++0x03 line.long 0x00 "DAC_SWTRGR,DAC Software Trigger Register" bitfld.long 0x00 1. " SWTRIG2 ,DAC channel2 software trigger" "Disabled,Enabled" bitfld.long 0x00 0. " SWTRIG1 ,DAC channel1 software trigger" "Disabled,Enabled" group.long 0x08++0x23 line.long 0x00 "DAC_DHR12R1,DAC Channel1 12-bit Right-Aligned Data Holding Register" hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit right-aligned data" line.long 0x04 "DAC_DHR12L1,DAC Channel1 12-bit Left Aligned Data Holding Register" hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit left-aligned data" line.long 0x08 "DAC_DHR8R1,DAC Channel1 8-bit Right Aligned Data Holding Register" hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit right-aligned data" line.long 0x0C "DAC_DHR12R2,DAC Channel2 12-bit Right Aligned Data Holding Register" hexmask.long.word 0x0C 0.--11. 1. " DACC2DHR ,DAC channel2 12-bit right-aligned data" line.long 0x10 "DAC_DHR12L2,DAC Channel2 12-bit Left Aligned Data Holding Register" hexmask.long.word 0x10 4.--15. 1. " DACC2DHR ,DAC channel2 12-bit left-aligned data" line.long 0x14 "DAC_DHR8R2,DAC Channel2 8-bit Right-Aligned Data Holding Register" hexmask.long.byte 0x14 0.--7. 1. " DACC2DHR ,DAC channel2 8-bit right-aligned data" line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit Right-Aligned Data Holding Register" hexmask.long.word 0x18 16.--27. 1. " DACC2DHR ,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit right-aligned data" line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit Left Aligned Data Holding Register" hexmask.long.word 0x1C 20.--31. 1. " DACC2DHR ,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit left-aligned data" line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit Right Aligned Data Holding Register" hexmask.long.byte 0x20 8.--15. 1. " DACC2DHR ,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x07 line.long 0x00 "DAC_DOR1,DAC Channel1 Data Output Register" hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel1 data output" line.long 0x04 "DAC_DOR2,DAC Channel2 Data Output Register" hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,DAC channel2 data output" group.long 0x34++0x07 line.long 0x00 "DAC_SR,DAC Status Register" rbitfld.long 0x00 31. " BWST2 ,DAC channel 2 busy writing sample time flag" "No write operation,Write operation" textline " " sif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L471*"))||(cpuis("STM32L475*"))||(cpuis("STM32L451*"))||(cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 30. " CAL_FLAG2 ,DAC channel 2 calibration offset status" "Cal valueoffset corr val" textline " " else rbitfld.long 0x00 30. " CAL_FLAG2 ,DAC channel 2 calibration offset status" "Value>offset cal,Valueoffset corr val" textline " " else rbitfld.long 0x00 14. " CAL_FLAG1 ,DAC channel 1 calibration offset status" "Value>offset cal,Value 2.4V)" rbitfld.long 0x00 15. " CALOUT ,Operational amplifier calibration output" "Not trimmed,Trimmed" bitfld.long 0x00 14. " USERTRIM ,Allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values" "Factory,User" bitfld.long 0x00 13. " CALSEL ,Calibration selection" "NMOS,PMOS" textline " " bitfld.long 0x00 12. " CALON ,Calibration mode enabled" "Normal,Calibration" bitfld.long 0x00 10. " VP_SEL ,Non inverted input selection" "GPIO-VINP,DAC-VINP" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,,Not connected,Not connected" textline " " elif (cpuis("STM32L4A6*")||cpuis("STM32L496*")) sif (cpuis("STM32L4A6Q*")||cpuis("STM32L496Q*")||cpuis("STM32L4A6A*")||cpuis("STM32L496A*")) bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,Ded low leak-VINM,Not connected,Not connected" textline " " else bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,,Not connected,Not connected" textline " " endif else bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,Ded low leak-VINM,Not connected,Not connected" textline " " endif bitfld.long 0x00 4.--5. " PGA_GAIN ,Operational amplifier programmable amplifier gain value" "Gain2,Gain4,Gain8,Gain16" bitfld.long 0x00 2.--3. " OPAMODE ,Operational amplifier PGA mode" "Disabled,Disabled,PGA_GAIN,Follower" bitfld.long 0x00 1. " OPALPM ,Operational amplifier low power mode" "Normal,Low-power" bitfld.long 0x00 0. " OPAEN ,Operational amplifier enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "OPAMP1_CSR,OPAMP1 Control/status Register" bitfld.long 0x00 31. " OPA_RANGE ,Operational amplifier power supply range for stability" "Low(VDDA < 2.4V),High(VDDA > 2.4V)" rbitfld.long 0x00 15. " CALOUT ,Operational amplifier calibration output" "Not trimmed,Trimmed" bitfld.long 0x00 14. " USERTRIM ,Allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values" "Factory,User" bitfld.long 0x00 13. " CALSEL ,Calibration selection" "NMOS,PMOS" textline " " bitfld.long 0x00 12. " CALON ,Calibration mode enabled" "Normal,Calibration" bitfld.long 0x00 10. " VP_SEL ,Non inverted input selection" "GPIO-VINP,DAC-VINP" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,?..." textline " " elif (cpuis("STM32L4A6*")||cpuis("STM32L496*")) sif (cpuis("STM32L4A6Q*")||cpuis("STM32L496Q*")||cpuis("STM32L4A6A*")||cpuis("STM32L496A*")) bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,Ded low leak-VINM,?..." textline " " else bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,?..." textline " " endif else bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,Ded low leak-VINM,?..." textline " " endif bitfld.long 0x00 4.--5. " PGA_GAIN ,Operational amplifier programmable amplifier gain value" "Gain2,Gain4,Gain8,Gain16" bitfld.long 0x00 2.--3. " OPAMODE ,Operational amplifier PGA mode" "Disabled,Disabled,PGA_GAIN,Follower" bitfld.long 0x00 1. " OPALPM ,Operational amplifier low power mode" "Normal,Low-power" bitfld.long 0x00 0. " OPAEN ,Operational amplifier enable" "Disabled,Enabled" endif group.long 0x04++0x07 line.long 0x00 "OPAMP1_OTR,OPAMP1 Offset Trimming Register In Normal Mode" bitfld.long 0x00 8.--12. " TRIMOFFSETP ,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRIMOFFSETN ,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "OPAMP1_LPOTR,OPAMP1 Offset Trimming Register In Low-Power Mode" bitfld.long 0x04 8.--12. " TRIMLPOFFSETP ,Low-power mode trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " TRIMLPOFFSETN ,Low-power mode trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) if (((per.l(ad:0x40007800+0x10))&0xC)==0x8) group.long 0x10++0x03 line.long 0x00 "OPAMP2_CSR,OPAMP2 Control/Status Register" rbitfld.long 0x00 15. " CALOUT ,Operational amplifier calibration output" "Not trimmed,Trimmed" bitfld.long 0x00 14. " USERTRIM ,Allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values" "Factory,User" bitfld.long 0x00 13. " CALSEL ,Calibration selection" "NMOS,PMOS" bitfld.long 0x00 12. " CALON ,Calibration mode enabled" "Normal,Calibration" textline " " bitfld.long 0x00 10. " VP_SEL ,Non inverted input selection" "GPIO-VINP,DAC-VINP" textline " " sif (cpuis("STM32L4A6Q*")||cpuis("STM32L496Q*")) bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,Ded low leak-VINM,Not connected,Not connected" textline " " else bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,,Not connected,Not connected" textline " " endif bitfld.long 0x00 4.--5. " PGA_GAIN ,Operational amplifier programmable amplifier gain value" "Gain2,Gain4,Gain8,Gain16" bitfld.long 0x00 2.--3. " OPAMODE ,Operational amplifier PGA mode" "Disabled,Disabled,PGA_GAIN,Follower" bitfld.long 0x00 1. " OPALPM ,Operational amplifier low power mode" "Normal,Low-power" bitfld.long 0x00 0. " OPAEN ,Operational amplifier enable" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "OPAMP2_CSR,OPAMP2 Control/Status Register" rbitfld.long 0x00 15. " CALOUT ,Operational amplifier calibration output" "Not trimmed,Trimmed" bitfld.long 0x00 14. " USERTRIM ,Allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values" "Factory,User" bitfld.long 0x00 13. " CALSEL ,Calibration selection" "NMOS,PMOS" bitfld.long 0x00 12. " CALON ,Calibration mode enabled" "Normal,Calibration" textline " " bitfld.long 0x00 10. " VP_SEL ,Non inverted input selection" "GPIO-VINP,DAC-VINP" textline " " sif (cpuis("STM32L4A6Q*")||cpuis("STM32L496Q*")) bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,Ded low leak-VINM,?..." textline " " else bitfld.long 0x00 8.--9. " VM_SEL ,Inverting input selection" "GPIO-VINM,?..." textline " " endif bitfld.long 0x00 4.--5. " PGA_GAIN ,Operational amplifier programmable amplifier gain value" "Gain2,Gain4,Gain8,Gain16" bitfld.long 0x00 2.--3. " OPAMODE ,Operational amplifier PGA mode" "Disabled,Disabled,PGA_GAIN,Follower" bitfld.long 0x00 1. " OPALPM ,Operational amplifier low power mode" "Normal,Low-power" bitfld.long 0x00 0. " OPAEN ,Operational amplifier enable" "Disabled,Enabled" endif group.long 0x14++0x07 line.long 0x00 "OPAMP2_OTR,OPAMP2 Offset Trimming Register In Normal Mode" bitfld.long 0x00 8.--12. " TRIMOFFSETP ,Trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRIMOFFSETN ,Trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "OPAMP2_LPOTR,OPAMP2 Offset Trimming Register In Low-Power Mode" bitfld.long 0x04 8.--12. " TRIMLPOFFSETP ,Low-power mode trim for PMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " TRIMLPOFFSETN ,Low-power mode trim for NMOS differential pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end sif (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L4?6*"))&&(!cpuis("STM32L431*")) tree "DFSDM (Digital filter for sigma delta modulators)" base ad:0x40016000 width 19. tree "Channel 0" if (((per.l(ad:0x40016000+0x0))&0x80)==0x0) group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel Configuration 0 register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN0R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CHDATIN0R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN0R,?..." textline " " else rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CHDATIN0R,?..." textline " " endif rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0x0))&0x80)==0x0) group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" else group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" endif rgroup.long (0x0+0x0C)++0x03 line.long 0x00 "DFSDM_CH0WDATR,DFSDM Channel 0 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0x0))&0x3000)==(0x2000||0x1000)) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 0 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" textline " " else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 0 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" textline " " endif else if (((per.l(ad:0x40016000+0x0))&0x3000)==0x2000) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 0 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" textline " " else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 0 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" textline " " endif endif tree.end tree "Channel 1" if (((per.l(ad:0x40016000+0x20))&0x80)==0x0) group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel Configuration 1 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN1R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CHDATIN1R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM channel Configuration 1 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CHDATIN1R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0x20))&0x80)==0x0) group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" else group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" endif rgroup.long (0x20+0x0C)++0x03 line.long 0x00 "DFSDM_CH1WDATR,DFSDM Channel 1 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0x20))&0x3000)==(0x2000||0x1000)) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 1 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" textline " " else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 1 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" textline " " endif else if (((per.l(ad:0x40016000+0x20))&0x3000)==0x2000) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 1 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" textline " " else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 1 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" textline " " endif endif tree.end tree "Channel 2" if (((per.l(ad:0x40016000+0x40))&0x80)==0x0) group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel Configuration 2 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN2R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CHDATIN2R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM channel Configuration 2 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CHDATIN2R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0x40))&0x80)==0x0) group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" else group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" endif rgroup.long (0x40+0x0C)++0x03 line.long 0x00 "DFSDM_CH2WDATR,DFSDM Channel 2 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0x40))&0x3000)==(0x2000||0x1000)) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 2 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" textline " " else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 2 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" textline " " endif else if (((per.l(ad:0x40016000+0x40))&0x3000)==0x2000) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 2 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" textline " " else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 2 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" textline " " endif endif tree.end tree "Channel 3" if (((per.l(ad:0x40016000+0x60))&0x80)==0x0) group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel Configuration 3 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN3R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CHDATIN3R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3CFGR1,DFSDM channel Configuration 3 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CHDATIN3R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0x60))&0x80)==0x0) group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CH3CFGR2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" else group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CH3CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" endif rgroup.long (0x60+0x0C)++0x03 line.long 0x00 "DFSDM_CH3WDATR,DFSDM Channel 3 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 3 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0x60))&0x3000)==(0x2000||0x1000)) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 3 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" textline " " else rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 3 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" textline " " endif else if (((per.l(ad:0x40016000+0x60))&0x3000)==0x2000) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 3 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" textline " " else rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 3 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" textline " " endif endif tree.end tree "Channel 4" if (((per.l(ad:0x40016000+0x80))&0x80)==0x0) group.long 0x80++0x3 line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel Configuration 4 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN4R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CHDATIN4R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0x80++0x3 line.long 0x00 "DFSDM_CH4CFGR1,DFSDM channel Configuration 4 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CHDATIN4R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0x80))&0x80)==0x0) group.long (0x80+0x04)++0x07 line.long 0x00 "DFSDM_CH4CFGR2,DFSDM Channel Configuration 4 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4" else group.long (0x80+0x04)++0x07 line.long 0x00 "DFSDM_CH4CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4" endif rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DFSDM_CH4WDATR,DFSDM Channel 4 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 4 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0x80))&0x3000)==(0x2000||0x1000)) group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 4 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" textline " " else rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 4 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" textline " " endif else if (((per.l(ad:0x40016000+0x80))&0x3000)==0x2000) group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 4 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" textline " " else rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 4 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" textline " " endif endif tree.end tree "Channel 5" if (((per.l(ad:0x40016000+0xA0))&0x80)==0x0) group.long 0xA0++0x3 line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel Configuration 5 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN5R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CHDATIN5R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0xA0++0x3 line.long 0x00 "DFSDM_CH5CFGR1,DFSDM channel Configuration 5 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CHDATIN5R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0xA0))&0x80)==0x0) group.long (0xA0+0x04)++0x07 line.long 0x00 "DFSDM_CH5CFGR2,DFSDM Channel Configuration 5 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5" else group.long (0xA0+0x04)++0x07 line.long 0x00 "DFSDM_CH5CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5" endif rgroup.long (0xA0+0x0C)++0x03 line.long 0x00 "DFSDM_CH5WDATR,DFSDM Channel 5 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 5 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0xA0))&0x3000)==(0x2000||0x1000)) group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 5 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" textline " " else rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 5 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" textline " " endif else if (((per.l(ad:0x40016000+0xA0))&0x3000)==0x2000) group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 5 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" textline " " else rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 5 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" textline " " endif endif tree.end tree "Channel 6" if (((per.l(ad:0x40016000+0xC0))&0x80)==0x0) group.long 0xC0++0x3 line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel Configuration 6 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN6R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CHDATIN6R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0xC0++0x3 line.long 0x00 "DFSDM_CH6CFGR1,DFSDM channel Configuration 6 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CHDATIN6R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0xC0))&0x80)==0x0) group.long (0xC0+0x04)++0x07 line.long 0x00 "DFSDM_CH6CFGR2,DFSDM Channel Configuration 6 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6" else group.long (0xC0+0x04)++0x07 line.long 0x00 "DFSDM_CH6CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6" endif rgroup.long (0xC0+0x0C)++0x03 line.long 0x00 "DFSDM_CH6WDATR,DFSDM Channel 6 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 6 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0xC0))&0x3000)==(0x2000||0x1000)) group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 6 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" textline " " else rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 6 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" textline " " endif else if (((per.l(ad:0x40016000+0xC0))&0x3000)==0x2000) group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 6 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" textline " " else rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 6 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" textline " " endif endif tree.end tree "Channel 7" if (((per.l(ad:0x40016000+0xE0))&0x80)==0x0) group.long 0xE0++0x3 line.long 0x00 "DFSDM_CH7CFGR1,DFSDM Channel Configuration 7 register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,Dual,?..." textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,Internal analog to digital converter,Internal DFSDM_CHDATIN7R,?..." textline " " else bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CHDATIN7R,?..." textline " " endif bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel" bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled" bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" else group.long 0xE0++0x3 line.long 0x00 "DFSDM_CH7CFGR1,DFSDM channel Configuration 7 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CHDATIN7R,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" endif if (((per.l(ad:0x40016000+0xE0))&0x80)==0x0) group.long (0xE0+0x04)++0x07 line.long 0x00 "DFSDM_CH7CFGR2,DFSDM Channel Configuration 7 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 7" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH7AWSCDR,DFSDM Channel Analog Watchdog and Short-Circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 7" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 7" else group.long (0xE0+0x04)++0x07 line.long 0x00 "DFSDM_CH7CFGR2,DFSDM channel configuration y register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 7" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH7AWSCDR,DFSDM analog watchdog and short-circuit detector register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 7" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 7" endif rgroup.long (0xE0+0x0C)++0x03 line.long 0x00 "DFSDM_CH7WDATR,DFSDM Channel 7 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 7 watchdog data" sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")) if (((per.l(ad:0x40016000+0xE0))&0x3000)==(0x2000||0x1000)) group.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 7 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7" textline " " else rgroup.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 7 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7" textline " " endif else if (((per.l(ad:0x40016000+0xE0))&0x3000)==0x2000) group.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 7 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7" textline " " else rgroup.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Input data for channel 7 or channel y+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7" textline " " endif endif tree.end tree "Module 0 registers" if (((per.l(ad:0x40016000+0x100))&0x1)==0x0) group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "JTRG0,JTRG1,JTRG2,JTRG3,JTRG5,JTRG7,JTRG9,JTRG10" textline " " else bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "INTRG0,INTRG1,INTRG2,INTRG3,INTRG5,INTRG7,EXTRG0,EXTRG1" textline " " endif bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 0 enable" "Disabled,Enabled" else group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM control register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32F76*")||cpuis("STM32F77*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..." elif (cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_JTRG0,DFSDM_JTRG1,DFSDM_JTRG2,DFSDM_JTRG3,DFSDM_JTRG5,DFSDM_JTRG7,DFSDM_JTRG9,DFSDM_JTRG10" textline " " elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " else rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_INTRG0,DFSDM_INTRG1,DFSDM_INTRG2,DFSDM_INTRG3,DFSDM_INTRG5,DFSDM_INTRG7,DFSDM_EXTRG0,DFSDM_EXTRG1" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 0 enable" "Disabled,Enabled" endif group.long (0x100+0x04)++0x03 line.long 0x00 "DFSDM_FLT0CR2,DFSDM Control Register 2" bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "No data accept,Accepts data" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "No data accept,Accepts data" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "No data accept,Accepts data" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "No data accept,Accepts data" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "No data accept,Accepts data" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" rgroup.long (0x100+0x08)++0x03 line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt and Status Register" bitfld.long 0x00 31. " SCDF[7] ,Short-circuit 7 detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Short-circuit 6 detector flag" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,Short-circuit 5 detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Short-circuit 4 detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,Short-circuit 3 detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Short-circuit 2 detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Short-circuit 1 detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Short-circuit 0 detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " CKABF[7] ,Clock absence flag 7" "Present,Absent" bitfld.long 0x00 22. " [6] ,Clock absence flag 6" "Present,Absent" bitfld.long 0x00 21. " [5] ,Clock absence flag 5" "Present,Absent" bitfld.long 0x00 20. " [4] ,Clock absence flag 4" "Present,Absent" textline " " bitfld.long 0x00 19. " [3] ,Clock absence flag 3" "Present,Absent" bitfld.long 0x00 18. " [2] ,Clock absence flag 2" "Present,Absent" bitfld.long 0x00 17. " [1] ,Clock absence flag 1" "Present,Absent" bitfld.long 0x00 16. " [0] ,Clock absence flag 0" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" group.long (0x100+0x0C)++0x07 line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register" eventfld.long 0x00 31. " CLRSCDF[7] ,Clear the short-circuit detector flag 7" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Clear the short-circuit detector flag 6" "No effect,Clear" eventfld.long 0x00 29. " [5] ,Clear the short-circuit detector flag 5" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Clear the short-circuit detector flag 4" "No effect,Clear" textline " " eventfld.long 0x00 27. " [3] ,Clear the short-circuit detector flag 3" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Clear the short-circuit detector flag 2" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Clear the short-circuit detector flag 1" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Clear the short-circuit detector flag 0" "No effect,Clear" textline " " eventfld.long 0x00 23. " CLRCKABF[7] ,Clear the clock absence flag 7" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Clear the clock absence flag 6" "No effect,Clear" eventfld.long 0x00 21. " [5] ,Clear the clock absence flag 5" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Clear the clock absence flag 4" "No effect,Clear" textline " " eventfld.long 0x00 19. " [3] ,Clear the clock absence flag 3" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Clear the clock absence flag 2" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Clear the clock absence flag 1" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Clear the clock absence flag 0" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear" line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register" bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" if (((per.l(ad:0x40016000+0x100))&0x1)==0x0) group.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif if (((per.l(ad:0x40016000+0x100)&0x20)==0x20)) hgroup.long (0x100+0x18)++0x03 hide.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" in else rgroup.long (0x100+0x18)++0x03 line.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Sinc filter oversampling ratio (decimation rate)" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" endif hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Data Register for The Regular Channel" in group.long (0x100+0x20)++0x07 line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" rgroup.long (0x100+0x28)++0x03 line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register" bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" group.long (0x100+0x2C)++0x03 line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register" eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear" hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x100+0x34)++0x03 hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x100+0x38)++0x03 line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDMCLK" tree.end tree "Module 1 registers" if (((per.l(ad:0x40016000+0x180))&0x1)==0x0) group.long 0x180++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "JTRG0,JTRG1,JTRG2,JTRG3,JTRG5,JTRG7,JTRG9,JTRG10" textline " " else bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "INTRG0,INTRG1,INTRG2,INTRG3,INTRG5,INTRG7,EXTRG0,EXTRG1" textline " " endif bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 1 enable" "Disabled,Enabled" else group.long 0x180++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM control register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32F76*")||cpuis("STM32F77*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..." elif (cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_JTRG0,DFSDM_JTRG1,DFSDM_JTRG2,DFSDM_JTRG3,DFSDM_JTRG5,DFSDM_JTRG7,DFSDM_JTRG9,DFSDM_JTRG10" textline " " elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " else rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_INTRG0,DFSDM_INTRG1,DFSDM_INTRG2,DFSDM_INTRG3,DFSDM_INTRG5,DFSDM_INTRG7,DFSDM_EXTRG0,DFSDM_EXTRG1" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 1 enable" "Disabled,Enabled" endif group.long (0x180+0x04)++0x03 line.long 0x00 "DFSDM_FLT1CR2,DFSDM Control Register 2" bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "No data accept,Accepts data" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "No data accept,Accepts data" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "No data accept,Accepts data" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "No data accept,Accepts data" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "No data accept,Accepts data" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" rgroup.long (0x180+0x08)++0x03 line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt and Status Register" bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" group.long (0x180+0x0C)++0x07 line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register" eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear" line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register" bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" if (((per.l(ad:0x40016000+0x180))&0x1)==0x0) group.long (0x180+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x180+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif if (((per.l(ad:0x40016000+0x180)&0x20)==0x20)) hgroup.long (0x180+0x18)++0x03 hide.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" in else rgroup.long (0x180+0x18)++0x03 line.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Sinc filter oversampling ratio (decimation rate)" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" endif hgroup.long (0x180+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Data Register for The Regular Channel" in group.long (0x180+0x20)++0x07 line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" rgroup.long (0x180+0x28)++0x03 line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register" bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" group.long (0x180+0x2C)++0x03 line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register" eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear" hgroup.long (0x180+0x30)++0x03 hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x180+0x34)++0x03 hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x180+0x38)++0x03 line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDMCLK" tree.end tree "Module 2 registers" if (((per.l(ad:0x40016000+0x200))&0x1)==0x0) group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "JTRG0,JTRG1,JTRG2,JTRG3,JTRG5,JTRG8,JTRG9,JTRG10" textline " " else bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "INTRG0,INTRG1,INTRG2,INTRG3,INTRG5,INTRG8,EXTRG0,EXTRG1" textline " " endif bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 2 enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM control register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32F76*")||cpuis("STM32F77*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..." elif (cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_JTRG0,DFSDM_JTRG1,DFSDM_JTRG2,DFSDM_JTRG3,DFSDM_JTRG5,DFSDM_JTRG8,DFSDM_JTRG9,DFSDM_JTRG10" textline " " elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM4_TRGO,TIM7_TRGO,EXTI11,EXTI15" textline " " else rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_INTRG0,DFSDM_INTRG1,DFSDM_INTRG2,DFSDM_INTRG3,DFSDM_INTRG5,DFSDM_INTRG8,DFSDM_EXTRG0,DFSDM_EXTRG1" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 2 enable" "Disabled,Enabled" endif group.long (0x200+0x04)++0x03 line.long 0x00 "DFSDM_FLT2CR2,DFSDM Control Register 2" bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "No data accept,Accepts data" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "No data accept,Accepts data" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "No data accept,Accepts data" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "No data accept,Accepts data" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "No data accept,Accepts data" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" rgroup.long (0x200+0x08)++0x03 line.long 0x00 "DFSDM_FLT2ISR,DFSDM Interrupt and Status Register" bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" group.long (0x200+0x0C)++0x07 line.long 0x00 "DFSDM_FLT2ICR,DFSDM Interrupt Flag Clear Register" eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear" line.long 0x04 "DFSDM_FLT2JCHGR,DFSDM Injected Channel Group Selection Register" bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" if (((per.l(ad:0x40016000+0x200))&0x1)==0x0) group.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif if (((per.l(ad:0x40016000+0x200)&0x20)==0x20)) hgroup.long (0x200+0x18)++0x03 hide.long 0x00 "DFSDM_FLT2JDATAR,Injected Group Conversion Data" in else rgroup.long (0x200+0x18)++0x03 line.long 0x00 "DFSDM_FLT2JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Sinc filter oversampling ratio (decimation rate)" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" endif hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT2RDATAR,DFSDM Data Register for The Regular Channel" in group.long (0x200+0x20)++0x07 line.long 0x00 "DFSDM_FLT2AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT2AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" rgroup.long (0x200+0x28)++0x03 line.long 0x00 "DFSDM_FLT2AWSR,DFSDM Analog Watchdog Status Register" bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" group.long (0x200+0x2C)++0x03 line.long 0x00 "DFSDM_FLT2AWCFR,DFSDM Analog Watchdog Clear Flag Register" eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear" hgroup.long (0x200+0x30)++0x03 hide.long 0x00 "DFSDM_FLT2EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x200+0x34)++0x03 hide.long 0x00 "DFSDM_FLT2EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x200+0x38)++0x03 line.long 0x00 "DFSDM_FLT2CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDMCLK" tree.end tree "Module 3 registers" if (((per.l(ad:0x40016000+0x280))&0x1)==0x0) group.long 0x280++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "JTRG0,JTRG1,JTRG2,JTRG4,JTRG6,JTRG8,JTRG9,JTRG10" textline " " else bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "INTRG0,INTRG1,INTRG2,INTRG4,INTRG6,INTRG8,EXTRG0,EXTRG1" textline " " endif bitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 3 enable" "Disabled,Enabled" else group.long 0x280++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM control register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" rbitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" textline " " rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif (cpuis("STM32F76*")||cpuis("STM32F77*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM10_OC1,TIM6_TRGO,TIM7_TRGO,,,,,,,,,,,,,,,EXTI11,EXTI15,LPTIMER1,?..." elif (cpuis("STM32L475*"))||(cpuis("STM32L476*"))||(cpuis("STM32L486*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_JTRG0,DFSDM_JTRG1,DFSDM_JTRG2,DFSDM_JTRG4,DFSDM_JTRG6,DFSDM_JTRG8,DFSDM_JTRG9,DFSDM_JTRG10" textline " " elif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM3_TRGO,TIM16_OC1,TIM7_TRGO,EXTI11,EXTI15" textline " " else rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "DFSDM_INTRG0,DFSDM_INTRG1,DFSDM_INTRG2,DFSDM_INTRG4,DFSDM_INTRG6,DFSDM_INTRG8,DFSDM_EXTRG0,DFSDM_EXTRG1" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started conv" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM 3 enable" "Disabled,Enabled" endif group.long (0x280+0x04)++0x03 line.long 0x00 "DFSDM_FLT3CR2,DFSDM Control Register 2" bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "No data accept,Accepts data" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "No data accept,Accepts data" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "No data accept,Accepts data" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "No data accept,Accepts data" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "No data accept,Accepts data" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "No data accept,Accepts data" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "No data accept,Accepts data" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" rgroup.long (0x280+0x08)++0x03 line.long 0x00 "DFSDM_FLT3ISR,DFSDM Interrupt and Status Register" bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" group.long (0x280+0x0C)++0x07 line.long 0x00 "DFSDM_FLT3ICR,DFSDM Interrupt Flag Clear Register" eventfld.long 0x00 3. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Clear" line.long 0x04 "DFSDM_FLT3JCHGR,DFSDM Injected Channel Group Selection Register" bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" if (((per.l(ad:0x40016000+0x280))&0x1)==0x0) group.long (0x280+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x280+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif if (((per.l(ad:0x40016000+0x280)&0x20)==0x20)) hgroup.long (0x280+0x18)++0x03 hide.long 0x00 "DFSDM_FLT3JDATAR,Injected Group Conversion Data" in else rgroup.long (0x280+0x18)++0x03 line.long 0x00 "DFSDM_FLT3JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Sinc filter oversampling ratio (decimation rate)" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" endif hgroup.long (0x280+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT3RDATAR,DFSDM Data Register for The Regular Channel" in group.long (0x280+0x20)++0x07 line.long 0x00 "DFSDM_FLT3AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" bitfld.long 0x00 3. " BKAWH3 ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " BKAWH2 ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x00 1. " BKAWH1 ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " BKAWH0 ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT3AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" bitfld.long 0x04 3. " BKAWL3 ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " BKAWL2 ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " bitfld.long 0x04 1. " BKAWL1 ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " BKAWL0 ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" rgroup.long (0x280+0x28)++0x03 line.long 0x00 "DFSDM_FLT3AWSR,DFSDM Analog Watchdog Status Register" bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" group.long (0x280+0x2C)++0x03 line.long 0x00 "DFSDM_FLT3AWCFR,DFSDM Analog Watchdog Clear Flag Register" eventfld.long 0x00 15. " CLRAWHTF[7] ,Clear the analog watchdog high threshold flag 7" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Clear the analog watchdog high threshold flag 6" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Clear the analog watchdog high threshold flag 5" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Clear the analog watchdog high threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Clear the analog watchdog high threshold flag 3" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Clear the analog watchdog high threshold flag 2" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Clear the analog watchdog high threshold flag 1" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Clear the analog watchdog high threshold flag 0" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Clear the analog watchdog low threshold flag 7" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Clear the analog watchdog low threshold flag 6" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Clear the analog watchdog low threshold flag 5" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Clear the analog watchdog low threshold flag 4" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Clear the analog watchdog low threshold flag 3" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Clear the analog watchdog low threshold flag 2" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Clear the analog watchdog low threshold flag 1" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Clear the analog watchdog low threshold flag 0" "No effect,Clear" hgroup.long (0x280+0x30)++0x03 hide.long 0x00 "DFSDM_FLT3EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x280+0x34)++0x03 hide.long 0x00 "DFSDM_FLT3EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x280+0x38)++0x03 line.long 0x00 "DFSDM_FLT3CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDMCLK" tree.end width 0x0B tree.end endif sif (cpuis("STM32L4?3*"))||(cpuis("STM32L4?6*"))||(cpuis("STM32L?2*"))||(cpuis("STM32L475*")) tree "LCD (Liquid crystal display controller)" base ad:0x40002400 width 9. if (((per.l(ad:0x40002408))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "LCD_CR,LCD control register" bitfld.long 0x00 8. " BUFEN ,Voltage output buffer enable" "Disabled,Enabled" bitfld.long 0x00 7. " MUX_SEG ,Mux segment enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " BIAS ,Bias selector" "1/4,1/2,1/3,?..." bitfld.long 0x00 2.--4. " DUTY ,Duty selection" "Static,1/2,1/3,1/4,1/8,?..." textline " " bitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External" bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "LCD_CR,LCD control register" rbitfld.long 0x00 8. " BUFEN ,Voltage output buffer enable" "Disabled,Enabled" rbitfld.long 0x00 7. " MUX_SEG ,Mux segment enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " BIAS ,Bias selector" "1/4,1/2,1/3,?..." rbitfld.long 0x00 2.--4. " DUTY ,Duty selection" "Static,1/2,1/3,1/4,1/8,?..." textline " " rbitfld.long 0x00 1. " VSEL ,Voltage source selection" "Internal,External" bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "LCD_FCR,LCD frame control register" bitfld.long 0x00 22.--25. " PS ,PS 16-bit prescaler" "LCDCLK,LCDCLK/2,LCDCLK/4,LCDCLK/8,LCDCLK/16,LCDCLK/32,LCDCLK/64,LCDCLK/128,LCDCLK/256,LCDCLK/512,LCDCLK/1024,LCDCLK/2048,LCDCLK/4096,LCDCLK/8192,LCDCLK/16384,LCDCLK/32768" bitfld.long 0x00 18.--21. " DIV ,DIV clock divider" "ck_ps/16,ck_ps/17,ck_ps/18,ck_ps/19,ck_ps/20,ck_ps/21,ck_ps/22,ck_ps/23,ck_ps/24,ck_ps/25,ck_ps/26,ck_ps/27,ck_ps/28,ck_ps/29,ck_ps/30,ck_ps/31" bitfld.long 0x00 16.--17. " BLINK ,Blink mode selection" "Disabled,SEG[0]_COM[0],SEG[0]_allCOMs,AllSEGs_allCOMs" bitfld.long 0x00 13.--15. " BLINKF ,Blink frequency selection" "fLCD/8,fLCD/16,fLCD/32,fLCD/64,fLCD/128,fLCD/256,fLCD/512,fLCD/1024" textline " " bitfld.long 0x00 10.--12. " CC ,Contrast control" "VLCD0,VLCD1,VLCD2,VLCD3,VLCD4,VLCD5,VLCD6,VLCD7" bitfld.long 0x00 7.--9. " DEAD ,Dead time duration" "No time,1phase,2phase,3phase,4phase,5phase,6phase,7phase" bitfld.long 0x00 4.--6. " PON ,Pulse ON duration" "0,1/ck_ps,2/ck_ps,3/ck_ps,4/ck_ps,5/ck_ps,6/ck_ps,7/ck_ps" bitfld.long 0x00 3. " UDDIE ,Update display done interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFIE ,Start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " HD ,High drive enable" "Disabled,Enabled" rgroup.long 0x08++0x03 line.long 0x00 "LCD_SR,LCD status register" bitfld.long 0x00 5. " FCRSF ,LCD Frame Control Register Synchronization flag" "Not synchronized,Synchronized" bitfld.long 0x00 4. " RDY ,Ready flag" "Not ready,Ready" bitfld.long 0x00 3. " UDD ,Update Display Done" "No effect,Done" bitfld.long 0x00 2. " UDR ,Update display request" "No effect,Requested" textline " " bitfld.long 0x00 1. " SOF ,Start of frame flag" "No effect,Started" bitfld.long 0x00 0. " ENS ,LCD enabled status" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "LCD_CLR,LCD clear register" bitfld.long 0x00 3. " UDDC ,Update display done clear" "No effect,Clear" bitfld.long 0x00 1. " SOFC ,Start of frame flag clear" "No effect,Clear" group.long 0x14++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM0) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM0) 32-43" hexmask.long.word 0x04 0.--11. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x1C++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM1) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM1) 32-43" hexmask.long.word 0x04 0.--11. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x24++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM2) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM2) 32-43" hexmask.long.word 0x04 0.--11. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x2C++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM3) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM3) 32-43" hexmask.long.word 0x04 0.--11. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x34++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM4) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM4) 32-39" hexmask.long.byte 0x04 0.--7. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x3C++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM5) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM5) 32-39" hexmask.long.byte 0x04 0.--7. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x44++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM6) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM6) 32-39" hexmask.long.byte 0x04 0.--7. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" group.long 0x4C++0x07 line.long 0x00 "LCD_RAM,LCD display memory(COM7) 0-31" line.long 0x04 "LCD_RAM,LCD display memory(COM7) 32-39" hexmask.long.byte 0x04 0.--7. 1. " SEGMENT_DATA ,Each bit corresponds to one pixel of the LCD display" width 0x0B tree.end endif tree "TSC (Touch sensing controller)" base ad:0x40024000 width 13. group.long 0x00++0x0B line.long 0x00 "TSC_CR,TSC control register" bitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1x tPGCLK,2x tPGCLK,3x tPGCLK,4x tPGCLK,5x tPGCLK,6x tPGCLK,7x tPGCLK,8x tPGCLK,9x tPGCLK,10x tPGCLK,11x tPGCLK,12x tPGCLK,13x tPGCLK,14x tPGCLK,15x tPGCLK,16 tPGCLK" bitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1x tPGCLK,2x tPGCLK,3x tPGCLK,4x tPGCLK,5x tPGCLK,6x tPGCLK,7x tPGCLK,8x tPGCLK,9x tPGCLK,10x tPGCLK,11x tPGCLK,12x tPGCLK,13x tPGCLK,14x tPGCLK,15x tPGCLK,16 tPGCLK" hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation" bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler" "fHCLK,fHCLK /2" bitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler" "fHCLK,fHCLK/2,fHCLK/4,fHCLK/8,fHCLK/16,fHCLK/32,fHCLK/64,fHCLK/128" bitfld.long 0x00 5.--7. " MCV ,Max count value" "255,511,1023,2047,4095,8191,16383,?..." bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull,Input floating" textline " " bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity" "Falling only,Rising&High" bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized" bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started" bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "TSC_ISR,TSC interrupt status register" setclrfld.long 0x00 1. -0x04 1. -0x08 1. " MCEF_set/clr ,Max count error flag" "No error,Error" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " EOAF_set/clr ,End of acquisition flag" "On-going,Complete" group.long 0x10++0x03 line.long 0x00 "TSC_IOHCR,TSC I/O hysteresis control register" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 31. " G8IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 30. " G8IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 29. " G8IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 28. " G8IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 27. " G7IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 26. " G7IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 25. " G7IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 24. " G7IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " G6IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 22. " G6IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 21. " G6IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 20. " G6IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " G5IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 18. " G5IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 17. " G5IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 16. " G5IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " G4IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 14. " G4IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 13. " G4IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 12. " G4IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " G3IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 10. " G3IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 9. " G3IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 8. " G3IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " G2IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 6. " G2IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 5. " G2IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 4. " G2IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " G1IO4 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 2. " G1IO3 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 1. " G1IO2 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" bitfld.long 0x00 0. " G1IO1 ,Schmitt trigger hysteresis mode" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "TSC_IOASCR,TSC I/O analog switch control register" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 31. " G8IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 30. " G8IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 29. " G8IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 28. " G8IO1 ,Analog switch enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 27. " G7IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 26. " G7IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 25. " G7IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 24. " G7IO1 ,Analog switch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " G6IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 22. " G6IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 21. " G6IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 20. " G6IO1 ,Analog switch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " G5IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 18. " G5IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 17. " G5IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 16. " G5IO1 ,Analog switch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " G4IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 14. " G4IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 13. " G4IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 12. " G4IO1 ,Analog switch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " G3IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 10. " G3IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 9. " G3IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " G3IO1 ,Analog switch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " G2IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 6. " G2IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 5. " G2IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 4. " G2IO1 ,Analog switch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " G1IO4 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 2. " G1IO3 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 1. " G1IO2 ,Analog switch enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1IO1 ,Analog switch enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 31. " G8IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 30. " G8IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 29. " G8IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 28. " G8IO1 ,Sampling mode" "Unused,Used" textline " " endif bitfld.long 0x00 27. " G7IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 26. " G7IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 25. " G7IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 24. " G7IO1 ,Sampling mode" "Unused,Used" textline " " bitfld.long 0x00 23. " G6IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 22. " G6IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 21. " G6IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 20. " G6IO1 ,Sampling mode" "Unused,Used" textline " " bitfld.long 0x00 19. " G5IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 18. " G5IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 17. " G5IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 16. " G5IO1 ,Sampling mode" "Unused,Used" textline " " bitfld.long 0x00 15. " G4IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 14. " G4IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 13. " G4IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 12. " G4IO1 ,Sampling mode" "Unused,Used" textline " " bitfld.long 0x00 11. " G3IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 10. " G3IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 9. " G3IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 8. " G3IO1 ,Sampling mode" "Unused,Used" textline " " bitfld.long 0x00 7. " G2IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 6. " G2IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 5. " G2IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 4. " G2IO1 ,Sampling mode" "Unused,Used" textline " " bitfld.long 0x00 3. " G1IO4 ,Sampling mode" "Unused,Used" bitfld.long 0x00 2. " G1IO3 ,Sampling mode" "Unused,Used" bitfld.long 0x00 1. " G1IO2 ,Sampling mode" "Unused,Used" bitfld.long 0x00 0. " G1IO1 ,Sampling mode" "Unused,Used" group.long 0x28++0x03 line.long 0x00 "TSC_IOCCR,TSC I/O channel control register" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 31. " G8IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 30. " G8IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 29. " G8IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 28. " G8IO1 ,Channel mode" "Unused,Used" textline " " endif bitfld.long 0x00 27. " G7IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 26. " G7IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 25. " G7IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 24. " G7IO1 ,Channel mode" "Unused,Used" textline " " bitfld.long 0x00 23. " G6IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 22. " G6IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 21. " G6IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 20. " G6IO1 ,Channel mode" "Unused,Used" textline " " bitfld.long 0x00 19. " G5IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 18. " G5IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 17. " G5IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 16. " G5IO1 ,Channel mode" "Unused,Used" textline " " bitfld.long 0x00 15. " G4IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 14. " G4IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 13. " G4IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 12. " G4IO1 ,Channel mode" "Unused,Used" textline " " bitfld.long 0x00 11. " G3IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 10. " G3IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 9. " G3IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 8. " G3IO1 ,Channel mode" "Unused,Used" textline " " bitfld.long 0x00 7. " G2IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 6. " G2IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 5. " G2IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 4. " G2IO1 ,Channel mode" "Unused,Used" textline " " bitfld.long 0x00 3. " G1IO4 ,Channel mode" "Unused,Used" bitfld.long 0x00 2. " G1IO3 ,Channel mode" "Unused,Used" bitfld.long 0x00 1. " G1IO2 ,Channel mode" "Unused,Used" bitfld.long 0x00 0. " G1IO1 ,Channel mode" "Unused,Used" group.long 0x30++0x03 line.long 0x00 "TSC_IOGCSR,TSC I/O group control status register" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) rbitfld.long 0x00 23. " G8S ,Analog I/O group 8 status" "On-going,Complete" textline " " endif rbitfld.long 0x00 22. " G7S ,Analog I/O group 7 status" "On-going,Complete" rbitfld.long 0x00 21. " G6S ,Analog I/O group 6 status" "On-going,Complete" rbitfld.long 0x00 20. " G5S ,Analog I/O group 5 status" "On-going,Complete" rbitfld.long 0x00 19. " G4S ,Analog I/O group 4 status" "On-going,Complete" textline " " rbitfld.long 0x00 18. " G3S ,Analog I/O group 3 status" "On-going,Complete" rbitfld.long 0x00 17. " G2S ,Analog I/O group 2 status" "On-going,Complete" rbitfld.long 0x00 16. " G1S ,Analog I/O group 1 status" "On-going,Complete" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 7. " G8E ,Analog I/O group 8 enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 6. " G7E ,Analog I/O group 7 enable" "Disabled,Enabled" bitfld.long 0x00 5. " G6E ,Analog I/O group 6 enable" "Disabled,Enabled" bitfld.long 0x00 4. " G5E ,Analog I/O group 5 enable" "Disabled,Enabled" bitfld.long 0x00 3. " G4E ,Analog I/O group 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G3E ,Analog I/O group 3 enable" "Disabled,Enabled" bitfld.long 0x00 1. " G2E ,Analog I/O group 2 enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1E ,Analog I/O group 1 enable" "Disabled,Enabled" sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) rgroup.long 0x34++0x03 line.long 0x00 "TSC_IOG1CR,TSC I/O group 1 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x38++0x03 line.long 0x00 "TSC_IOG2CR,TSC I/O group 2 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x3C++0x03 line.long 0x00 "TSC_IOG3CR,TSC I/O group 3 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x40++0x03 line.long 0x00 "TSC_IOG4CR,TSC I/O group 4 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x44++0x03 line.long 0x00 "TSC_IOG5CR,TSC I/O group 5 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x48++0x03 line.long 0x00 "TSC_IOG6CR,TSC I/O group 6 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x4C++0x03 line.long 0x00 "TSC_IOG7CR,TSC I/O group 7 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" else rgroup.long 0x34++0x03 line.long 0x00 "TSC_IOG1CR,TSC I/O group 1 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x38++0x03 line.long 0x00 "TSC_IOG2CR,TSC I/O group 2 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x3C++0x03 line.long 0x00 "TSC_IOG3CR,TSC I/O group 3 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x40++0x03 line.long 0x00 "TSC_IOG4CR,TSC I/O group 4 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x44++0x03 line.long 0x00 "TSC_IOG5CR,TSC I/O group 5 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x48++0x03 line.long 0x00 "TSC_IOG6CR,TSC I/O group 6 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x4C++0x03 line.long 0x00 "TSC_IOG7CR,TSC I/O group 7 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" rgroup.long 0x50++0x03 line.long 0x00 "TSC_IOG8CR,TSC I/O group 8 counter register" hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value" endif width 0x0B tree.end tree "RNG (Random number generator)" base ad:0x50060800 width 8. group.long 0x00++0x07 line.long 0x00 "RNG_CR,RNG Control Register" bitfld.long 0x00 3. " IE ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RNGEN ,Random number generator enable" "Disabled,Enabled" line.long 0x04 "RNG_SR,RNG Status Register" bitfld.long 0x04 6. " SEIS ,Seed error interrupt status" "No error,Error" bitfld.long 0x04 5. " CEIS ,Clock error interrupt status" "No error,Error" rbitfld.long 0x04 2. " SECS ,Seed error current status" "No error,Error" rbitfld.long 0x04 1. " CECS ,Clock error current status" "No error,Error" textline " " rbitfld.long 0x04 0. " DRDY ,Data ready" "Invalid register,Valid random data" rgroup.long 0x08++0x03 line.long 0x00 "RNG_DR,RNG Data Register" width 0x0B tree.end sif (!cpuis("STM32L4?1*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L433*"))&&(!cpuis("STM32L452*")) tree "AES (Advanced encryption standard hardware accelerator)" base ad:0x50060000 width 12. if (((per.l(ad:0x50060000))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "AES_CR,AES Control Register" bitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b" bitfld.long 0x00 13.--14. " GCMPH ,Used only for GCM_GMAC_CMAC algorithms and has no effect when other algorithms are selected" "Init,Header,Payload,Final" bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled" bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear" bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear" textline " " bitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&&GMAC,CMAC,?..." bitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key_der + Decrypt" bitfld.long 0x00 1.--2. " DATATYPE ,Data type selection (for data in and data out to/from the cryptographic block)" "32b-no swap,16b-swapped,8b-swapped,1b-swapped" bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "AES_CR,AES Control Register" rbitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b" bitfld.long 0x00 13.--14. " GCMPH ,Used only for GCM_GMAC_CMAC algorithms and has no effect when other algorithms are selected" "Init,Header,Payload,Final" bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled" bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear" bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear" textline " " rbitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&&GMAC,CMAC,?..." rbitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key_der + Decrypt" rbitfld.long 0x00 1.--2. " DATATYPE ,Data type selection (for data in and data out to/from the cryptographic block)" "32b-no swap,16b-swapped,8b-swapped,1b-swapped" bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled" endif rgroup.long 0x04++0x03 line.long 0x00 "AES_SR,AES Status Register" bitfld.long 0x00 3. " BUSY ,Busy flag" "Idle,Busy" bitfld.long 0x00 2. " WRERR ,Write error flag" "No error,Error" bitfld.long 0x00 1. " RDERR ,Read error flag" "No error,Error" bitfld.long 0x00 0. " CCF ,Computation complete flag" "Completed,Not completed" group.long 0x08++0x03 line.long 0x00 "AES_DINR,AES Data Input Register" rgroup.long 0x0C++0x03 line.long 0x00 "AES_DOUTR,AES Data Output Register" group.long 0x10++0x1F line.long 0x00 "AES_KEYR0,AES Key Register 0 [31:0]" line.long 0x04 "AES_KEYR1,AES Key Register 1 [63:32]" line.long 0x08 "AES_KEYR2,AES Key Register 2 [95:64]" line.long 0x0C "AES_KEYR3,AES Key Register 3 [127:96]" line.long 0x10 "AES_IVR0,AES Initialization Vector Register 0 [31:0]" line.long 0x14 "AES_IVR1,AES Initialization Vector Register 1 [63:32]" line.long 0x18 "AES_IVR2,AES Initialization Vector Register 2 [95:64]" line.long 0x1C "AES_IVR3,AES Initialization Vector Register 3 [127:96]" sif cpuis("STM32F423?H")||cpuis("STM32L4?6*")||cpuis("STM32L44*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") if (((per.l(ad:0x50060000))&0x40000)==0x40000) group.long 0x30++0x0F line.long 0x00 "AES_KEYR4,AES Key Register 4 [159:128]" line.long 0x04 "AES_KEYR5,AES Key Register 5 [191:160]" line.long 0x08 "AES_KEYR6,AES Key Register 6 [223:192]" line.long 0x0c "AES_KEYR7,AES Key Register 7 [255:224]" endif else if (((per.l(ad:0x50060000))&0x40000)==0x40000) group.long 0x30++0x0F line.long 0x00 "AES_IVR4,AES Initialization Vector Register 4 [159:128]" line.long 0x04 "AES_IVR5,AES Initialization Vector Register 5 [191:160]" line.long 0x08 "AES_IVR6,AES Initialization Vector Register 6 [223:192]" line.long 0x0c "AES_IVR7,AES Initialization Vector Register 7 [255:224]" endif endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x40++0x03 line.long 0x00 "AES_SUSP0R,AES Suspend Register" else wgroup.long 0x40++0x03 line.long 0x00 "AES_SUSP0R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x44++0x03 line.long 0x00 "AES_SUSP1R,AES Suspend Register" else wgroup.long 0x44++0x03 line.long 0x00 "AES_SUSP1R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x48++0x03 line.long 0x00 "AES_SUSP2R,AES Suspend Register" else wgroup.long 0x48++0x03 line.long 0x00 "AES_SUSP2R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x4C++0x03 line.long 0x00 "AES_SUSP3R,AES Suspend Register" else wgroup.long 0x4C++0x03 line.long 0x00 "AES_SUSP3R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x50++0x03 line.long 0x00 "AES_SUSP4R,AES Suspend Register" else wgroup.long 0x50++0x03 line.long 0x00 "AES_SUSP4R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x54++0x03 line.long 0x00 "AES_SUSP5R,AES Suspend Register" else wgroup.long 0x54++0x03 line.long 0x00 "AES_SUSP5R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x58++0x03 line.long 0x00 "AES_SUSP6R,AES Suspend Register" else wgroup.long 0x58++0x03 line.long 0x00 "AES_SUSP6R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x5C++0x03 line.long 0x00 "AES_SUSP7R,AES Suspend Register" else wgroup.long 0x5C++0x03 line.long 0x00 "AES_SUSP7R,AES Suspend Register" endif width 0x0B tree.end endif tree "TIM1/TIM8 (Advanced-control timers 1/8)" tree "TIM1" base ad:0x40012C00 width 12. if ((((per.l(ad:0x40012C00))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40012C00+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv ctrl,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM1_CR1,TIM1 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv ctrl,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif if (((per.l(ad:0x40012C00+0x44))&0x300)==0x00) group.long 0x04++0x03 line.long 0x00 "TIM1_CR2,TIM1 control register 2" bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF),Compare(OC5REF),Compare(OC6REF),CompPulse(OC4REF ris/fal),CompPulse(OC6REF ris/fal),CompPulse(OC4REF/OC6REF ris),CompPulse(OC4REF ris/OC6REF fal),CompPulse(OC5REF/OC6REF ris),CompPulse(OC5REF ris/OC6REF fal)" bitfld.long 0x00 18. " OIS6 ,Output Idle state 6" "OC6=0,OC6=1" bitfld.long 0x00 16. " OIS5 ,Output Idle state 5" "OC5=0,OC5=1" textline " " bitfld.long 0x00 14. " OIS4 ,Output Idle state 4" "OC4=0,OC4=1" bitfld.long 0x00 13. " OIS3N ,Output Idle state 3" "OC3N=0,OC3N=1" bitfld.long 0x00 12. " OIS3 ,Output Idle state 3" "OC3=0,OC3=1" textline " " bitfld.long 0x00 11. " OIS2N ,Output Idle state 2" "OC2N=0,OC2N=1" bitfld.long 0x00 10. " OIS2 ,Output Idle state 2" "OC2=0,OC2=1" bitfld.long 0x00 9. " OIS1N ,Output Idle state 1" "OC1N=0,OC1N=1" textline " " bitfld.long 0x00 8. " OIS1 ,Output Idle state 1" "OC1=0,OC1=1" bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" textline " " bitfld.long 0x00 3. " CCDS ,Capture/compare DMA selection" "CC1 occurred,Update occurred" bitfld.long 0x00 2. " CCUS ,Capture/compare control update selection" "COMG only,COMGorTRGI(Rising)" bitfld.long 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" else group.long 0x04++0x03 line.long 0x00 "TIM1_CR2,TIM1 control register 2" bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF),Compare(OC5REF),Compare(OC6REF),CompPulse(OC4REF ris/fal),CompPulse(OC6REF ris/fal),CompPulse(OC4REF/OC6REF ris),CompPulse(OC4REF ris/OC6REF fal),CompPulse(OC5REF/OC6REF ris),CompPulse(OC5REF ris/OC6REF fal)" rbitfld.long 0x00 18. " OIS6 ,Output Idle state 6" "OC6=0,OC6=1" rbitfld.long 0x00 16. " OIS5 ,Output Idle state 5" "OC5=0,OC5=1" textline " " rbitfld.long 0x00 14. " OIS4 ,Output Idle state 4" "OC4=0,OC4=1" rbitfld.long 0x00 13. " OIS3N ,Output Idle state 3" "OC3N=0,OC3N=1" rbitfld.long 0x00 12. " OIS3 ,Output Idle state 3" "OC3=0,OC3=1" textline " " rbitfld.long 0x00 11. " OIS2N ,Output Idle state 2" "OC2N=0,OC2N=1" rbitfld.long 0x00 10. " OIS2 ,Output Idle state 2" "OC2=0,OC2=1" rbitfld.long 0x00 9. " OIS1N ,Output Idle state 1" "OC1N=0,OC1N=1" textline " " rbitfld.long 0x00 8. " OIS1 ,Output Idle state 1" "OC1=0,OC1=1" bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" textline " " bitfld.long 0x00 3. " CCDS ,Capture/compare DMA selection" "CC1 occurred,Update occurred" bitfld.long 0x00 2. " CCUS ,Capture/compare control update selection" "COMG only,COMGorTRGI(Rising)" bitfld.long 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" endif group.long 0x08++0x03 line.long 0x00 "TIM1_SMCR,TIM1 slave mode control register" bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted,Inverted" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,/2,/4,/8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" group.word 0x0C++0x01 line.word 0x00 "TIM1_DIER,TIM1 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "TIM1_SR,TIM1 status register" bitfld.long 0x00 17. " CC6IF ,Compare 6 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 16. " CC5IF ,Compare 5 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " SBIF ,System Break interrupt flag" "No break interrupt,Break interrupt" textline " " bitfld.long 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.long 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.long 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.long 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" bitfld.long 0x00 8. " B2IF ,Break 2 interrupt flag" "No break2 interrupt,Break interrupt" bitfld.long 0x00 7. " BIF ,Break interrupt flag" "No break event,Break interrupt" textline " " bitfld.long 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.long 0x00 5. " COMIF ,COM interrupt flag" "No COM event,COM interrupt" bitfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x03 line.word 0x00 "TIM1_EGR,TIM1 event generation register" bitfld.word 0x00 8. " B2G ,Break 2 generation" "No action,Break2" bitfld.word 0x00 7. " BG ,Break generation" "No action,Break" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" textline " " bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Generate" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" textline " " bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if ((((per.l(ad:0x40012C00+0x18))&0x3)==0x0)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM1_CCMR1,TIM1 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40012C00+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM1_CCMR1,TIM1 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40012C00+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM1_CCMR1,TIM1 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" textline " " bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM1_CCMR1,TIM1 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" textline " " bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM1_CCMR2,TIM1 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40012C00+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM1_CCMR2,TIM1 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40012C00+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM1_CCMR2,TIM1 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" textline " " bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM1_CCMR2,TIM1 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" textline " " bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40012C00+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40012C00+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40012C00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40012C00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40012C00+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40012C00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40012C00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40012C00+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40012C00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40012C00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40012C00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40012C00+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.long 0x20++0x03 line.long 0x00 "TIM1_CCER,TIM1 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40012C00))&0x800)==0x000) group.long 0x24++0x03 line.long 0x00 "TIM1_CNT,TIM1 counter" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" else group.long 0x24++0x03 line.long 0x00 "TIM1_CNT,TIM1 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF copy" "No update,Update interrupt" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" endif group.word 0x28++0x01 line.word 0x00 "TIM1_PSC,TIM1 prescaler" group.word 0x2C++0x01 line.word 0x00 "TIM1_ARR,TIM1 auto-reload register" group.word 0x30++0x01 line.word 0x00 "TIM1_RCR,TIM1 repetition counter register" group.word 0x34++0x01 line.word 0x00 "TIM1_CCR1,TIM1 capture/compare register 1" group.word 0x38++0x01 line.word 0x00 "TIM1_CCR2,TIM1 capture/compare register 2" group.word 0x3C++0x01 line.word 0x00 "TIM1_CCR3,TIM1 capture/compare register 3" group.word 0x40++0x01 line.word 0x00 "TIM1_CCR4,TIM1 capture/compare register 4" if (((per.l(ad:0x40012C00+0x44))&0x300)==0x200) group.long 0x44++0x03 line.long 0x00 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high" bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled" bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" textline " " rbitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" elif (((per.l(ad:0x40012C00+0x44))&0x300)==0x100) group.long 0x44++0x03 line.long 0x00 "TIM1_BDTR,TIM1 break and dead-time register" rbitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high" rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled" rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" textline " " bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" else group.long 0x44++0x03 line.long 0x00 "TIM1_BDTR,TIM1 break and dead-time register" bitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high" bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled" bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" textline " " bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" endif group.word 0x48++0x01 line.word 0x00 "TIM1_DCR,TIM1 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,TIM1_OR1,TIM1_CCMR3,TIM1_CCR5,TIM1_CCR6,TIM1_OR2,TIM1_OR3,?..." group.long 0x4C++0x03 line.long 0x00 "TIM1_DMAR,TIM1 DMA address for full transfer" group.long 0x50++0x03 line.long 0x00 "TIM1_OR1,TIM1 option register 1" bitfld.long 0x00 4. " TI1_RMP ,Input Capture 1 remap" "I/O,COMP1" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 2.--3. " ETR_ADC3_RMP ,External trigger remap on ADC3 analog watchdog" "Not connected,ADC3 AWD1,ADC3 AWD2,ADC3 AWD3" textline " " endif bitfld.long 0x00 0.--1. " ETR_ADC1_RMP ,External trigger remap on ADC1 analog watchdog" "Not connected,ADC1 AWD1,ADC1 AWD2,ADC1 AWD3" if (((per.l(ad:0x40012C00+0x44))&0x300)!=0x300) group.long 0x54++0x03 line.long 0x00 "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x00 15. " OC6CE ,Output Compare 6 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC6PE ,Output Compare 6 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC6FE ,Output Compare 6 fast enable" "Disabled,Enabled" bitfld.long 0x00 7. " OC5CE ,Output Compare 5 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" textline " " bitfld.long 0x00 3. " OC5PE ,Output Compare 5 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC5FE ,Output Compare 5 fast enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "TIM1_CCMR3,TIM1 capture/compare mode register 3" bitfld.long 0x00 15. " OC6CE ,Output Compare 6 clear enable" "Disabled,Enabled" rbitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" rbitfld.long 0x00 11. " OC6PE ,Output Compare 6 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC6FE ,Output Compare 6 fast enable" "Disabled,Enabled" bitfld.long 0x00 7. " OC5CE ,Output Compare 5 clear enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" textline " " rbitfld.long 0x00 3. " OC5PE ,Output Compare 5 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC5FE ,Output Compare 5 fast enable" "Disabled,Enabled" endif group.long 0x58++0x03 line.long 0x00 "TIM1_CCR5,TIM1 capture/compare register 5" bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC&&OC5REF" bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC&&OC5REF" bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC&&OC5REF" textline " " hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value" group.word 0x5C++0x01 line.word 0x00 "TIM1_CCR6,TIM1 capture/compare register 6" if (((per.l(ad:0x40012C00+0x44))&0x300)!=0x100) group.long 0x60++0x07 line.long 0x00 "TIM1_OR2,TIM1 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "TIM1_ETR,COMP1-ETR,COMP2-ETR,?..." bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active high,Active low" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active high,Active low" textline " " bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active high,Active low" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 8. " BKDFBK0E ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled" line.long 0x04 "TIM1_OR3,TIM1 option register 3" bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Active high,Active low" bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Active high,Active low" bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN input polarity" "Active high,Active low" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x04 8. " BK2DFBK1E ,BRK2 DFSDM_BREAK[0] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled" else rgroup.long 0x60++0x07 line.long 0x00 "TIM1_OR2,TIM1 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "TIM1_ETR,COMP1-ETR,COMP2-ETR,?..." bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active high,Active low" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active high,Active low" textline " " bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active high,Active low" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 8. " BKDFBK0E ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN2 input enable" "Disabled,Enabled" line.long 0x04 "TIM1_OR3,TIM1 option register 3" bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Active low,Active high" bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Active low,Active high" bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN2 input polarity" "Active low,Active high" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x04 8. " BK2DFBK1E ,BRK2 DFSDM_BREAK[1] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled" bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled" endif width 0x0B tree.end sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) tree "TIM8" base ad:0x40013400 width 12. if ((((per.l(ad:0x40013400))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40013400+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM8_CR1,TIM8 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv ctrl,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM8_CR1,TIM8 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv ctrl,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif if (((per.l(ad:0x40013400+0x44))&0x300)==0x00) group.long 0x04++0x03 line.long 0x00 "TIM8_CR2,TIM8 control register 2" bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF),Compare(OC5REF),Compare(OC6REF),CompPulse(OC4REF ris/fal),CompPulse(OC6REF ris/fal),CompPulse(OC4REF/OC6REF ris),CompPulse(OC4REF ris/OC6REF fal),CompPulse(OC5REF/OC6REF ris),CompPulse(OC5REF ris/OC6REF fal)" bitfld.long 0x00 18. " OIS6 ,Output Idle state 6" "OC6=0,OC6=1" bitfld.long 0x00 16. " OIS5 ,Output Idle state 5" "OC5=0,OC5=1" textline " " bitfld.long 0x00 14. " OIS4 ,Output Idle state 4" "OC4=0,OC4=1" bitfld.long 0x00 13. " OIS3N ,Output Idle state 3" "OC3N=0,OC3N=1" bitfld.long 0x00 12. " OIS3 ,Output Idle state 3" "OC3=0,OC3=1" textline " " bitfld.long 0x00 11. " OIS2N ,Output Idle state 2" "OC2N=0,OC2N=1" bitfld.long 0x00 10. " OIS2 ,Output Idle state 2" "OC2=0,OC2=1" bitfld.long 0x00 9. " OIS1N ,Output Idle state 1" "OC1N=0,OC1N=1" textline " " bitfld.long 0x00 8. " OIS1 ,Output Idle state 1" "OC1=0,OC1=1" bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" textline " " bitfld.long 0x00 3. " CCDS ,Capture/compare DMA selection" "CC8 occurred,Update occurred" bitfld.long 0x00 2. " CCUS ,Capture/compare control update selection" "COMG only,COMGorTRGI(Rising)" bitfld.long 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" else group.long 0x04++0x03 line.long 0x00 "TIM8_CR2,TIM8 control register 2" bitfld.long 0x00 20.--23. " MMS2 ,Master mode selection 2" "Reset,Enable,Update,Compare pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF),Compare(OC5REF),Compare(OC6REF),CompPulse(OC4REF ris/fal),CompPulse(OC6REF ris/fal),CompPulse(OC4REF/OC6REF ris),CompPulse(OC4REF ris/OC6REF fal),CompPulse(OC5REF/OC6REF ris),CompPulse(OC5REF ris/OC6REF fal)" rbitfld.long 0x00 18. " OIS6 ,Output Idle state 6" "OC6=0,OC6=1" rbitfld.long 0x00 16. " OIS5 ,Output Idle state 5" "OC5=0,OC5=1" textline " " rbitfld.long 0x00 14. " OIS4 ,Output Idle state 4" "OC4=0,OC4=1" rbitfld.long 0x00 13. " OIS3N ,Output Idle state 3" "OC3N=0,OC3N=1" rbitfld.long 0x00 12. " OIS3 ,Output Idle state 3" "OC3=0,OC3=1" textline " " rbitfld.long 0x00 11. " OIS2N ,Output Idle state 2" "OC2N=0,OC2N=1" rbitfld.long 0x00 10. " OIS2 ,Output Idle state 2" "OC2=0,OC2=1" rbitfld.long 0x00 9. " OIS1N ,Output Idle state 1" "OC1N=0,OC1N=1" textline " " rbitfld.long 0x00 8. " OIS1 ,Output Idle state 1" "OC1=0,OC1=1" bitfld.long 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.long 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" textline " " bitfld.long 0x00 3. " CCDS ,Capture/compare DMA selection" "CC8 occurred,Update occurred" bitfld.long 0x00 2. " CCUS ,Capture/compare control update selection" "COMG only,COMGorTRGI(Rising)" bitfld.long 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" endif group.long 0x08++0x03 line.long 0x00 "TIM8_SMCR,TIM8 slave mode control register" bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted,Inverted" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,/2,/4,/8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" group.word 0x0C++0x01 line.word 0x00 "TIM8_DIER,TIM8 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "TIM8_SR,TIM8 status register" bitfld.long 0x00 17. " CC6IF ,Compare 6 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 16. " CC5IF ,Compare 5 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 13. " SBIF ,System Break interrupt flag" "No break interrupt,Break interrupt" textline " " bitfld.long 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.long 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.long 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.long 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" bitfld.long 0x00 8. " B2IF ,Break 2 interrupt flag" "No break2 interrupt,Break interrupt" bitfld.long 0x00 7. " BIF ,Break interrupt flag" "No break event,Break interrupt" textline " " bitfld.long 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.long 0x00 5. " COMIF ,COM interrupt flag" "No COM event,COM interrupt" bitfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x03 line.word 0x00 "TIM8_EGR,TIM8 event generation register" bitfld.word 0x00 8. " B2G ,Break 2 generation" "No action,Break2" bitfld.word 0x00 7. " BG ,Break generation" "No action,Break" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" textline " " bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Generate" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" textline " " bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if ((((per.l(ad:0x40013400+0x18))&0x3)==0x0)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM8_CCMR1,TIM8 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40013400+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM8_CCMR1,TIM8 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40013400+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM8_CCMR1,TIM8 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" textline " " bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM8_CCMR1,TIM8 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" textline " " bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM8_CCMR2,TIM8 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40013400+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM8_CCMR2,TIM8 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40013400+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM8_CCMR2,TIM8 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" textline " " bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM8_CCMR2,TIM8 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" textline " " bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40013400+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40013400+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40013400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40013400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40013400+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40013400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40013400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40013400+0x1C))&0x303)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" textline " " bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)==0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.long 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" textline " " bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40013400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40013400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40013400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40013400+0x1C))&0x300)!=0x000) group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.long 0x20++0x03 line.long 0x00 "TIM8_CCER,TIM8 capture/compare enable register" bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output polarity" "Active high,Active low" bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable" "Off,On" bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output polarity" "Active high,Active low" textline " " bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable" "Off,On" bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Off,On" bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On" bitfld.long 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.long 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40013400))&0x800)==0x000) group.long 0x24++0x03 line.long 0x00 "TIM8_CNT,TIM8 counter" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" else group.long 0x24++0x03 line.long 0x00 "TIM8_CNT,TIM8 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF copy" "No update,Update interrupt" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" endif group.word 0x28++0x01 line.word 0x00 "TIM8_PSC,TIM8 prescaler" group.word 0x2C++0x01 line.word 0x00 "TIM8_ARR,TIM8 auto-reload register" group.word 0x30++0x01 line.word 0x00 "TIM8_RCR,TIM8 repetition counter register" group.word 0x34++0x01 line.word 0x00 "TIM8_CCR1,TIM8 capture/compare register 1" group.word 0x38++0x01 line.word 0x00 "TIM8_CCR2,TIM8 capture/compare register 2" group.word 0x3C++0x01 line.word 0x00 "TIM8_CCR3,TIM8 capture/compare register 3" group.word 0x40++0x01 line.word 0x00 "TIM8_CCR4,TIM8 capture/compare register 4" if (((per.l(ad:0x40013400+0x44))&0x300)==0x200) group.long 0x44++0x03 line.long 0x00 "TIM8_BDTR,TIM8 break and dead-time register" bitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high" bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled" bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" textline " " rbitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" elif (((per.l(ad:0x40013400+0x44))&0x300)==0x100) group.long 0x44++0x03 line.long 0x00 "TIM8_BDTR,TIM8 break and dead-time register" rbitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high" rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled" rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" textline " " bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" else group.long 0x44++0x03 line.long 0x00 "TIM8_BDTR,TIM8 break and dead-time register" bitfld.long 0x00 25. " BK2P ,Break 2 polarity" "Active low,Active high" bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled" bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" textline " " bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" endif group.word 0x48++0x01 line.word 0x00 "TIM8_DCR,TIM8 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,TIM1_OR1,TIM1_CCMR3,TIM1_CCR5,TIM1_CCR6,TIM1_OR2,TIM1_OR3,?..." group.long 0x4C++0x03 line.long 0x00 "TIM8_DMAR,TIM8 DMA address for full transfer" group.long 0x50++0x03 line.long 0x00 "TIM8_OR1,TIM8 option register 1" bitfld.long 0x00 4. " TI1_RMP ,Input Capture 1 remap" "I/O,COMP2" bitfld.long 0x00 2.--3. " ETR_ADC3_RMP ,External trigger remap on ADC3 analog watchdog" "Not connected,ADC3 AWD1,ADC3 AWD2,ADC3 AWD3" bitfld.long 0x00 0.--1. " ETR_ADC2_RMP ,External trigger remap on ADC2 analog watchdog" "Not connected,ADC2 AWD1,ADC2 AWD2,ADC2 AWD3" if (((per.l(ad:0x40013400+0x44))&0x300)!=0x300) group.long 0x54++0x03 line.long 0x00 "TIM8_CCMR3,TIM8 capture/compare mode register 3" bitfld.long 0x00 15. " OC6CE ,Output Compare 6 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC6PE ,Output Compare 6 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC6FE ,Output Compare 6 fast enable" "Disabled,Enabled" bitfld.long 0x00 7. " OC5CE ,Output Compare 5 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" textline " " bitfld.long 0x00 3. " OC5PE ,Output Compare 5 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC5FE ,Output Compare 5 fast enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "TIM8_CCMR3,TIM8 capture/compare mode register 3" bitfld.long 0x00 15. " OC6CE ,Output Compare 6 clear enable" "Disabled,Enabled" rbitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" rbitfld.long 0x00 11. " OC6PE ,Output Compare 6 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OC6FE ,Output Compare 6 fast enable" "Disabled,Enabled" bitfld.long 0x00 7. " OC5CE ,Output Compare 5 clear enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" textline " " rbitfld.long 0x00 3. " OC5PE ,Output Compare 5 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC5FE ,Output Compare 5 fast enable" "Disabled,Enabled" endif group.long 0x58++0x03 line.long 0x00 "TIM8_CCR5,TIM8 capture/compare register 5" bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC&&OC5REF" bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC&&OC5REF" bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC&&OC5REF" textline " " hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value" group.word 0x5C++0x01 line.word 0x00 "TIM8_CCR6,TIM8 capture/compare register 6" if (((per.l(ad:0x40013400+0x44))&0x300)!=0x100) group.long 0x60++0x7 line.long 0x00 "TIM8_OR2,TIM8 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "TIM1_ETR,COMP1-ETR,COMP2-ETR,?..." bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active high,Active low" textline " " bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" bitfld.long 0x00 8. " BKDFBK2E ,BRK DFSDM_BREAK[2] enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled" line.long 0x04 "TIM8_OR3,TIM8 option register 3" bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Active low,Active high" bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Active low,Active high" bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN input polarity" "Active low,Active high" textline " " bitfld.long 0x04 8. " BK2DFBK3E ,BRK2 DFSDM_BREAK[3] enable" "Disabled,Enabled" bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled" else rgroup.long 0x60++0x7 line.long 0x00 "TIM8_OR2,TIM8 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "ETR legacy,COMP1-ETR,COMP2-ETR,?..." bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" textline " " bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" bitfld.long 0x00 8. " BKDFBK2E ,BRK DFSDM_BREAK[2] enable" "Disabled,Enabled" bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN input enable" "Disabled,Enabled" line.long 0x04 "TIM8_OR3,TIM8 option register 3" bitfld.long 0x04 11. " BK2CMP2P ,BRK2 COMP2 input polarity" "Active low,Active high" bitfld.long 0x04 10. " BK2CMP1P ,BRK2 COMP1 input polarity" "Active low,Active high" bitfld.long 0x04 9. " BK2INP ,BRK2 BKIN input polarity" "Active low,Active high" textline " " bitfld.long 0x04 8. " BK2DFBK3E ,BRK2 DFSDM_BREAK[3] enable" "Disabled,Enabled" bitfld.long 0x04 2. " BK2CMP2E ,BRK2 COMP2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " BK2CMP1E ,BRK2 COMP1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " BK2INE ,BRK2 BKIN input enable" "Disabled,Enabled" endif width 0x0B tree.end endif tree.end tree "TIM2/3/4/5 (General-purpose timers)" tree "TIM2" base ad:0x40000000 width 12. if ((((per.l(ad:0x40000000))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40000000+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "TIM2_CR2,TIM2 control register 2" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "When CC2 occurs,When update occurs" group.long 0x08++0x03 line.long 0x00 "TIM2_SMCR,TIM2 slave mode control register" bitfld.long 0x00 15. " ETP ,External trigger polarity" "Rising edge,Falling edge" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,Div2,Div4,Div8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif sif (cpuis("STM32L4?5*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" textline " " elif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||(cpuis("STM32L451*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." group.word 0x0C++0x01 line.word 0x00 "TIM2_DIER,TIM2 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM2_SR,TIM2 status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM2_EGR,TIM2 event generation register" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40000000+0x18))&0x303)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM2_CCMR1,TIM2 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000000+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM2_CCMR1,TIM2 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000000+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM2_CCMR1,TIM2 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM2_CCMR1,TIM2 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM2_CCMR2,TIM2 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000000+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM2_CCMR2,TIM2 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000000+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM2_CCMR2,TIM2 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM2_CCMR2,TIM2 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40000000+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000000+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000000+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000000+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000000+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000000+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000000+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000000+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000000+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000000+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000000+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000000+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000000+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM2_CCER,TIM2 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40000000))&0x800)==0x800) group.long 0x24++0x03 line.long 0x00 "TIM2_CNT,TIM2 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" else group.long 0x24++0x03 line.long 0x00 "TIM2_CNT,TIM2 counter" bitfld.long 0x00 31. " CNT[31] ,Most significant bit of counter value" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" endif group.word 0x28++0x01 line.word 0x00 "TIM2_PSC,TIM2 prescaler" group.long 0x2C++0x03 line.long 0x00 "TIM2_ARR,TIM2 auto-reload register" hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value" hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value" group.long 0x34++0x0f line.long 0x00 "TIM2_CCR1,TIM2 capture/compare register 1" hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM2_CCR2,TIM2 capture/compare register 2" hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM2_CCR3,TIM2 capture/compare register 3" hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM2_CCR4,TIM2 capture/compare register 4" hexmask.long.word 0x0c 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" group.word 0x48++0x01 line.word 0x00 "TIM2_DCR,TIM2 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,TIM2_DCR,TIM2_DMAR,TIM2_OR1,TIM2_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM2_DMAR,TIM2 DMA address for full transfer" sif (cpuis("STM32L431*")) group.long 0x50++0x03 line.long 0x00 "TIM2_OR1,TIM2 option register 1" bitfld.long 0x00 2.--3. " TI4_RMP ,Input Capture 4 remap" "I/O,COMP1_OUT,COMP2_OUT,COMP1_OUT||COMP2_OUT" bitfld.long 0x00 1. " ETR1_RMP ,External trigger remap" "I/O,LSE" bitfld.long 0x00 0. " ITR1_RMP ,Internal trigger 1 remap" "Not triggered,?..." elif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) group.long 0x50++0x03 line.long 0x00 "TIM2_OR1,TIM2 option register 1" bitfld.long 0x00 2.--3. " TI4_RMP ,Input Capture 4 remap" "I/O,COMP1_OUT,COMP2_OUT,COMP1_OUT||COMP2_OUT" bitfld.long 0x00 1. " ETR1_RMP ,External trigger remap" "I/O,LSE" bitfld.long 0x00 0. " ITR1_RMP ,Internal trigger 1 remap" "Not triggered,Triggered" else group.long 0x50++0x03 line.long 0x00 "TIM2_OR1,TIM2 option register 1" bitfld.long 0x00 2.--3. " TI4_RMP ,Input Capture 4 remap" "I/O,COMP1_OUT,COMP2_OUT,COMP1_OUT||COMP2_OUT" bitfld.long 0x00 1. " ETR1_RMP ,External trigger remap" "I/O,LSE" bitfld.long 0x00 0. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGO,OTG_FS SOF" endif sif (cpuis("STM32L431*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*") group.long 0x60++0x03 line.long 0x00 "TIM2_OR2,TIM2 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "TIM2_ETR,COMP1-ETR,COMP2-ETR,?..." else group.long 0x60++0x03 line.long 0x00 "TIM2_OR2,TIM2 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "ETR legacy,COMP1-ETR,COMP2-ETR,?..." endif width 0x0B tree.end sif (cpuis("STM32L462*"))||(cpuis("STM32L452*")) tree "TIM3" base ad:0x40000400 width 12. if ((((per.l(ad:0x40000400))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40000400+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "TIM3_CR2,TIM3 control register 2" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "When CC3 occurs,When update occurs" group.long 0x08++0x03 line.long 0x00 "TIM3_SMCR,TIM3 slave mode control register" bitfld.long 0x00 15. " ETP ,External trigger polarity" "Rising edge,Falling edge" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,Div2,Div4,Div8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif sif (cpuis("STM32L4?5*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" textline " " elif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||(cpuis("STM32L451*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." group.word 0x0C++0x01 line.word 0x00 "TIM3_DIER,TIM3 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM3_SR,TIM3 status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM3_EGR,TIM3 event generation register" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40000400+0x18))&0x303)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000400+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000400+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000400+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000400+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40000400+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif group.long 0x24++0x03 line.long 0x00 "TIM3_CNT,TIM3 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" group.word 0x28++0x01 line.word 0x00 "TIM3_PSC,TIM3 prescaler" sif (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x2C++0x03 line.long 0x00 "TIM3_ARR,TIM3 auto-reload register" hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value" hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value" else group.long 0x2C++0x03 line.long 0x00 "TIM3_ARR,TIM3 auto-reload register" hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value" endif sif (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x34++0x0f line.long 0x00 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.long.word 0x0c 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" else group.long 0x34++0x0f line.long 0x00 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" endif group.word 0x48++0x01 line.word 0x00 "TIM3_DCR,TIM3 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,TIM2_DCR,TIM2_DMAR,TIM2_OR1,TIM2_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM3_DMAR,TIM3 DMA address for full transfer" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) group.long 0x50++0x03 line.long 0x00 "TIM3_OR1,TIM3 option register 1" bitfld.long 0x00 0.--1. " TI1_RMP ,Input Capture 1 remap" "I/O,COMP1_OUT,COMP2_OUT,COMP1_OUT||COMP2_OUT" group.long 0x60++0x03 line.long 0x00 "TIM3_OR2,TIM3 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "ETR legacy,COMP1-ETR,?..." endif width 0x0B tree.end elif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) tree "TIM3" base ad:0x40000400 width 12. if ((((per.l(ad:0x40000400))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40000400+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "TIM3_CR2,TIM3 control register 2" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "When CC3 occurs,When update occurs" group.long 0x08++0x03 line.long 0x00 "TIM3_SMCR,TIM3 slave mode control register" bitfld.long 0x00 15. " ETP ,External trigger polarity" "Rising edge,Falling edge" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,Div2,Div4,Div8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif sif (cpuis("STM32L4?5*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" textline " " elif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||(cpuis("STM32L451*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." group.word 0x0C++0x01 line.word 0x00 "TIM3_DIER,TIM3 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM3_SR,TIM3 status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM3_EGR,TIM3 event generation register" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40000400+0x18))&0x303)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000400+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000400+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM3_CCMR1,TIM3 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000400+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000400+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM3_CCMR2,TIM3 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40000400+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000400+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000400+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000400+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000400+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000400+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000400+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000400+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM3_CCER,TIM3 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif group.long 0x24++0x03 line.long 0x00 "TIM3_CNT,TIM3 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" group.word 0x28++0x01 line.word 0x00 "TIM3_PSC,TIM3 prescaler" sif (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x2C++0x03 line.long 0x00 "TIM3_ARR,TIM3 auto-reload register" hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value" hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value" else group.long 0x2C++0x03 line.long 0x00 "TIM3_ARR,TIM3 auto-reload register" hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value" endif sif (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) group.long 0x34++0x0f line.long 0x00 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.long.word 0x0c 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" else group.long 0x34++0x0f line.long 0x00 "TIM3_CCR1,TIM3 capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM3_CCR2,TIM3 capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM3_CCR3,TIM3 capture/compare register 3" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM3_CCR4,TIM3 capture/compare register 4" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" endif group.word 0x48++0x01 line.word 0x00 "TIM3_DCR,TIM3 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,TIM2_DCR,TIM2_DMAR,TIM2_OR1,TIM2_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM3_DMAR,TIM3 DMA address for full transfer" sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) group.long 0x50++0x03 line.long 0x00 "TIM3_OR1,TIM3 option register 1" bitfld.long 0x00 0.--1. " TI1_RMP ,Input Capture 1 remap" "I/O,COMP1_OUT,COMP2_OUT,COMP1_OUT||COMP2_OUT" group.long 0x60++0x03 line.long 0x00 "TIM3_OR2,TIM3 option register 2" bitfld.long 0x00 14.--16. " ETRSEL ,ETR source selection" "ETR legacy,COMP1-ETR,?..." endif width 0x0B tree.end tree "TIM4" base ad:0x40000800 width 12. if ((((per.l(ad:0x40000800))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40000800+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "TIM4_CR2,TIM4 control register 2" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "When CC4 occurs,When update occurs" group.long 0x08++0x03 line.long 0x00 "TIM4_SMCR,TIM4 slave mode control register" bitfld.long 0x00 15. " ETP ,External trigger polarity" "Rising edge,Falling edge" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,Div2,Div4,Div8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif sif (cpuis("STM32L4?5*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" textline " " elif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||(cpuis("STM32L451*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." group.word 0x0C++0x01 line.word 0x00 "TIM4_DIER,TIM4 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM4_SR,TIM4 status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM4_EGR,TIM4 event generation register" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40000800+0x18))&0x303)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM4_CCMR1,TIM4 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000800+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM4_CCMR1,TIM4 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000800+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM4_CCMR1,TIM4 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM4_CCMR1,TIM4 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM4_CCMR2,TIM4 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000800+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM4_CCMR2,TIM4 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000800+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM4_CCMR2,TIM4 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM4_CCMR2,TIM4 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40000800+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000800+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000800+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000800+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000800+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000800+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000800+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000800+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000800+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000800+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000800+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000800+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000800+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM4_CCER,TIM4 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif group.long 0x24++0x03 line.long 0x00 "TIM4_CNT,TIM4 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" group.word 0x28++0x01 line.word 0x00 "TIM4_PSC,TIM4 prescaler" group.long 0x2C++0x03 line.long 0x00 "TIM4_ARR,TIM4 auto-reload register" hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value" group.long 0x34++0x0f line.long 0x00 "TIM4_CCR1,TIM4 capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM4_CCR2,TIM4 capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM4_CCR3,TIM4 capture/compare register 3" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM4_CCR4,TIM4 capture/compare register 4" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" group.word 0x48++0x01 line.word 0x00 "TIM4_DCR,TIM4 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,TIM2_DCR,TIM2_DMAR,TIM2_OR1,TIM2_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM4_DMAR,TIM4 DMA address for full transfer" width 0x0B tree.end tree "TIM5" base ad:0x40000C00 width 12. if ((((per.l(ad:0x40000c00))&0x60)==(0x20||0x40||0x60))||(((per.l(ad:0x40000c00+0x08))&0x10007)==(0x00001||0x00002||0x00003))) group.word 0x00++0x01 line.word 0x00 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned,Center-aligned1,Center-aligned2,Center-aligned3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "TIM5_CR2,TIM5 control register 2" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1 connected,CH1/CH2/CH3 connected(XOR)" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),Compare(OC3REF),Compare(OC4REF)" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "When CC5 occurs,When update occurs" group.long 0x08++0x03 line.long 0x00 "TIM5_SMCR,TIM5 slave mode control register" bitfld.long 0x00 15. " ETP ,External trigger polarity" "Rising edge,Falling edge" bitfld.long 0x00 14. " ECE ,External clock mode 2 enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "OFF,Div2,Div4,Div8" bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" textline " " sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L451*")) bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " else bitfld.long 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif sif (cpuis("STM32L4?5*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "Not connected,ETRF" textline " " elif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||(cpuis("STM32L451*")) bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder1,Encoder2,Encoder3,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." group.word 0x0C++0x01 line.word 0x00 "TIM5_DIER,TIM5 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM5_SR,TIM5 status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "No overcapture,Counter captured" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "No overcapture,Counter captured" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger event,Trigger interrupt" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM5_EGR,TIM5 event generation register" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation" "No action,CH4 capture/compare" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation" "No action,CH3 capture/compare" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40000c00+0x18))&0x303)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM5_CCMR1,TIM5 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000c00+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x0)) group.long 0x18++0x03 line.long 0x00 "TIM5_CCMR1,TIM5 capture/compare mode register 1" bitfld.long 0x00 15. " OC2CE ,Output Compare 2 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif ((((per.l(ad:0x40000c00+0x18))&0x3)!=0x0)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x0)) group.long 0x18++0x03 line.long 0x00 "TIM5_CCMR1,TIM5 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM5_CCMR1,TIM5 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 7. " OC1CE ,Output Compare 1 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.long 0x1C++0x03 line.long 0x00 "TIM5_CCMR2,TIM5 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000c00+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM5_CCMR2,TIM5 capture/compare mode register 2" bitfld.long 0x00 15. " OC4CE ,Output Compare 4 clear enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 11. " OC4PE ,Output Compare 4 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC4FE ,Output Compare 4 fast enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" elif ((((per.l(ad:0x40000c00+0x1C))&0x3)!=0x0)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x0)) group.long 0x1C++0x03 line.long 0x00 "TIM5_CCMR2,TIM5 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" else group.long 0x1C++0x03 line.long 0x00 "TIM5_CCMR2,TIM5 capture/compare mode register 2" bitfld.long 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input(IC4-TI4),Input(IC4-TI3),Input(IC4-TRC)" bitfld.long 0x00 7. " OC3CE ,Output Compare 3 clear enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 mode" "Frozen,Active on match,Inactive on match,Toggle,Forced inactive,Forced active,PWM 1,PWM 2,Retrigerrable OPM 1,Retrigerrable OPM 2,,,Combined PWM 1,Combined PWM 2,Asymmetric PWM 1,Asymmetric PWM 2" bitfld.long 0x00 3. " OC3PE ,Output Compare 3 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC3FE ,Output Compare 3 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input(IC3-TI3),Input(IC3-TI4),Input(IC3-TRC)" endif if (((per.l(ad:0x40000c00+0x08))&0x10007)==(0x00001||0x00002||0x00003)) if (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000c00+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000c00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000c00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,?..." bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000c00+0x18))&0x300)==(0x000))&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40000c00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40000c00+0x18))&0x300)!=(0x000))&&(((per.l(ad:0x40000c00+0x1C))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output polarity" "Active high,Active low" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "Active high,Active low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Off,On" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output polarity" "Active high,Active low" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Off,On" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x303)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40000c00+0x18))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)==0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40000c00+0x18))&0x03)==0x00)&&(((per.l(ad:0x40000c00+0x18))&0x300)!=0x000)&&(((per.l(ad:0x40000c00+0x1C))&0x03)!=0x00)&&(((per.l(ad:0x40000c00+0x1C))&0x300)!=0x000) group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM5_CCER,TIM5 capture/compare enable register" bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40000c00))&0x800)==0x800) group.long 0x24++0x03 line.long 0x00 "TIM5_CNT,TIM5 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" else group.long 0x24++0x03 line.long 0x00 "TIM5_CNT,TIM5 counter" bitfld.long 0x00 31. " CNT[31] ,Most significant bit of counter value" "0,1" hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" endif group.word 0x28++0x01 line.word 0x00 "TIM5_PSC,TIM5 prescaler" group.long 0x2C++0x03 line.long 0x00 "TIM5_ARR,TIM5 auto-reload register" hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value" hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value" group.long 0x34++0x0f line.long 0x00 "TIM5_CCR1,TIM5 capture/compare register 1" hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM5_CCR2,TIM5 capture/compare register 2" hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM5_CCR3,TIM5 capture/compare register 3" hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0c "TIM5_CCR4,TIM5 capture/compare register 4" hexmask.long.word 0x0c 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value" hexmask.long.word 0x0c 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" group.word 0x48++0x01 line.word 0x00 "TIM5_DCR,TIM5 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,TIM2_DCR,TIM2_DMAR,TIM2_OR1,TIM2_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM5_DMAR,TIM5 DMA address for full transfer" width 0x0B tree.end endif tree.end tree "TIM15/16/17 (General-purpose timers)" tree "TIM15" base ad:0x40014000 width 13. group.word 0x00++0x01 line.word 0x00 "TIM15_CR1,TIM15 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" if (((per.l(ad:0x40014000+0x44))&0x300)==0x00) group.word 0x04++0x01 line.word 0x00 "TIM15_CR2,TIM15 control register 2" bitfld.word 0x00 10. " OIS2 ,Output idle state 2(OC2 output)" "0,1" bitfld.word 0x00 9. " OIS1N ,Output idle state 1(OC1N output)" "0,1" bitfld.word 0x00 8. " OIS1 ,Output idle state 1(OC1 output)" "0,1" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1-TI1,(CH1 xor CH2)-TI1" textline " " bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),?..." bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "WhenCC15 occurs,When update occurs" bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/TRGI(Rising)" bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" else group.word 0x04++0x01 line.word 0x00 "TIM15_CR2,TIM15 control register 2" rbitfld.word 0x00 10. " OIS2 ,Output idle state 2(OC2 output)" "0,1" rbitfld.word 0x00 9. " OIS1N ,Output idle state 1(OC1N output)" "0,1" rbitfld.word 0x00 8. " OIS1 ,Output idle state 1(OC1 output)" "0,1" bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1-TI1,(CH1 xor CH2)-TI1" textline " " bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,Compare(OC1REF),Compare(OC2REF),?..." bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "WhenCC15 occurs,When update occurs" bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/TRGI(Rising)" bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" endif group.long 0x08++0x03 line.long 0x00 "TIM15_SMCR,TIM15 slave mode control register" bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,TRGI delayed" bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External clock,Reset+Trigger,?..." group.word 0x0C++0x01 line.word 0x00 "TIM15_DIER,TIM15 DMA/interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000) group.word 0x10++0x01 line.word 0x00 "TIM15_SR,TIM15 status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No match,Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No match,Matched" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" elif (((per.w((ad:0x40014000+0x18)))&0x003)==0x000) group.word 0x10++0x01 line.word 0x00 "TIM15_SR,TIM15 status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No input,Captured" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No match,Matched" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000) group.word 0x10++0x01 line.word 0x00 "TIM15_SR,TIM15 status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No match,Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No input,Captured" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" else group.word 0x10++0x01 line.word 0x00 "TIM15_SR,TIM15 status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag" "No input,Captured" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No input,Captured" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" endif group.word 0x14++0x01 line.word 0x00 "TIM15_EGR,TIM15 event generation register" bitfld.word 0x00 7. " BG ,Break generation" "No action,Break" bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Triggered" bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update possible" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation" "No action,CH2 capture/compare" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Updated" if (((per.l(ad:0x40014000+0x18))&0x3)==0x0&&((per.l(ad:0x40014000+0x18))&0x300)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM15_CCMR1,TIM15 capture/compare mode register 1" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Channel 2 active,Channel 2 inactive,Toggle,Force inactive level,Force active level,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..." bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" textline " " bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Channel 1 active,Channel 1 inactive,Toggle,Force inactive level,Force active level,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..." bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif (((per.l(ad:0x40014000+0x18))&0x3)!=0x0&&((per.l(ad:0x40014000))&0x300)==0x0) group.long 0x18++0x03 line.long 0x00 "TIM15_CCMR1,TIM15 capture/compare mode register 1" bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 mode" "Frozen,Channel 2 active,Channel 2 inactive,Toggle,Force inactive level,Force active level,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..." bitfld.long 0x00 11. " OC2PE ,Output Compare 2 preload enable" "Disabled,Enabled" bitfld.long 0x00 10. " OC2FE ,Output Compare 2 fast enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" textline " " bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" elif (((per.l(ad:0x40014000+0x18))&0x3)!=0x0&&((per.l(ad:0x40014000))&0x300)!=0x0) group.long 0x18++0x03 line.long 0x00 "TIM15_CCMR1,TIM15 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM15_CCMR1,TIM15 capture/compare mode register 1" bitfld.long 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input(IC2-TI2),Input(IC2-TI1),Input(IC2-TRC)" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 mode" "Frozen,Channel 2 active,Channel 2 inactive,Toggle,Force inactive level,Force active level,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..." textline " " bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40014000+0x18))&0x303)==0x000) group.word 0x20++0x01 line.word 0x00 "TIM15_CCER,TIM15 capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" textline " " bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" elif (((per.l(ad:0x40014000+0x18))&0x03)!=(0x00))&&(((per.l(ad:0x40014000+0x18))&0x300)==(0x000)) group.word 0x20++0x01 line.word 0x00 "TIM15_CCER,TIM15 capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edge" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.l(ad:0x40014000+0x18))&0x03)==(0x00))&&(((per.l(ad:0x40014000+0x18))&0x300)!=(0x000)) group.word 0x20++0x01 line.word 0x00 "TIM15_CCER,TIM15 capture/compare enable register" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edge" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM15_CCER,TIM15 capture/compare enable register" bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edge" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edge" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif group.long 0x24++0x03 line.long 0x00 "TIM15_CNT,TIM15 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "No update,Update interrupt" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part counter value" group.word 0x28++0x01 line.word 0x00 "TIM15_PSC,TIM15 prescaler" group.word 0x2C++0x03 line.word 0x00 "TIM15_ARR,TIM15 auto-reload register" group.word 0x30++0x01 line.word 0x00 "TIM15_RCR,TIM15 repetition counter register" hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value" group.word 0x34++0x01 line.word 0x00 "TIM15_CCR1,TIM15 capture/compare register 1" group.word 0x38++0x01 line.word 0x00 "TIM15_CCR2,TIM15 capture/compare register 2" if (((per.l(ad:0x40014000+0x44))&0x300)==0x200) group.long 0x44++0x03 line.long 0x00 "TIM15_BDTR,TIM15 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&(!cpuis("STM32L475*"))&&(!cpuis("STM32L471*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" rbitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" elif (((per.l(ad:0x40014000+0x44))&0x300)==0x100) group.long 0x44++0x03 line.long 0x00 "TIM15_BDTR,TIM15 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&(!cpuis("STM32L475*"))&&(!cpuis("STM32L471*"))&&(!cpuis("STM32L451*")) rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" else group.long 0x44++0x03 line.long 0x00 "TIM15_BDTR,TIM15 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&(!cpuis("STM32L475*"))&&(!cpuis("STM32L471*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" endif group.word 0x48++0x01 line.word 0x00 "TIM15_DCR,TIM15 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM15_CR1,TIM15_CR2,TIM15_SMCR,TIM15_DIER,TIM15_SR,TIM15_EGR,TIM15_CCMR1,TIM15_CCER,TIM15_CNT,TIM15_PSC,TIM15_ARR,TIM15_RCR,TIM15_CCR1,TIM15_CCR2,TIM15_BDTR,TIM15_DCR,TIM15_DMAR,TIM15_OR1,TIM15_OR2,?..." group.word 0x4c++0x01 line.word 0x00 "TIM15_DMAR,TIM15 DMA address for full transfer" group.long 0x50++0x03 line.long 0x00 "TIM15_OR1,TIM15 option register 1" sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L451*")) bitfld.long 0x00 1.--2. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2(IC1/IC2)-TIM15(IC1/IC2),?..." textline " " else bitfld.long 0x00 1.--2. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2(IC1/IC2)-TIM15(IC1/IC2),TIM3(IC1/IC2)-TIM15(IC1/IC2),TIM4(IC1/IC2)-TIM15(IC1/IC2)" textline " " endif bitfld.long 0x00 0. " TI1_RMP ,Input capture 1 remap" "I/O,LSE" if (((per.l(ad:0x40014000+0x44))&0x300)==0x100) rgroup.long 0x60++0x03 line.long 0x00 "TIM15_OR2,TIM15 option register 2" bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 8. " BKDFBK0E ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN enable" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "TIM15_OR2,TIM15 option register 2" bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 8. " BKDFBK0E ,BRK DFSDM_BREAK[0] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN enable" "Disabled,Enabled" endif width 0x0B tree.end tree "TIM16" base ad:0x40014400 width 13. group.word 0x00++0x01 line.word 0x00 "TIM16_CR1,TIM16 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" if (((per.l(ad:0x40014400+0x44))&0x300)!=0x0) group.word 0x04++0x01 line.word 0x00 "TIM16_CR2,TIM16 control register 2" rbitfld.word 0x00 9. " OIS1N ,Output idle state 1(OC1N output)" "0,1" rbitfld.word 0x00 8. " OIS1 ,Output idle state 1(OC1 output)" "0,1" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "WhenCC16 occurs,When update occurs" bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/TRGI(Rising)" textline " " bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" else group.word 0x04++0x01 line.word 0x00 "TIM16_CR2,TIM16 control register 2" bitfld.word 0x00 9. " OIS1N ,Output idle state 1(OC1N output)" "0,1" bitfld.word 0x00 8. " OIS1 ,Output idle state 1(OC1 output)" "0,1" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "WhenCC16 occurs,When update occurs" bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/TRGI(Rising)" textline " " bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" endif group.word 0x0C++0x01 line.word 0x00 "TIM16_DIER,TIM16 DMA/interrupt enable register" sif (!cpuis("STM32L43*"))&&(!cpuis("STM32L44*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" endif textline " " bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00) group.word 0x10++0x01 line.word 0x00 "TIM16_SR,TIM16 status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No match,Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" elif (((per.w((ad:0x40014400+0x18)))&0x03)!=0x00) group.word 0x10++0x01 line.word 0x00 "TIM16_SR,TIM16 status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No input,Captured" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" endif wgroup.word 0x14++0x01 line.word 0x00 "TIM16_EGR,TIM16 event generation register" bitfld.word 0x00 7. " BG ,Break generation" "No action,Break" textline " " sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" textline " " endif bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40014400+0x18))&0x03)==0x00) group.long 0x18++0x03 line.long 0x00 "TIM16_CCMR1,TIM16 capture/compare mode register 1" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 2 mode" "Frozen,Channel 1 active,Channel 1 inactive,Toggle,Force inactive level,Force active level,PWM mode 1,PWM mode 2,?..." bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM16_CCMR1,TIM16 capture/compare mode register 1" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40014400+0x18))&0x03)==0x00) group.word 0x20++0x01 line.word 0x00 "TIM16_CCER,TIM16 capture/compare enable register" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM16_CCER,TIM16 capture/compare enable register" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edge" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif if (((per.l(ad:0x40014400))&0x800)==0x000) group.long 0x24++0x03 line.long 0x00 "TIM16_CNT,TIM16 counter" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" else group.long 0x24++0x03 line.long 0x00 "TIM16_CNT,TIM16 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF copy" "No update,Update interrupt" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" endif group.word 0x28++0x01 line.word 0x00 "TIM16_PSC,TIM16 prescaler" group.word 0x2C++0x03 line.word 0x00 "TIM16_ARR,TIM16 auto-reload register" group.word 0x30++0x01 line.word 0x00 "TIM16_RCR,TIM16 repetition counter register" hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value" group.word 0x34++0x01 line.word 0x00 "TIM16_CCR1,TIM16 capture/compare register 1" if (((per.l(ad:0x40014400+0x44))&0x300)==0x200) group.long 0x44++0x03 line.long 0x00 "TIM16_BDTR,TIM16 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" rbitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" elif (((per.l(ad:0x40014400+0x44))&0x300)==0x100) group.long 0x44++0x03 line.long 0x00 "TIM16_BDTR,TIM16 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" else group.long 0x44++0x03 line.long 0x00 "TIM16_BDTR,TIM16 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" endif group.word 0x48++0x01 line.word 0x00 "TIM16_DCR,TIM16 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CCMR1,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,TIM16_OR1,TIM16_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM16_DMAR,TIM16 DMA address for full transfer" sif (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L451*")) group.long 0x50++0x03 line.long 0x00 "TIM16_OR1,TIM16 option register 1" bitfld.long 0x00 0.--2. " TI1_RMP ,Input capture 1 remap" "I/O,LSI,LSE,RTC wakeup int,MSI,HSE/32,MCO,?..." else group.long 0x50++0x03 line.long 0x00 "TIM16_OR1,TIM16 option register 1" bitfld.long 0x00 0.--1. " TI1_RMP ,Input capture 1 remap" "I/O,LSI,LSE,RTC wakeup int" endif if (((per.l(ad:0x40014400+0x44))&0x300)==0x100) rgroup.long 0x60++0x03 line.long 0x00 "TIM16_OR2,TIM16 option register 2" bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 8. " BKDFBK1E ,BRK DFSDM_BREAK[1] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN enable" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "TIM16_OR2,TIM16 option register 2" bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" textline " " sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) bitfld.long 0x00 8. " BKDFBK1E ,BRK DFSDM_BREAK[1] enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN enable" "Disabled,Enabled" endif width 0x0B tree.end sif (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) tree "TIM17" base ad:0x40014800 width 13. group.word 0x00++0x01 line.word 0x00 "TIM17_CR1,TIM17 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" bitfld.word 0x00 1. " UDIS ,Update disable" "UEV enabled,UEV disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" if (((per.l(ad:0x40018418+0x44))&0x300)!=0x0) group.word 0x04++0x01 line.word 0x00 "TIM17_CR2,TIM17 control register 2" rbitfld.word 0x00 9. " OIS1N ,Output idle state 1(OC1N output)" "0,1" rbitfld.word 0x00 8. " OIS1 ,Output idle state 1(OC1 output)" "0,1" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "WhenCC17 occurs,When update occurs" bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/TRGI(Rising)" textline " " bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" else group.word 0x04++0x01 line.word 0x00 "TIM17_CR2,TIM17 control register 2" bitfld.word 0x00 9. " OIS1N ,Output idle state 1(OC1N output)" "0,1" bitfld.word 0x00 8. " OIS1 ,Output idle state 1(OC1 output)" "0,1" bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "WhenCC17 occurs,When update occurs" bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/TRGI(Rising)" textline " " bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded" endif group.word 0x0C++0x01 line.word 0x00 "TIM17_DIER,TIM17 DMA/interrupt enable register" sif (!cpuis("STM32L43*"))&&(!cpuis("STM32L44*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" endif textline " " bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" textline " " sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" if (((per.w((ad:0x40018418+0x18)))&0x03)==0x00) group.word 0x10++0x01 line.word 0x00 "TIM17_SR,TIM17 status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No match,Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" elif (((per.w((ad:0x40018418+0x18)))&0x03)!=0x00) group.word 0x10++0x01 line.word 0x00 "TIM17_SR,TIM17 status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag" "No input,Captured" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt flag" "Not occurred,Occurred" endif wgroup.word 0x14++0x01 line.word 0x00 "TIM17_EGR,TIM17 event generation register" bitfld.word 0x00 7. " BG ,Break generation" "No action,Break" textline " " sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Trigger" textline " " endif bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation" "No action,CH1 capture/compare" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" if (((per.l(ad:0x40018418+0x18))&0x03)==0x00) group.long 0x18++0x03 line.long 0x00 "TIM17_CCMR1,TIM17 capture/compare mode register 1" bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 2 mode" "Frozen,Channel 1 active,Channel 1 inactive,Toggle,Force inactive level,Force active level,PWM mode 1,PWM mode 2,?..." bitfld.long 0x00 3. " OC1PE ,Output Compare 1 preload enable" "Disabled,Enabled" bitfld.long 0x00 2. " OC1FE ,Output Compare 1 fast enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" else group.long 0x18++0x03 line.long 0x00 "TIM17_CCMR1,TIM17 capture/compare mode register 1" bitfld.long 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" bitfld.long 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input(IC1-TI1),Input(IC1-TI2),Input(IC1-TRC)" endif if (((per.l(ad:0x40018418+0x18))&0x03)==0x00) group.word 0x20++0x01 line.word 0x00 "TIM17_CCER,TIM17 capture/compare enable register" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On" else group.word 0x20++0x01 line.word 0x00 "TIM17_CCER,TIM17 capture/compare enable register" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On" bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/both edge" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif if (((per.l(ad:0x40018418))&0x800)==0x000) group.long 0x24++0x03 line.long 0x00 "TIM17_CNT,TIM17 counter" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" else group.long 0x24++0x03 line.long 0x00 "TIM17_CNT,TIM17 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF copy" "No update,Update interrupt" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" endif group.word 0x28++0x01 line.word 0x00 "TIM17_PSC,TIM17 prescaler" group.word 0x2C++0x03 line.word 0x00 "TIM17_ARR,TIM17 auto-reload register" group.word 0x30++0x01 line.word 0x00 "TIM17_RCR,TIM17 repetition counter register" hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value" group.word 0x34++0x01 line.word 0x00 "TIM17_CCR1,TIM17 capture/compare register 1" if (((per.l(ad:0x40018418+0x44))&0x300)==0x200) group.long 0x44++0x03 line.long 0x00 "TIM17_BDTR,TIM17 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" rbitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" elif (((per.l(ad:0x40018418+0x44))&0x300)==0x100) group.long 0x44++0x03 line.long 0x00 "TIM17_BDTR,TIM17 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" else group.long 0x44++0x03 line.long 0x00 "TIM17_BDTR,TIM17 break and dead-time register" sif (!cpuis("STM32L431*"))&&(!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&!cpuis("STM32L4?6*")&&!cpuis("STM32L475")&&!cpuis("STM32L471*")&&(!cpuis("STM32L451*")) bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT(N=2),fCK_INT(N=4),fCK_INT(N=8),fDTS/2(N=6),fDTS/2(N=8),fDTS/4(N=6),fDTS/4(N=8),fDTS/8(N=6),fDTS/8(N=8),fDTS/16(N=5),fDTS/16(N=6),fDTS/16(N=8),fDTS/32(N=5),fDTS/32(N=6),fDTS/32(N=8)" textline " " endif bitfld.long 0x00 15. " MOE ,Main output enable" "Disabled,Enabled" bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled" bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high" bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled" bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode" "OC/OCN disabled,OC/OCN first forced" bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3" hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup" endif group.word 0x48++0x01 line.word 0x00 "TIM17_DCR,TIM17 DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CCMR1,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,TIM17_OR1,TIM17_OR2,?..." group.word 0x4C++0x01 line.word 0x00 "TIM17_DMAR,TIM17 DMA address for full transfer" group.long 0x50++0x03 line.long 0x00 "TIM17_OR1,TIM17 option register 1" bitfld.long 0x00 0.--1. " TI1_RMP ,Input capture 1 remap" "I/O,MSI,HSE/32,MCO" if (((per.l(ad:0x40018418+0x44))&0x300)==0x100) rgroup.long 0x60++0x03 line.long 0x00 "TIM17_OR2,TIM17 option register 2" bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" bitfld.long 0x00 8. " BKDFBK2E ,BRK DFSDM_BREAK[2] enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN enable" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "TIM17_OR2,TIM17 option register 2" bitfld.long 0x00 11. " BKCMP2P ,BRK COMP2 input polarity" "Active low,Active high" bitfld.long 0x00 10. " BKCMP1P ,BRK COMP1 input polarity" "Active low,Active high" bitfld.long 0x00 9. " BKINP ,BRK BKIN input polarity" "Active low,Active high" bitfld.long 0x00 8. " BKDFBK2E ,BRK DFSDM_BREAK[2] enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BKCMP2E ,BRK COMP2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " BKCMP1E ,BRK COMP1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " BKINE ,BRK BKIN enable" "Disabled,Enabled" endif width 0x0B tree.end endif tree.end tree "TIM6/7 (Basic timers)" tree "TIM6" base ad:0x40001000 width 13. group.word 0x00++0x01 line.word 0x00 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "Enabled,Disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x01 line.word 0x00 "TIM6_CR2,TIM6 control register 2" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..." group.word 0x0c++0x01 line.word 0x00 "TIM6_DIER,TIM6 DMA/interrupt enable register" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM6_SR,TIM6 status register" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM6_EGR,TIM6 event generation register" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" group.long 0x24++0x03 line.long 0x00 "TIM6_CNT,TIM6 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 0.--15. 1. " CNT ,Least significant part counter value" group.word 0x28++0x01 line.word 0x00 "TIM6_PSC,TIM6 prescaler" group.word 0x2C++0x03 line.word 0x00 "TIM6_ARR,TIM6 auto-reload register" width 0x0B tree.end tree "TIM7" base ad:0x40001400 width 13. group.word 0x00++0x01 line.word 0x00 "TIM7_CR1,TIM7 control register 1" bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Disabled,Enabled" bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Count flow/UG/slv mode control,Counter over/underflow" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "Enabled,Disabled" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x01 line.word 0x00 "TIM7_CR2,TIM7 control register 2" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..." group.word 0x0c++0x01 line.word 0x00 "TIM7_DIER,TIM7 DMA/interrupt enable register" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM7_SR,TIM7 status register" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update interrupt" wgroup.word 0x14++0x01 line.word 0x00 "TIM7_EGR,TIM7 event generation register" bitfld.word 0x00 0. " UG ,Update generation" "No action,Update" group.long 0x24++0x03 line.long 0x00 "TIM7_CNT,TIM7 counter" rbitfld.long 0x00 31. " UIFCPY ,UIF Copy" "0,1" hexmask.long.word 0x00 0.--15. 1. " CNT ,Least significant part counter value" group.word 0x28++0x01 line.word 0x00 "TIM7_PSC,TIM7 prescaler" group.word 0x2C++0x03 line.word 0x00 "TIM7_ARR,TIM7 auto-reload register" width 0x0B tree.end tree.end tree "LPTIM1/2 (Low power timers)" tree "LPTIM1" base ad:0x40007C00 width 13. rgroup.long 0x00++0x03 line.long 0x00 "LPTIM1_ISR,LPTIM Interrupt and Status Register" bitfld.long 0x00 6. " DOWN ,Counter direction change up to down" "No change,DOWN direction" bitfld.long 0x00 5. " UP ,Counter direction change down to up" "No change,UP direction" bitfld.long 0x00 4. " ARROK ,Autoreload register update OK" "Writing,Write complete" bitfld.long 0x00 3. " CMPOK ,Compare register update OK" "Writing,Write complete" textline " " bitfld.long 0x00 2. " EXTTRIG ,External trigger edge event" "No valid edge event,Valid edge event" bitfld.long 0x00 1. " ARRM ,Autoreload match" "CNT 2clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock Polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..." textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" else rgroup.long 0x0C++0x03 line.long 0x00 "LPTIM1_CFGR,LPTIM Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After each write access,At the end of period" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM/One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Sw trigger,Rising edge,Falling edge,Both edges" bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "ext_trig0,ext_trig1,ext_trig2,ext_trig3,ext_trig4,ext_trig5,ext_trig6,ext_trig7" textline " " bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock Polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..." textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" endif else group.long 0x0C++0x03 line.long 0x00 "LPTIM1_CFGR,LPTIM Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After each write access,At the end of period" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM/One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Sw trigger,Rising edge,Falling edge,Both edges" bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "ext_trig0,ext_trig1,ext_trig2,ext_trig3,ext_trig4,ext_trig5,ext_trig6,ext_trig7" textline " " bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "All valid,>2clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock Polarity" "Rising edge,Falling edge,Both edges," textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" endif if (((per.l(ad:0x40007C10))&0x1)==0x1) group.long 0x10++0x03 line.long 0x00 "LPTIM1_CR,LPTIM Control Register" bitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "No effect,Start" bitfld.long 0x00 1. " SNGSTRT ,Timer start in single mode" "No effect,Start" bitfld.long 0x00 0. " ENABLE ,LPTIM Enable" "Disabled,Enabled" group.long 0x14++0x07 line.long 0x00 "LPTIM1_CMP,LPTIM Compare Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Compare value" line.long 0x04 "LPTIM1_ARR,LPTIM Autoreload Register" hexmask.long.word 0x04 0.--15. 1. " ARR ,Auto reload value" else group.long 0x10++0x03 line.long 0x00 "LPTIM1_CR,LPTIM Control Register" rbitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "No effect,Start" rbitfld.long 0x00 1. " SNGSTRT ,Timer start in single mode" "No effect,Start" bitfld.long 0x00 0. " ENABLE ,LPTIM Enable" "Disabled,Enabled" rgroup.long 0x14++0x07 line.long 0x00 "LPTIM1_CMP,LPTIM Compare Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Compare value" line.long 0x04 "LPTIM1_ARR,LPTIM Autoreload Register" hexmask.long.word 0x04 0.--15. 1. " ARR ,Auto reload value" endif rgroup.long 0x1C++0x03 line.long 0x00 "LPTIM1_CNT,LPTIM Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") group.long 0x20++0x03 line.long 0x00 "LPTIM1_OR,LPTIM Option Register" bitfld.long 0x00 1. " OR_1 ,Option register bit 1" "I2 connected to I/O,I2 connected to COMP2_OUT" bitfld.long 0x00 0. " OR_0 ,Option register bit 0" "I1 connected to I/O,I1 connected to COMP1_OUT" endif width 0x0B tree.end tree "LPTIM2" base ad:0x40009400 width 13. rgroup.long 0x00++0x03 line.long 0x00 "LPTIM2_ISR,LPTIM Interrupt and Status Register" bitfld.long 0x00 6. " DOWN ,Counter direction change up to down" "No change,DOWN direction" bitfld.long 0x00 5. " UP ,Counter direction change down to up" "No change,UP direction" bitfld.long 0x00 4. " ARROK ,Autoreload register update OK" "Writing,Write complete" bitfld.long 0x00 3. " CMPOK ,Compare register update OK" "Writing,Write complete" textline " " bitfld.long 0x00 2. " EXTTRIG ,External trigger edge event" "No valid edge event,Valid edge event" bitfld.long 0x00 1. " ARRM ,Autoreload match" "CNT 2clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock Polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..." textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" else rgroup.long 0x0C++0x03 line.long 0x00 "LPTIM2_CFGR,LPTIM Configuration Register" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After each write access,At the end of period" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM/One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Sw trigger,Rising edge,Falling edge,Both edges" bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "ext_trig0,ext_trig1,ext_trig2,ext_trig3,ext_trig4,ext_trig5,ext_trig6,ext_trig7" textline " " bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock Polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..." textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" endif else group.long 0x0C++0x03 line.long 0x00 "LPTIM2_CFGR,LPTIM Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After each write access,At the end of period" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM/One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Sw trigger,Rising edge,Falling edge,Both edges" bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "ext_trig0,ext_trig1,ext_trig2,ext_trig3,ext_trig4,ext_trig5,ext_trig6,ext_trig7" textline " " bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "All valid,>2 clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "All valid,>2clock periods,>4 clock periods,>8 clock periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock Polarity" "Rising edge,Falling edge,Both edges," textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" endif if (((per.l(ad:0x40009410))&0x1)==0x1) group.long 0x10++0x03 line.long 0x00 "LPTIM2_CR,LPTIM Control Register" bitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "No effect,Start" bitfld.long 0x00 1. " SNGSTRT ,Timer start in single mode" "No effect,Start" bitfld.long 0x00 0. " ENABLE ,LPTIM Enable" "Disabled,Enabled" group.long 0x14++0x07 line.long 0x00 "LPTIM2_CMP,LPTIM Compare Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Compare value" line.long 0x04 "LPTIM2_ARR,LPTIM Autoreload Register" hexmask.long.word 0x04 0.--15. 1. " ARR ,Auto reload value" else group.long 0x10++0x03 line.long 0x00 "LPTIM2_CR,LPTIM Control Register" rbitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "No effect,Start" rbitfld.long 0x00 1. " SNGSTRT ,Timer start in single mode" "No effect,Start" bitfld.long 0x00 0. " ENABLE ,LPTIM Enable" "Disabled,Enabled" rgroup.long 0x14++0x07 line.long 0x00 "LPTIM2_CMP,LPTIM Compare Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Compare value" line.long 0x04 "LPTIM2_ARR,LPTIM Autoreload Register" hexmask.long.word 0x04 0.--15. 1. " ARR ,Auto reload value" endif rgroup.long 0x1C++0x03 line.long 0x00 "LPTIM2_CNT,LPTIM Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") group.long 0x20++0x03 line.long 0x00 "LPTIM2_OR,LPTIM Option Register" bitfld.long 0x00 1. " OR_1 ,Option register bit 1" "I1 connected to I/O,I1 connected to COMP2_OUT" bitfld.long 0x00 0. " OR_0 ,Option register bit 0" "I1 connected to I/O,I1 connected to COMP1_OUT" endif width 0x0B tree.end tree.end tree "IWDG (Independent watchdog)" base ad:0x40003000 width 11. wgroup.long 0x00++0x03 line.long 0x00 "IWDG_KR,Key Register" hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value" group.long 0x04++0x03 line.long 0x00 "IWDG_PR,Prescaler Register" bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256" if (((per.l(ad:0x4000300C))&0x2)==0x0) group.long 0x08++0x03 line.long 0x00 "IWDG_RLR,Reload Register" hexmask.long.word 0x00 0.--11. 1. " RL ,Watchdog counter reload value" else rgroup.long 0x08++0x03 line.long 0x00 "IWDG_RLR,Reload Register" hexmask.long.word 0x00 0.--11. 1. " RL ,Watchdog counter reload value" endif rgroup.long 0x0C++0x03 line.long 0x00 "IWDG_SR,Status Register" bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "No update,Update ongoing" bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "No update,Update ongoing" bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "No update,Update ongoing" if (((per.l(ad:0x4000300C))&0x4)==0x0) group.long 0x10++0x03 line.long 0x00 "IWDG_WINR,Window Register" hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value" else rgroup.long 0x10++0x03 line.long 0x00 "IWDG_WINR,Window Register" hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value" endif width 0x0B tree.end tree "WWDG (System window watchdog)" base ad:0x40002C00 width 10. group.long 0x00++0x0B line.long 0x00 "WWDG_CR,Control Register" bitfld.long 0x00 7. " WDGA ,Activation bit for watchdog" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter (MSB to LSB)" line.long 0x04 "WWDG_CFR,Configuration Register" bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt" bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div1,Div2,Div4,Div8" hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value" line.long 0x08 "WWDG_SR,Status Register" bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "Counter<0x40,0x40 reached" width 0x0B tree.end tree "RTC (Real-time clock)" base ad:0x40002800 width 14. if (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)!=0x200000)) group.long 0x00++0x03 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)==0x200000)) group.long 0x00++0x03 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x08)&0x40)==0x40)&&((per.l(ad:0x40002800)&0x300000)==0x100000)) group.long 0x00++0x03 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x00++0x03 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif if ((((per.l(ad:0x40002800+0x04))&0x1000)==0x1000)&&(((per.l(ad:0x40002800+0x04))&0x30)==0x30)) group.long 0x04++0x03 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. " YU ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" textline " " bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x04))&0x1000)==0x1000)&&(((per.l(ad:0x40002800+0x04))&0x30)!=0x30)) group.long 0x04++0x03 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. " YU ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" textline " " bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x04))&0x1000)!=0x1000)&&(((per.l(ad:0x40002800+0x04))&0x30)==0x30)) group.long 0x04++0x03 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. " YU ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" textline " " bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x04))&0x1000)!=0x1000)&&(((per.l(ad:0x40002800+0x04))&0x30)!=0x30)) group.long 0x04++0x03 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. " YU ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" textline " " bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif if (((per.l(ad:0x40002800+0xC))&0x40)==0x40&&((per.l(ad:0x40002800+0x8))&0x400)==0x0&&((per.l(ad:0x40002800+0xC))&0x400)==0x400) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x0)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x0)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x400)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" rbitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x400)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x00)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x0)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x400)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x00)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" rbitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x0)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x0)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x00)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" rbitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x0)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x400)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x400)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" rbitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x400)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x400)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" elif ((((per.l(ad:0x40002800+0xC))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x8))&0x400)==0x0)&&(((per.l(ad:0x40002800+0xC))&0x400)==0x00)) group.long 0x08++0x03 line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,AlarmA,AlarmB,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" textline " " bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" bitfld.long 0x00 18. " BKP ,Backup. DSTC(Daylight Saving Time Change)" "DSTC not performed,DSTC performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Substracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" textline " " bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TSE ,Timestamp enable" "Disabled,Enabled" bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FMT ,Hour format" "24 hour,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Calendar from shadow,Calendar directly" bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising,Falling" textline " " rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,ck_spre,ck_spre,ck_spre+2^16,ck_spre+2^16" endif group.long 0x0C++0x0B line.long 0x00 "RTC_ISR,RTC initialization and status register" bitfld.long 0x00 17. " ITSF ,Internal Time-stamp flag" "No time-stamp event,Time-stamp event" rbitfld.long 0x00 16. " RECALPF ,Recalibration pending Flag" "RTC_CALR unlocked,RTC_CALR locked" textline " " bitfld.long 0x00 15. " TAMP3F ,RTC_TAMP3 detection flag" "No tamper detection,Tamper detection" textline " " bitfld.long 0x00 14. " TAMP2F ,RTC_TAMP2 detection flag" "No tamper detection,Tamper detection" textline " " bitfld.long 0x00 13. " TAMP1F ,RTC_TAMP1 detection flag" "No tamper detection,Tamper detection" textline " " bitfld.long 0x00 12. " TSOVF ,Time-stamp overflow flag" "TSF not set,TSF already set" bitfld.long 0x00 11. " TSF ,Time-stamp flag" "No time-stamp event,Time-stamp event" bitfld.long 0x00 10. " WUTF ,Wakeup timer flag" "Counter>0,Counter=0" bitfld.long 0x00 9. " ALRBF ,Alarm B flag" "Time/date<>AlarmB,Time/date=AlarmB" textline " " bitfld.long 0x00 8. " ALRAF ,Alarm A flag" "Time/date<>AlarmA,Time/date=AlarmA" bitfld.long 0x00 7. " INIT ,Initialization mode" "Free running,Initialization" rbitfld.long 0x00 6. " INITF ,Initialization flag" "Update not allowed,Update allowed" bitfld.long 0x00 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized" textline " " rbitfld.long 0x00 4. " INITS ,Initialization status flag" "Not initialized,Initialized" rbitfld.long 0x00 3. " SHPF ,Shift operation pending" "Not pending,Pending" rbitfld.long 0x00 2. " WUTWF ,Wakeup timer write flag" "Update not allowed,Update allowed" rbitfld.long 0x00 1. " ALRBWF ,Alarm B write flag" "Update not allowed,Update allowed" textline " " rbitfld.long 0x00 0. " ALRAWF ,Alarm A write flag" "Update not allowed,Update allowed" line.long 0x04 "RTC_PRER,RTC prescaler register" hexmask.long.byte 0x04 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor" hexmask.long.word 0x04 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor" line.long 0x08 "RTC_WUTR,RTC wakeup timer register" hexmask.long.word 0x08 0.--15. 1. " WUT ,Wakeup auto-reload value bits" if ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0xC+0x10))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0xC+0x10))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0xC+0x10))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0xC+0x10))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x0)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0xC+0x10))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000)) group.long 0x1c++0x03 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif if ((((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x300000)!=0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x300000)==0x200000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x30000000)!=0x30000000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x0)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 28.--29. " DT ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" textline " " bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x300000)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x20))&0x300000)==0x100000)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40)&&(((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000)) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Date/day match,Date/day don't care" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" bitfld.long 0x00 24.--27. " DU ,Date units or day in BCD format" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked" textline " " bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif wgroup.long 0x24++0x03 line.long 0x00 "RTC_WPR,RTC write protection register" hexmask.long.byte 0x00 0.--7. 1. " KEY ,Write protection key" rgroup.long 0x28++0x03 line.long 0x00 "RTC_SSR,RTC sub second register" hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value" wgroup.long 0x2c++0x03 line.long 0x00 "RTC_SHIFTR,RTC shift control register" bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,1 second added" hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second" if ((per.l(ad:0x40002800+0x0C)&0x800)==0x00) hgroup.long 0x30++0x03 hide.long 0x00 "RTC_TSTR,RTC time stamp time register" elif (((per.l(ad:0x40002800+0xC)&0x800)==0x800)&&((per.l(ad:0x40002800+0x8)&0x40)==0x0))&&(((per.l(ad:0x40002800+0x30))&0x300000)==0x200000) rgroup.long 0x30++0x03 line.long 0x00 "RTC_TSTR,RTC timestamp time register" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0xC)&0x800)==0x800)&&((per.l(ad:0x40002800+0x8)&0x40)==0x0))&&(((per.l(ad:0x40002800+0x30))&0x300000)!=0x200000) rgroup.long 0x30++0x03 line.long 0x00 "RTC_TSTR,RTC timestamp time register" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0xC)&0x800)==0x800)&&((per.l(ad:0x40002800+0x8)&0x40)==0x40))&&(((per.l(ad:0x40002800+0x30))&0x300000)==0x100000) rgroup.long 0x30++0x03 line.long 0x00 "RTC_TSTR,RTC timestamp time register" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else rgroup.long 0x30++0x03 line.long 0x00 "RTC_TSTR,RTC timestamp time register" bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM" bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-" textline " " bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif if ((per.l(ad:0x40002800+0x0C)&0x800)==0x00) hgroup.long 0x34++0x03 hide.long 0x00 "RTC_TSDR,RTC timestamp date register" elif ((((per.l(ad:0x40002800+0x34))&0x1000)==0x1000)&&(((per.l(ad:0x40002800+0x34))&0x30)==0x30)&&(((per.l(ad:0x40002800+0xC))&0x800)==0x800)) rgroup.long 0x34++0x03 line.long 0x00 "RTC_TSDR,RTC timestamp date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" textline " " bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x34))&0x1000)!=0x1000)&&(((per.l(ad:0x40002800+0x34))&0x30)==0x30)&&(((per.l(ad:0x40002800+0xC))&0x800)==0x800)) rgroup.long 0x34++0x03 line.long 0x00 "RTC_TSDR,RTC timestamp date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" textline " " bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" elif ((((per.l(ad:0x40002800+0x34))&0x1000)==0x1000)&&(((per.l(ad:0x40002800+0x34))&0x30)!=0x30)&&(((per.l(ad:0x40002800+0xC))&0x800)==0x800)) rgroup.long 0x34++0x03 line.long 0x00 "RTC_TSDR,RTC timestamp date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" textline " " bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else rgroup.long 0x34++0x03 line.long 0x00 "RTC_TSDR,RTC timestamp date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--5. " DT ,Date tens in BCD format" "0,1,2,3" textline " " bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") if ((per.l(ad:0x40002800+0x0C)&0x800)==0x800) rgroup.long 0x38++0x03 line.long 0x00 "RTC_TSSSR,RTC time-stamp sub second register" hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value" else hgroup.long 0x38++0x03 hide.long 0x00 "RTC_TSSSR,RTC time-stamp sub second register" endif else rgroup.long 0x38++0x03 line.long 0x00 "RTC_TSSSR,RTC time-stamp sub second register" hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value" endif group.long 0x3C++0x03 line.long 0x00 "RTC_CALR,RTC calibration register" bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No pulses,1 pulse every 2^11" bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "No 8 sec calib,8 sec calibration" bitfld.long 0x00 13. " CALW16 ,Use an 16-second calibration cycle period" "No 16 sec calib,16 sec calibration" hexmask.long.word 0x00 0.--8. 1. " CALM ,Calibration minus" if (((per.l(ad:0x40002800+0x30+0x10))&0x1800)==0x0) group.long 0x40++0x03 line.long 0x00 "RTC_TAMPCR,RTC tamper configuration register" bitfld.long 0x00 24. " TAMP3MF ,Tamper 3 mask flag" "Not masked,Masked" bitfld.long 0x00 23. " TAMP3NOERASE ,Tamper 3 no erase" "Erased,Not erased" bitfld.long 0x00 22. " TAMP3IE ,Tamper 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked" bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "Erased,Not erased" bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked" bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "Erased,Not erased" bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "Enabled,Disabled" bitfld.long 0x00 13.--14. " TAMPPRCH ,RTC_TAMPx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "On edge of RTC_TAMPx,After 2 samples,After 4 samples,After 8 samples" bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256" textline " " bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "No save,Save" textline " " bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Rising edge,Falling edge" bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP2 input" "Rising edge,Falling edge" bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 input detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Rising edge,Falling edge" bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled" else group.long 0x40++0x03 line.long 0x00 "RTC_TAMPCR,RTC tamper configuration register" bitfld.long 0x00 24. " TAMP3MF ,Tamper 3 mask flag" "Not masked,Masked" bitfld.long 0x00 23. " TAMP3NOERASE ,Tamper 3 no erase" "Erased,Not erased" bitfld.long 0x00 22. " TAMP3IE ,Tamper 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked" bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "Erased,Not erased" bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked" bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "Erased,Not erased" bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "Enabled,Disabled" bitfld.long 0x00 13.--14. " TAMPPRCH ,RTC_TAMPx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "On edge of RTC_TAMPx,After 2 samples,After 4 samples,After 8 samples" bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256" textline " " bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "No save,Save" textline " " bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Low,High" bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP2 input" "Low,High" bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 input detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High" bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled" endif sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") if ((per.l(ad:0x40002800+0x0C)&0x80)==0x80)||((per.l(ad:0x40002800+0x08)&0x100)==0x00) group.long 0x44++0x03 line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared" hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" else rgroup.long 0x44++0x03 line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared" hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" endif else group.long 0x44++0x03 line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,SS[14:0] compared" hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" endif sif (cpuis("STM32L431*"))||(cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||cpuis("STM32L4?6*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") if ((per.l(ad:0x40002800+0x0C)&0x80)==0x80)||((per.l(ad:0x40002800+0x08)&0x200)==0x00) group.long 0x48++0x03 line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,SS[14:0] compared" hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" else rgroup.long 0x48++0x03 line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,SS[14:0] compared" hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" endif else group.long 0x48++0x03 line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,SS[14:0] compared" hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" endif group.long 0x4C++0x03 line.long 0x00 "RTC_OR,RTC option register" bitfld.long 0x00 1. " RTC_OUT_RMP ,RTC_OUT remap" "No remap,Remapped" bitfld.long 0x00 0. " RTC_ALARM_TYPE ,RTC_ALARM on PC13 output type" "Open-drain,Push-pull" tree "RTC backup registers" group.long 0x50++0x03 line.long 0x00 "RTC_BKP0R,RTC backup register 0" group.long 0x54++0x03 line.long 0x00 "RTC_BKP1R,RTC backup register 1" group.long 0x58++0x03 line.long 0x00 "RTC_BKP2R,RTC backup register 2" group.long 0x5C++0x03 line.long 0x00 "RTC_BKP3R,RTC backup register 3" group.long 0x60++0x03 line.long 0x00 "RTC_BKP4R,RTC backup register 4" group.long 0x64++0x03 line.long 0x00 "RTC_BKP5R,RTC backup register 5" group.long 0x68++0x03 line.long 0x00 "RTC_BKP6R,RTC backup register 6" group.long 0x6C++0x03 line.long 0x00 "RTC_BKP7R,RTC backup register 7" group.long 0x70++0x03 line.long 0x00 "RTC_BKP8R,RTC backup register 8" group.long 0x74++0x03 line.long 0x00 "RTC_BKP9R,RTC backup register 9" group.long 0x78++0x03 line.long 0x00 "RTC_BKP10R,RTC backup register 10" group.long 0x7C++0x03 line.long 0x00 "RTC_BKP11R,RTC backup register 11" group.long 0x80++0x03 line.long 0x00 "RTC_BKP12R,RTC backup register 12" group.long 0x84++0x03 line.long 0x00 "RTC_BKP13R,RTC backup register 13" group.long 0x88++0x03 line.long 0x00 "RTC_BKP14R,RTC backup register 14" group.long 0x8C++0x03 line.long 0x00 "RTC_BKP15R,RTC backup register 15" group.long 0x90++0x03 line.long 0x00 "RTC_BKP16R,RTC backup register 16" group.long 0x94++0x03 line.long 0x00 "RTC_BKP17R,RTC backup register 17" group.long 0x98++0x03 line.long 0x00 "RTC_BKP18R,RTC backup register 18" group.long 0x9C++0x03 line.long 0x00 "RTC_BKP19R,RTC backup register 19" group.long 0xA0++0x03 line.long 0x00 "RTC_BKP20R,RTC backup register 20" group.long 0xA4++0x03 line.long 0x00 "RTC_BKP21R,RTC backup register 21" group.long 0xA8++0x03 line.long 0x00 "RTC_BKP22R,RTC backup register 22" group.long 0xAC++0x03 line.long 0x00 "RTC_BKP23R,RTC backup register 23" group.long 0xB0++0x03 line.long 0x00 "RTC_BKP24R,RTC backup register 24" group.long 0xB4++0x03 line.long 0x00 "RTC_BKP25R,RTC backup register 25" group.long 0xB8++0x03 line.long 0x00 "RTC_BKP26R,RTC backup register 26" group.long 0xBC++0x03 line.long 0x00 "RTC_BKP27R,RTC backup register 27" group.long 0xC0++0x03 line.long 0x00 "RTC_BKP28R,RTC backup register 28" group.long 0xC4++0x03 line.long 0x00 "RTC_BKP29R,RTC backup register 29" group.long 0xC8++0x03 line.long 0x00 "RTC_BKP30R,RTC backup register 30" group.long 0xCC++0x03 line.long 0x00 "RTC_BKP31R,RTC backup register 31" tree.end width 0x0B tree.end tree "I2C (Inter-integrated circuit interface)" tree "I2C 1" base ad:0x40005400 width 15. if ((((per.l(ad:0x40005400))&0x100000)==0x100000)&&(((per.l(ad:0x40005400))&0x1)==0x0)&&(((per.l(ad:0x40005400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)==0x100000)&&(((per.l(ad:0x40005400))&0x1)==0x0)&&(((per.l(ad:0x40005400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)==0x100000)&&(((per.l(ad:0x40005400))&0x1)!=0x0)&&(((per.l(ad:0x40005400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)!=0x100000)&&(((per.l(ad:0x40005400))&0x1)==0x0)&&(((per.l(ad:0x40005400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)==0x100000)&&(((per.l(ad:0x40005400))&0x1)!=0x0)&&(((per.l(ad:0x40005400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)!=0x100000)&&(((per.l(ad:0x40005400))&0x1)==0x0)&&(((per.l(ad:0x40005400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)!=0x100000)&&(((per.l(ad:0x40005400))&0x1)!=0x0)&&(((per.l(ad:0x40005400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005400))&0x100000)!=0x100000)&&(((per.l(ad:0x40005400))&0x1)!=0x0)&&(((per.l(ad:0x40005400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif if (((per.l(ad:0x40005400+0x04))&0x2000)==0x0) group.long 0x04++0x03 line.long 0x00 "I2C1_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Not reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" bitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" bitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" else group.long 0x04++0x03 line.long 0x00 "I2C1_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "No reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" rbitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" rbitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " rbitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" endif if (((per.l(ad:0x40005400+0x08))&0x8000)==0x0) group.long 0x08++0x03 line.long 0x00 "I2C1_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C1_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" endif if (((per.l(ad:0x40005400+0x0c))&0x8000)==0x0) group.long 0x0C++0x03 line.long 0x00 "I2C1_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" else group.long 0x0C++0x03 line.long 0x00 "I2C1_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" endif if (((per.l(ad:0x40005400))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "I2C1_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" else rgroup.long 0x10++0x03 line.long 0x00 "I2C1_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" endif if (((per.l(ad:0x40005400+0x14))&0x8000)==0x0) group.long 0x14++0x03 line.long 0x00 "I2C1_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" else group.long 0x14++0x03 line.long 0x00 "I2C1_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" endif rgroup.long 0x18++0x03 line.long 0x00 "I2C1_ISR,Interrupt and Status Register" hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code (Slave mode)" bitfld.long 0x00 16. " DIR ,Transfer direction (Slave mode)" "Write,Read" bitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy" bitfld.long 0x00 13. " ALERT ,SMBus alert" "No alert,Alert" textline " " bitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "No timeout,Timeout" bitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error" bitfld.long 0x00 10. " OVR ,Overrun/underrun (slave mode)" "No error,Error" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "No loss,Arbitration loss" textline " " bitfld.long 0x00 8. " BERR ,Bus error" "Not detected,Misplaced start/stop" bitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not detected,Misplaced start/stop" bitfld.long 0x00 6. " TC ,Transfer complete (master mode)" "Transfer ongoing,Transfer complete" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "No stop,Stop" textline " " bitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "No NACK,NACK" bitfld.long 0x00 3. " ADDR ,Address matched (slave mode)" "Not matched,Matched" bitfld.long 0x00 2. " RXNE ,Receive data register not empty (receivers)" "Empty,Not empty" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status (transmitters)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TXE ,Transmit data register empty (transmitters)" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C1_ICR,Interrupt Clear Register" bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear" bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear" bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear" bitfld.long 0x00 10. " OVRCF ,Overrun/underrun flag clear" "No effect,Clear" textline " " bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear" rgroup.long 0x20++0x03 line.long 0x00 "I2C1_PECR,PEC Register" hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register" rgroup.long 0x24++0x03 line.long 0x00 "I2C1_RXDR,Receive Data Register" hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data" if (((per.l(ad:0x40005400+0x18))&0x1)==0x1) group.long 0x28++0x03 line.long 0x00 "I2C1_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" else rgroup.long 0x28++0x03 line.long 0x00 "I2C1_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" endif width 0x0B tree.end sif (!cpuis("STM32L431K*")) tree "I2C 2" base ad:0x40005800 width 15. if ((((per.l(ad:0x40005800))&0x100000)==0x100000)&&(((per.l(ad:0x40005800))&0x1)==0x0)&&(((per.l(ad:0x40005800))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)==0x100000)&&(((per.l(ad:0x40005800))&0x1)==0x0)&&(((per.l(ad:0x40005800))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)==0x100000)&&(((per.l(ad:0x40005800))&0x1)!=0x0)&&(((per.l(ad:0x40005800))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)!=0x100000)&&(((per.l(ad:0x40005800))&0x1)==0x0)&&(((per.l(ad:0x40005800))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)==0x100000)&&(((per.l(ad:0x40005800))&0x1)!=0x0)&&(((per.l(ad:0x40005800))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)!=0x100000)&&(((per.l(ad:0x40005800))&0x1)==0x0)&&(((per.l(ad:0x40005800))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)!=0x100000)&&(((per.l(ad:0x40005800))&0x1)!=0x0)&&(((per.l(ad:0x40005800))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005800))&0x100000)!=0x100000)&&(((per.l(ad:0x40005800))&0x1)!=0x0)&&(((per.l(ad:0x40005800))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif if (((per.l(ad:0x40005800+0x04))&0x2000)==0x0) group.long 0x04++0x03 line.long 0x00 "I2C2_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Not reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" bitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" bitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" else group.long 0x04++0x03 line.long 0x00 "I2C2_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "No reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" rbitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" rbitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " rbitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" endif if (((per.l(ad:0x40005800+0x08))&0x8000)==0x0) group.long 0x08++0x03 line.long 0x00 "I2C2_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C2_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" endif if (((per.l(ad:0x40005800+0x0c))&0x8000)==0x0) group.long 0x0C++0x03 line.long 0x00 "I2C2_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" else group.long 0x0C++0x03 line.long 0x00 "I2C2_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" endif if (((per.l(ad:0x40005800))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "I2C2_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" else rgroup.long 0x10++0x03 line.long 0x00 "I2C2_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" endif if (((per.l(ad:0x40005800+0x14))&0x8000)==0x0) group.long 0x14++0x03 line.long 0x00 "I2C2_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" else group.long 0x14++0x03 line.long 0x00 "I2C2_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" endif rgroup.long 0x18++0x03 line.long 0x00 "I2C2_ISR,Interrupt and Status Register" hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code (Slave mode)" bitfld.long 0x00 16. " DIR ,Transfer direction (Slave mode)" "Write,Read" bitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy" bitfld.long 0x00 13. " ALERT ,SMBus alert" "No alert,Alert" textline " " bitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "No timeout,Timeout" bitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error" bitfld.long 0x00 10. " OVR ,Overrun/underrun (slave mode)" "No error,Error" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "No loss,Arbitration loss" textline " " bitfld.long 0x00 8. " BERR ,Bus error" "Not detected,Misplaced start/stop" bitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not detected,Misplaced start/stop" bitfld.long 0x00 6. " TC ,Transfer complete (master mode)" "Transfer ongoing,Transfer complete" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "No stop,Stop" textline " " bitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "No NACK,NACK" bitfld.long 0x00 3. " ADDR ,Address matched (slave mode)" "Not matched,Matched" bitfld.long 0x00 2. " RXNE ,Receive data register not empty (receivers)" "Empty,Not empty" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status (transmitters)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TXE ,Transmit data register empty (transmitters)" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C2_ICR,Interrupt Clear Register" bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear" bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear" bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear" bitfld.long 0x00 10. " OVRCF ,Overrun/underrun flag clear" "No effect,Clear" textline " " bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear" rgroup.long 0x20++0x03 line.long 0x00 "I2C2_PECR,PEC Register" hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register" rgroup.long 0x24++0x03 line.long 0x00 "I2C2_RXDR,Receive Data Register" hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data" if (((per.l(ad:0x40005800+0x18))&0x1)==0x1) group.long 0x28++0x03 line.long 0x00 "I2C2_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" else rgroup.long 0x28++0x03 line.long 0x00 "I2C2_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" endif width 0x0B tree.end endif tree "I2C 3" base ad:0x40005C00 width 15. if ((((per.l(ad:0x40005C00))&0x100000)==0x100000)&&(((per.l(ad:0x40005C00))&0x1)==0x0)&&(((per.l(ad:0x40005C00))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)==0x100000)&&(((per.l(ad:0x40005C00))&0x1)==0x0)&&(((per.l(ad:0x40005C00))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)==0x100000)&&(((per.l(ad:0x40005C00))&0x1)!=0x0)&&(((per.l(ad:0x40005C00))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)!=0x100000)&&(((per.l(ad:0x40005C00))&0x1)==0x0)&&(((per.l(ad:0x40005C00))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)==0x100000)&&(((per.l(ad:0x40005C00))&0x1)!=0x0)&&(((per.l(ad:0x40005C00))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)!=0x100000)&&(((per.l(ad:0x40005C00))&0x1)==0x0)&&(((per.l(ad:0x40005C00))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)!=0x100000)&&(((per.l(ad:0x40005C00))&0x1)!=0x0)&&(((per.l(ad:0x40005C00))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40005C00))&0x100000)!=0x100000)&&(((per.l(ad:0x40005C00))&0x1)!=0x0)&&(((per.l(ad:0x40005C00))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif if (((per.l(ad:0x40005C00+0x04))&0x2000)==0x0) group.long 0x04++0x03 line.long 0x00 "I2C3_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Not reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" bitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" bitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" else group.long 0x04++0x03 line.long 0x00 "I2C3_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "No reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" rbitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" rbitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " rbitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" endif if (((per.l(ad:0x40005C00+0x08))&0x8000)==0x0) group.long 0x08++0x03 line.long 0x00 "I2C3_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C3_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" endif if (((per.l(ad:0x40005C00+0x0c))&0x8000)==0x0) group.long 0x0C++0x03 line.long 0x00 "I2C3_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" else group.long 0x0C++0x03 line.long 0x00 "I2C3_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" endif if (((per.l(ad:0x40005C00))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "I2C3_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" else rgroup.long 0x10++0x03 line.long 0x00 "I2C3_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" endif if (((per.l(ad:0x40005C00+0x14))&0x8000)==0x0) group.long 0x14++0x03 line.long 0x00 "I2C3_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" else group.long 0x14++0x03 line.long 0x00 "I2C3_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" endif rgroup.long 0x18++0x03 line.long 0x00 "I2C3_ISR,Interrupt and Status Register" hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code (Slave mode)" bitfld.long 0x00 16. " DIR ,Transfer direction (Slave mode)" "Write,Read" bitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy" bitfld.long 0x00 13. " ALERT ,SMBus alert" "No alert,Alert" textline " " bitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "No timeout,Timeout" bitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error" bitfld.long 0x00 10. " OVR ,Overrun/underrun (slave mode)" "No error,Error" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "No loss,Arbitration loss" textline " " bitfld.long 0x00 8. " BERR ,Bus error" "Not detected,Misplaced start/stop" bitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not detected,Misplaced start/stop" bitfld.long 0x00 6. " TC ,Transfer complete (master mode)" "Transfer ongoing,Transfer complete" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "No stop,Stop" textline " " bitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "No NACK,NACK" bitfld.long 0x00 3. " ADDR ,Address matched (slave mode)" "Not matched,Matched" bitfld.long 0x00 2. " RXNE ,Receive data register not empty (receivers)" "Empty,Not empty" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status (transmitters)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TXE ,Transmit data register empty (transmitters)" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C3_ICR,Interrupt Clear Register" bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear" bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear" bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear" bitfld.long 0x00 10. " OVRCF ,Overrun/underrun flag clear" "No effect,Clear" textline " " bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear" rgroup.long 0x20++0x03 line.long 0x00 "I2C3_PECR,PEC Register" hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register" rgroup.long 0x24++0x03 line.long 0x00 "I2C3_RXDR,Receive Data Register" hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data" if (((per.l(ad:0x40005C00+0x18))&0x1)==0x1) group.long 0x28++0x03 line.long 0x00 "I2C3_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" else rgroup.long 0x28++0x03 line.long 0x00 "I2C3_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" endif width 0x0B tree.end sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) tree "I2C 4" base ad:0x40008400 width 15. if ((((per.l(ad:0x40008400))&0x100000)==0x100000)&&(((per.l(ad:0x40008400))&0x1)==0x0)&&(((per.l(ad:0x40008400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)==0x100000)&&(((per.l(ad:0x40008400))&0x1)==0x0)&&(((per.l(ad:0x40008400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)==0x100000)&&(((per.l(ad:0x40008400))&0x1)!=0x0)&&(((per.l(ad:0x40008400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)!=0x100000)&&(((per.l(ad:0x40008400))&0x1)==0x0)&&(((per.l(ad:0x40008400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)==0x100000)&&(((per.l(ad:0x40008400))&0x1)!=0x0)&&(((per.l(ad:0x40008400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)!=0x100000)&&(((per.l(ad:0x40008400))&0x1)==0x0)&&(((per.l(ad:0x40008400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)!=0x100000)&&(((per.l(ad:0x40008400))&0x1)!=0x0)&&(((per.l(ad:0x40008400))&0xF00)==0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif ((((per.l(ad:0x40008400))&0x100000)!=0x100000)&&(((per.l(ad:0x40008400))&0x1)!=0x0)&&(((per.l(ad:0x40008400))&0xF00)!=0x0)) group.long 0x00++0x03 line.long 0x00 "I2C4_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "High,Low" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 18. " WUPEN ,Wakeup from stop mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "Enabled,Disabled" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,11 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" textline " " bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable (slave only)" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif if (((per.l(ad:0x40008400+0x04))&0x2000)==0x0) group.long 0x04++0x03 line.long 0x00 "I2C4_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Not reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" bitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" bitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" else group.long 0x04++0x03 line.long 0x00 "I2C4_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC transfer,PEC transfer" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode (master mode)" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "No reloaded,Reloaded" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes" textline " " bitfld.long 0x00 15. " NACK ,NACK generation (slave mode)" "ACK sent,NACK sent" bitfld.long 0x00 14. " STOP ,Stop generation (master mode)" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction (master receiver mode)" "10b read sequence,7b address" textline " " rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode (master mode)" "7b addressing mode,10b addressing mode" rbitfld.long 0x00 10. " RD_WRN ,Transfer direction (master mode)" "Write,Read" rbitfld.long 0x00 8.--9. " SADD ,Slave address bit 9:8 (master mode)" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " SADD ,Slave address bit 7:1 (master mode)" textline " " rbitfld.long 0x00 0. " SADD0 ,Slave address bit 0 (master mode)" "0,1" endif if (((per.l(ad:0x40008400+0x08))&0x8000)==0x0) group.long 0x08++0x03 line.long 0x00 "I2C4_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C4_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7b,10b" rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x2 " OA1[7:1],Interface address" textline " " rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1" endif if (((per.l(ad:0x40008400+0x0c))&0x8000)==0x0) group.long 0x0C++0x03 line.long 0x00 "I2C4_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" else group.long 0x0C++0x03 line.long 0x00 "I2C4_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No masks,OA2[1] masked,OA2[2:1] masked,OA2[3:1] masked,OA2[4:1] masked,OA2[5:1] masked,OA2[6:1] masked,OA2[7:1] masked" hexmask.long.byte 0x00 1.--7. 0x2 " OA2 ,Interface address" endif if (((per.l(ad:0x40008400))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "I2C4_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" else rgroup.long 0x10++0x03 line.long 0x00 "I2C4_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period (master mode)" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period (master mode)" endif if (((per.l(ad:0x40008400+0x14))&0x8000)==0x0) group.long 0x14++0x03 line.long 0x00 "I2C4_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" else group.long 0x14++0x03 line.long 0x00 "I2C4_TIMEOUTR,Timeout Register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus Timeout A" endif rgroup.long 0x18++0x03 line.long 0x00 "I2C4_ISR,Interrupt and Status Register" hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code (Slave mode)" bitfld.long 0x00 16. " DIR ,Transfer direction (Slave mode)" "Write,Read" bitfld.long 0x00 15. " BUSY ,Bus busy" "Idle,Busy" bitfld.long 0x00 13. " ALERT ,SMBus alert" "No alert,Alert" textline " " bitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "No timeout,Timeout" bitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error" bitfld.long 0x00 10. " OVR ,Overrun/underrun (slave mode)" "No error,Error" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "No loss,Arbitration loss" textline " " bitfld.long 0x00 8. " BERR ,Bus error" "Not detected,Misplaced start/stop" bitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not detected,Misplaced start/stop" bitfld.long 0x00 6. " TC ,Transfer complete (master mode)" "Transfer ongoing,Transfer complete" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "No stop,Stop" textline " " bitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "No NACK,NACK" bitfld.long 0x00 3. " ADDR ,Address matched (slave mode)" "Not matched,Matched" bitfld.long 0x00 2. " RXNE ,Receive data register not empty (receivers)" "Empty,Not empty" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status (transmitters)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TXE ,Transmit data register empty (transmitters)" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C4_ICR,Interrupt Clear Register" bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear" bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear" bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear" bitfld.long 0x00 10. " OVRCF ,Overrun/underrun flag clear" "No effect,Clear" textline " " bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear" rgroup.long 0x20++0x03 line.long 0x00 "I2C4_PECR,PEC Register" hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register" rgroup.long 0x24++0x03 line.long 0x00 "I2C4_RXDR,Receive Data Register" hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data" if (((per.l(ad:0x40008400+0x18))&0x1)==0x1) group.long 0x28++0x03 line.long 0x00 "I2C4_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" else rgroup.long 0x28++0x03 line.long 0x00 "I2C4_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" endif width 0x0B tree.end endif tree.end tree "USART (Universal synchronous asynchronous receiver/transmitter)" tree "USART1" base ad:0x40013800 width 13. if (((per.l(ad:0x40013800))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "USART1_CR1,Control Register 1" bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "USART1_CR1,Control Register 1" bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40013800))&0x09)==0x00) group.long 0x04++0x03 line.long 0x00 "USART1_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" bitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif (((per.l(ad:0x40013800))&0x09)==0x08) group.long 0x04++0x03 line.long 0x00 "USART1_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40013800))&0x5)==0x1)&&(((per.l(ad:0x40013800+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART1_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40013800))&0x5)==0x1)&&(((per.l(ad:0x40013800+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART1_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40013800))&0x5)==0x5)&&(((per.l(ad:0x40013800+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART1_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40013800))&0x5)==0x5)&&(((per.l(ad:0x40013800+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART1_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" endif if (((per.l(ad:0x40013800))&0x1)==0x0) group.long 0x08++0x03 line.long 0x00 "USART1_CR3,Control Register 3" sif (cpuis("STM32L471*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " WUS ,Wakeup from stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "USART1_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" else group.long 0x08++0x03 line.long 0x00 "USART1_CR3,Control Register 3" sif (cpuis("STM32L471*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,?..." textline " " rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "USART1_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" endif if (((per.l(ad:0x40013800))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "USART1_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART1_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART1_RTOR,Receiver Timeout Register" hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length" hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART1_RQR,Request Register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Transmit flush" textline " " bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,ABRF reset" rgroup.long 0x1C++0x03 line.long 0x00 "USART1_ISR,Interrupt & Status Register" sif (!cpuis("STM32L4?5*")) bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time completion" "Not completed,Completed" textline " " endif bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "No wakeup,Wakeup" bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not matched,Matched" bitfld.long 0x00 16. " BUSY ,Busy flag" "USART idle,Reception ongoing" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No auto baud,Auto baud" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" textline " " bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,EOB reached" textline " " bitfld.long 0x00 11. " RTOF ,Receiver timeout" "Not reached,Timeout reached" bitfld.long 0x00 10. " CTS ,CTS flag" "CTS set,CTS reset" bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "No break,Break" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty - indicates if received data is ready to be read" "Not ready,Ready" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,START bit noise detection flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" group.long 0x20++0x03 line.long 0x00 "USART1_ICR,Interrupt Flag Clear Register" eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear" eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " eventfld.long 0x00 12. " EOBCF ,End of block clear flag" "No effect,Clear" textline " " eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" textline " " sif (!cpuis("STM32L4?5*")) eventfld.long 0x00 7. " TCBGTCF ,Transmission completed before guard time clear flag" "No effect,Clear" textline " " endif eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" textline " " eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "USART1_RDR,Receive Data Register" hexmask.long.word 0x00 0.--8. 1. " RDR ,Receive data value" if (((per.l(ad:0x40013800+0x1C))&0x80)==0x80) group.long 0x28++0x03 line.long 0x00 "USART1_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" else rgroup.long 0x28++0x03 line.long 0x00 "USART1_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" endif width 0x0B tree.end tree "USART2" base ad:0x40004400 width 13. if (((per.l(ad:0x40004400))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "USART2_CR1,Control Register 1" bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "USART2_CR1,Control Register 1" bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40004400))&0x09)==0x00) group.long 0x04++0x03 line.long 0x00 "USART2_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" bitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif (((per.l(ad:0x40004400))&0x09)==0x08) group.long 0x04++0x03 line.long 0x00 "USART2_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004400))&0x5)==0x1)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART2_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004400))&0x5)==0x1)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART2_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004400))&0x5)==0x5)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART2_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004400))&0x5)==0x5)&&(((per.l(ad:0x40004400+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART2_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" endif if (((per.l(ad:0x40004400))&0x1)==0x0) group.long 0x08++0x03 line.long 0x00 "USART2_CR3,Control Register 3" sif (cpuis("STM32L471*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " WUS ,Wakeup from stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "USART2_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" else group.long 0x08++0x03 line.long 0x00 "USART2_CR3,Control Register 3" sif (cpuis("STM32L471*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,?..." textline " " rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "USART2_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" endif if (((per.l(ad:0x40004400))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "USART2_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART2_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART2_RTOR,Receiver Timeout Register" hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length" hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART2_RQR,Request Register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Transmit flush" textline " " bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,ABRF reset" rgroup.long 0x1C++0x03 line.long 0x00 "USART2_ISR,Interrupt & Status Register" sif (!cpuis("STM32L4?5*")) bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time completion" "Not completed,Completed" textline " " endif bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "No wakeup,Wakeup" bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not matched,Matched" bitfld.long 0x00 16. " BUSY ,Busy flag" "USART idle,Reception ongoing" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No auto baud,Auto baud" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" textline " " bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,EOB reached" textline " " bitfld.long 0x00 11. " RTOF ,Receiver timeout" "Not reached,Timeout reached" bitfld.long 0x00 10. " CTS ,CTS flag" "CTS set,CTS reset" bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "No break,Break" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty - indicates if received data is ready to be read" "Not ready,Ready" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,START bit noise detection flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" group.long 0x20++0x03 line.long 0x00 "USART2_ICR,Interrupt Flag Clear Register" eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear" eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " eventfld.long 0x00 12. " EOBCF ,End of block clear flag" "No effect,Clear" textline " " eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" textline " " sif (!cpuis("STM32L4?5*")) eventfld.long 0x00 7. " TCBGTCF ,Transmission completed before guard time clear flag" "No effect,Clear" textline " " endif eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" textline " " eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "USART2_RDR,Receive Data Register" hexmask.long.word 0x00 0.--8. 1. " RDR ,Receive data value" if (((per.l(ad:0x40004400+0x1C))&0x80)==0x80) group.long 0x28++0x03 line.long 0x00 "USART2_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" else rgroup.long 0x28++0x03 line.long 0x00 "USART2_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" endif width 0x0B tree.end sif (!cpuis("STM32L432*")&&!cpuis("STM32L442*")&&!cpuis("STM32L431K*")) tree "USART3" base ad:0x40004800 width 13. if (((per.l(ad:0x40004800))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "USART3_CR1,Control Register 1" bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "USART3_CR1,Control Register 1" bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40004800))&0x09)==0x00) group.long 0x04++0x03 line.long 0x00 "USART3_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" bitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif (((per.l(ad:0x40004800))&0x09)==0x08) group.long 0x04++0x03 line.long 0x00 "USART3_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004800))&0x5)==0x1)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART3_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004800))&0x5)==0x1)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART3_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004800))&0x5)==0x5)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART3_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004800))&0x5)==0x5)&&(((per.l(ad:0x40004800+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART3_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Steady low,Steady high" rbitfld.long 0x00 9. " CPHA ,Clock phase" "First transition,Second transition" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "No output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" endif if (((per.l(ad:0x40004800))&0x1)==0x0) group.long 0x08++0x03 line.long 0x00 "USART3_CR3,Control Register 3" sif (cpuis("STM32L471*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " WUS ,Wakeup from stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "USART3_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" else group.long 0x08++0x03 line.long 0x00 "USART3_CR3,Control Register 3" sif (cpuis("STM32L471*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) bitfld.long 0x00 24. " TCBGTIE ,Transmission complete before guard time interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,?..." textline " " rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "USART3_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" endif if (((per.l(ad:0x40004800))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "USART3_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART3_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" textline " " hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART3_RTOR,Receiver Timeout Register" hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length" hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART3_RQR,Request Register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Transmit flush" textline " " bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,ABRF reset" rgroup.long 0x1C++0x03 line.long 0x00 "USART3_ISR,Interrupt & Status Register" sif (!cpuis("STM32L4?5*")) bitfld.long 0x00 25. " TCBGT ,Transmission complete before guard time completion" "Not completed,Completed" textline " " endif bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "No wakeup,Wakeup" bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not matched,Matched" bitfld.long 0x00 16. " BUSY ,Busy flag" "USART idle,Reception ongoing" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No auto baud,Auto baud" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" textline " " bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,EOB reached" textline " " bitfld.long 0x00 11. " RTOF ,Receiver timeout" "Not reached,Timeout reached" bitfld.long 0x00 10. " CTS ,CTS flag" "CTS set,CTS reset" bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "No break,Break" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty - indicates if received data is ready to be read" "Not ready,Ready" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,START bit noise detection flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" group.long 0x20++0x03 line.long 0x00 "USART3_ICR,Interrupt Flag Clear Register" eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear" eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " eventfld.long 0x00 12. " EOBCF ,End of block clear flag" "No effect,Clear" textline " " eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" textline " " sif (!cpuis("STM32L4?5*")) eventfld.long 0x00 7. " TCBGTCF ,Transmission completed before guard time clear flag" "No effect,Clear" textline " " endif eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" textline " " eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "USART3_RDR,Receive Data Register" hexmask.long.word 0x00 0.--8. 1. " RDR ,Receive data value" if (((per.l(ad:0x40004800+0x1C))&0x80)==0x80) group.long 0x28++0x03 line.long 0x00 "USART3_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" else rgroup.long 0x28++0x03 line.long 0x00 "USART3_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" endif width 0x0B tree.end endif sif (!cpuis("STM32L4?2*")&&!cpuis("STM32L4?3*")&&!cpuis("STM32L431*")&&!cpuis("STM32L451*")) tree "UART4" base ad:0x40004C00 width 13. if (((per.l(ad:0x40004C00))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "USART4_CR1,Control Register 1" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "USART4_CR1,Control Register 1" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40004C00))&0x09)==0x00) group.long 0x04++0x03 line.long 0x00 "USART4_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif (((per.l(ad:0x40004C00))&0x09)==0x08) group.long 0x04++0x03 line.long 0x00 "USART4_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004C00))&0x5)==0x1)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART4_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004C00))&0x5)==0x1)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART4_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004C00))&0x5)==0x5)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART4_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40004C00))&0x5)==0x5)&&(((per.l(ad:0x40004C00+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART4_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" endif if (((per.l(ad:0x40004C00))&0x1)==0x0) group.long 0x08++0x03 line.long 0x00 "USART4_CR3,Control Register 3" sif (cpuis("STM32L471*")) elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " WUS ,Wakeup from stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "USART4_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" else group.long 0x08++0x03 line.long 0x00 "USART4_CR3,Control Register 3" sif (cpuis("STM32L471*")) elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "USART4_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" endif if (((per.l(ad:0x40004C00))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "USART4_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART4_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART4_RTOR,Receiver Timeout Register" hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length" hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART4_RQR,Request Register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,ABRF reset" rgroup.long 0x1C++0x03 line.long 0x00 "USART4_ISR,Interrupt & Status Register" sif (!cpuis("STM32L4?5*")) endif bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "No wakeup,Wakeup" bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not matched,Matched" bitfld.long 0x00 16. " BUSY ,Busy flag" "USART idle,Reception ongoing" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No auto baud,Auto baud" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" textline " " bitfld.long 0x00 11. " RTOF ,Receiver timeout" "Not reached,Timeout reached" bitfld.long 0x00 10. " CTS ,CTS flag" "CTS set,CTS reset" bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "No break,Break" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty - indicates if received data is ready to be read" "Not ready,Ready" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,START bit noise detection flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" group.long 0x20++0x03 line.long 0x00 "USART4_ICR,Interrupt Flag Clear Register" eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear" eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" textline " " sif (!cpuis("STM32L4?5*")) endif eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" textline " " eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "USART4_RDR,Receive Data Register" hexmask.long.word 0x00 0.--8. 1. " RDR ,Receive data value" if (((per.l(ad:0x40004C00+0x1C))&0x80)==0x80) group.long 0x28++0x03 line.long 0x00 "USART4_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" else rgroup.long 0x28++0x03 line.long 0x00 "USART4_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" endif width 0x0B tree.end tree "UART5" base ad:0x40005000 width 13. if (((per.l(ad:0x40005000))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "USART5_CR1,Control Register 1" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "USART5_CR1,Control Register 1" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "Mode 16,Mode 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" textline " " rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40005000))&0x09)==0x00) group.long 0x04++0x03 line.long 0x00 "USART5_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif (((per.l(ad:0x40005000))&0x09)==0x08) group.long 0x04++0x03 line.long 0x00 "USART5_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40005000))&0x5)==0x1)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART5_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40005000))&0x5)==0x1)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART5_CR2,Control Register 2" bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40005000))&0x5)==0x5)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x0)) group.long 0x04++0x03 line.long 0x00 "USART5_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif ((((per.l(ad:0x40005000))&0x5)==0x5)&&(((per.l(ad:0x40005000+0x04))&0x100000)==0x100000)) group.long 0x04++0x03 line.long 0x00 "USART5_CR2,Control Register 2" rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame" textline " " bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,0.5 stop bit,2 stop bits,1.5 stop bits" textline " " bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10b,11b" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" endif if (((per.l(ad:0x40005000))&0x1)==0x0) group.long 0x08++0x03 line.long 0x00 "USART5_CR3,Control Register 3" sif (cpuis("STM32L471*")) elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " WUS ,Wakeup from stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "USART5_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" else group.long 0x08++0x03 line.long 0x00 "USART5_CR3,Control Register 3" sif (cpuis("STM32L471*")) elif (cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*"))||(cpuis("STM32L432*"))||(cpuis("STM32L442KC*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) sif (!cpuis("STM32L475*")) endif bitfld.long 0x00 23. " UCESM ,USART clock enable in stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "USART5_BRR,Baud Rate Register" hexmask.long.word 0x00 0.--15. 1. " BRR ,Baud rate register" endif if (((per.l(ad:0x40005000))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "USART5_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART5_GTPR,Guard Time and Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART5_RTOR,Receiver Timeout Register" hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length" hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART5_RQR,Request Register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,ABRF reset" rgroup.long 0x1C++0x03 line.long 0x00 "USART5_ISR,Interrupt & Status Register" sif (!cpuis("STM32L4?5*")) endif bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "No wakeup,Wakeup" bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not matched,Matched" bitfld.long 0x00 16. " BUSY ,Busy flag" "USART idle,Reception ongoing" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No auto baud,Auto baud" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" textline " " bitfld.long 0x00 11. " RTOF ,Receiver timeout" "Not reached,Timeout reached" bitfld.long 0x00 10. " CTS ,CTS flag" "CTS set,CTS reset" bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "No break,Break" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty - indicates if received data is ready to be read" "Not ready,Ready" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,START bit noise detection flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" group.long 0x20++0x03 line.long 0x00 "USART5_ICR,Interrupt Flag Clear Register" eventfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear" eventfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " eventfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" eventfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" eventfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" textline " " sif (!cpuis("STM32L4?5*")) endif eventfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" eventfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" eventfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" eventfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" textline " " eventfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" eventfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "USART5_RDR,Receive Data Register" hexmask.long.word 0x00 0.--8. 1. " RDR ,Receive data value" if (((per.l(ad:0x40005000+0x1C))&0x80)==0x80) group.long 0x28++0x03 line.long 0x00 "USART5_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" else rgroup.long 0x28++0x03 line.long 0x00 "USART5_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" endif width 0x0B tree.end endif tree.end tree "LPUART (Low-power universal asynchronous receiver/transmitter)" base ad:0x40008000 width 14. sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")) if (((per.l(ad:0x40008000))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "LPUART1_CR1,Control Register 1" bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" textline " " bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "LPUART1_CR1,Control Register 1" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" textline " " bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40008000))&0x20000000)==0x20000000) if (((per.l(ad:0x40008000))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "LPUART1_CR1,Control Register 1" bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." textline " " bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "LPUART1_CR1,Control Register 1" bitfld.long 0x00 31. " RXFFIE ,RXFIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " TXFEIE ,TXFIFO empty interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." textline " " rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40008000))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "LPUART1_CR1,Control Register 1" bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "LPUART1_CR1,Control Register 1" bitfld.long 0x00 29. " FIFOEN ,FIFO mode enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable de-assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 12. 28. " M[1:0] ,Word length" "1b Start+8b Data,1b Start+9b Data,1b Start+7b data,?..." rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif endif endif if (((per.l(ad:0x40008000))&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "LPUART1_CR2,Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the LPUART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the LPUART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" else bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" endif textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,?..." bitfld.long 0x00 4. " ADDM7 ,7-bit address detection/4-bit address detection" "4b,7b" elif (((per.l(ad:0x40008000))&0x05)==0x01) group.long 0x04++0x03 line.long 0x00 "LPUART1_CR2,Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the LPUART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the LPUART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" else bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" endif textline " " rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" textline " " rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,?..." rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" elif (((per.l(ad:0x40008000))&0x05)==0x05) rgroup.long 0x04++0x03 line.long 0x00 "LPUART1_CR2,Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the LPUART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the LPUART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" else bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf" endif textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0b first,7/8/9b first" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive logic,Negative logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Standard,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Standard,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Standard,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,?..." bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4b,7b" endif if (((per.l(ad:0x40008000))&0x1)==0x0) group.long 0x08++0x07 line.long 0x00 "LPUART1_CR3,Control Register 3" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,,3/4,7/8,Empty,1/2,?..." bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,,3/4,7/8,Empty,1/2,?..." bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled" textline " " endif sif (cpuis("STM32L4?3*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L431*"))||(cpuis("STM32L442KC"))||(cpuis("STM32L432KC"))||(cpuis("STM32L475*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 23. " UCESM ,LPUART clock enable in stop mode" "Disabled,Enabled" textline " " endif sif (!cpuis("STM32H743*")&&!cpuis("STM32H753*")) bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " WUS ,Wakeup from stop mode interrupt flag selection" "Address match,,Start bit,RXNE" textline " " endif bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" line.long 0x04 "LPUART1_BRR,Baud Rate Register" hexmask.long.tbyte 0x04 0.--19. 1. " BRR ,Baud rate register" else group.long 0x08++0x03 line.long 0x00 "LPUART1_CR3,Control Register 3" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 29.--31. " TXFTCFG ,TXFIFO threshold configuration" "1/8,1/4,,3/4,7/8,Empty,1/2,?..." bitfld.long 0x00 28. " RXFTIE ,RXFIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25.--27. " RXFTCFG ,Receive FIFO threshold configuration" "1/8,1/4,,3/4,7/8,Empty,1/2,?..." bitfld.long 0x00 23. " TXFTIE ,TXFIFO threshold interrupt enable" "Disabled,Enabled" textline " " endif sif (cpuis("STM32L4?3*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L431*"))||(cpuis("STM32L442KC"))||(cpuis("STM32L432KC"))||(cpuis("STM32L475*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) bitfld.long 0x00 23. " UCESM ,LPUART Clock Enable in Stop mode" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " WUFIE ,Wakeup from stop mode interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Active high,Active low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "LPUART1_BRR,Baud Rate Register" hexmask.long.tbyte 0x00 0.--19. 1. " BRR ,Baud rate register" endif sif (cpuis("STM32H743*")||cpuis("STM32H753*")) if (((per.l(ad:0x40008000))&0x20000000)==0x20000000) wgroup.long 0x18++0x03 line.long 0x00 "LPUART1_RQR,Request Register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Transmit flush" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" else wgroup.long 0x18++0x03 line.long 0x00 "LPUART1_RQR,Request Register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" endif else wgroup.long 0x18++0x03 line.long 0x00 "LPUART1_RQR,Request Register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Receive flush" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Mute mode" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Break" endif rgroup.long 0x1C++0x03 line.long 0x00 "LPUART1_ISR,Interrupt & Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 27. " TXFT ,TXFIFO threshold flag" "Not reached,Reached" bitfld.long 0x00 26. " RXFT ,RXFIFO threshold flag" "Not reached,Reached" bitfld.long 0x00 24. " RXFF ,RXFIFO full" "Not full,Full" bitfld.long 0x00 23. " TXFE ,TXFIFO empty" "Not empty,Empty" textline " " endif bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled" bitfld.long 0x00 20. " WUF ,Wakeup from stop mode flag" "No wakeup,Wakeup" bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not matched,Matched" bitfld.long 0x00 16. " BUSY ,Busy flag" "USART Idle,Reception ongoing" bitfld.long 0x00 10. " CTS ,CTS flag" "CTS set,CTS reset" textline " " bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not empty,Empty" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty - indicates if received data is ready to be read" "Not ready,Ready" textline " " bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,START bit noise detection flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" textline " " bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "LPUART1_ICR,Interrupt Flag Clear Register" bitfld.long 0x00 20. " WUCF ,Wakeup from stop mode clear flag" "No effect,Clear" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" textline " " bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" textline " " bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "LPUART1_RDR,Receive Data Register" hexmask.long.word 0x00 0.--8. 1. " RDR ,Receive data value" if (((per.l(ad:0x40008000+0x1C))&0x80)==0x80) group.long 0x28++0x03 line.long 0x00 "LPUART1_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" else rgroup.long 0x28++0x03 line.long 0x00 "LPUART1_TDR,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value" endif sif (cpuis("STM32H743*")||cpuis("STM32H753*")) if (((per.l(ad:0x40008000))&0x1)==0x0) group.long 0x2C++0x03 line.long 0x00 "LPUART_PRESC,Prescaler Register" bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..." else rgroup.long 0x2C++0x03 line.long 0x00 "LPUART_PRESC,Prescaler Register" bitfld.long 0x00 0.--3. " PRESCALER ,Clock prescaler" "Not divided,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,?..." endif endif width 0x0B tree.end tree "SPI (Serial peripheral interface)" tree "SPI1" base ad:0x40013000 width 13. if ((((per.l(ad:0x40013000))&0x40)==0x0)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x0)) group.word 0x00++0x01 line.word 0x00 "SPI1_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 9. " SSM ,Software slave management enable" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "NSS,NSS ignored" bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock polarity" "CK to 0 when idle,CK to 1 when idle" bitfld.word 0x00 0. " CPHA ,Clock phase" "1st CLK transition,2nd CLK transition" elif ((((per.l(ad:0x40013000))&0x40)==0x40)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x0)) group.word 0x00++0x01 line.word 0x00 "SPI1_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" rbitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 9. " SSM ,Software slave management enable" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "NSS,NSS ignored" bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock polarity" "CK to 0 when idle,CK to 1 when idle" bitfld.word 0x00 0. " CPHA ,Clock phase" "1st CLK transition,2nd CLK transition" elif ((((per.l(ad:0x40013000))&0x40)==0x0)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI1_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" elif ((((per.l(ad:0x40013000))&0x40)==0x40)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI1_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" rbitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" endif if ((((per.l(ad:0x40013000))&0x41)==0x01)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI1_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40013000))&0x41)==0x41)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI1_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40013000))&0x40)==0x0)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI1_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40013000))&0x40)==0x40)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI1_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40013000))&0x40)==0x0)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI1_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40013000))&0x40)==0x40)&&(((per.l(ad:0x40013000+0x04))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI1_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" endif if (((per.l(ad:0x40013000))&0x2400)==0x2400) group.word 0x08++0x01 line.word 0x00 "SPI1_SR,SPI Status Register" rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" textline " " rbitfld.word 0x00 7. " BSY ,Busy flag" "Idle,Busy" rbitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" rbitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" else group.word 0x08++0x01 line.word 0x00 "SPI1_SR,SPI Status Register" rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" textline " " rbitfld.word 0x00 7. " BSY ,Busy flag" "Idle,Busy" rbitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" rbitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif if (((per.l(ad:0x40013000))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI1_DR,SPI Data Register" else group.word 0x0C++0x01 line.word 0x00 "SPI1_DR,SPI Data Register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data received or to be transmitted" endif group.word 0x10++0x01 line.word 0x00 "SPI1_CRCPR,SPI CRC Polynomial Register" if (((per.l(ad:0x40013000))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI1_RXCRCR,SPI Rx CRC Register" rgroup.word 0x18++0x01 line.word 0x00 "SPI1_TXCRCR,SPI Tx CRC Register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI1_RXCRCR,SPI Rx CRC Register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI1_TXCRCR,SPI Tx CRC Register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif width 0x0B tree.end sif (!cpuis("STM32L431K*")) tree "SPI2" base ad:0x40003800 width 13. if ((((per.l(ad:0x40003800))&0x40)==0x0)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x0)) group.word 0x00++0x01 line.word 0x00 "SPI2_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 9. " SSM ,Software slave management enable" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "NSS,NSS ignored" bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock polarity" "CK to 0 when idle,CK to 1 when idle" bitfld.word 0x00 0. " CPHA ,Clock phase" "1st CLK transition,2nd CLK transition" elif ((((per.l(ad:0x40003800))&0x40)==0x40)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x0)) group.word 0x00++0x01 line.word 0x00 "SPI2_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" rbitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 9. " SSM ,Software slave management enable" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "NSS,NSS ignored" bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock polarity" "CK to 0 when idle,CK to 1 when idle" bitfld.word 0x00 0. " CPHA ,Clock phase" "1st CLK transition,2nd CLK transition" elif ((((per.l(ad:0x40003800))&0x40)==0x0)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI2_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" elif ((((per.l(ad:0x40003800))&0x40)==0x40)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI2_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" rbitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" endif if ((((per.l(ad:0x40003800))&0x41)==0x01)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI2_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003800))&0x41)==0x41)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI2_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003800))&0x40)==0x0)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI2_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003800))&0x40)==0x40)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI2_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003800))&0x40)==0x0)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI2_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003800))&0x40)==0x40)&&(((per.l(ad:0x40003800+0x04))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI2_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" endif if (((per.l(ad:0x40003800))&0x2400)==0x2400) group.word 0x08++0x01 line.word 0x00 "SPI2_SR,SPI Status Register" rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" textline " " rbitfld.word 0x00 7. " BSY ,Busy flag" "Idle,Busy" rbitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" rbitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" else group.word 0x08++0x01 line.word 0x00 "SPI2_SR,SPI Status Register" rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" textline " " rbitfld.word 0x00 7. " BSY ,Busy flag" "Idle,Busy" rbitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" rbitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif if (((per.l(ad:0x40003800))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI2_DR,SPI Data Register" else group.word 0x0C++0x01 line.word 0x00 "SPI2_DR,SPI Data Register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data received or to be transmitted" endif group.word 0x10++0x01 line.word 0x00 "SPI2_CRCPR,SPI CRC Polynomial Register" if (((per.l(ad:0x40003800))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI2_RXCRCR,SPI Rx CRC Register" rgroup.word 0x18++0x01 line.word 0x00 "SPI2_TXCRCR,SPI Tx CRC Register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI2_RXCRCR,SPI Rx CRC Register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI2_TXCRCR,SPI Tx CRC Register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif width 0x0B tree.end endif tree "SPI3" base ad:0x40003C00 width 13. if ((((per.l(ad:0x40003C00))&0x40)==0x0)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x0)) group.word 0x00++0x01 line.word 0x00 "SPI3_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 9. " SSM ,Software slave management enable" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "NSS,NSS ignored" bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock polarity" "CK to 0 when idle,CK to 1 when idle" bitfld.word 0x00 0. " CPHA ,Clock phase" "1st CLK transition,2nd CLK transition" elif ((((per.l(ad:0x40003C00))&0x40)==0x40)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x0)) group.word 0x00++0x01 line.word 0x00 "SPI3_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" rbitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 9. " SSM ,Software slave management enable" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "NSS,NSS ignored" bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock polarity" "CK to 0 when idle,CK to 1 when idle" bitfld.word 0x00 0. " CPHA ,Clock phase" "1st CLK transition,2nd CLK transition" elif ((((per.l(ad:0x40003C00))&0x40)==0x0)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI3_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" elif ((((per.l(ad:0x40003C00))&0x40)==0x40)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI3_CR1,SPI Control Register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "2-line unidirectional,1-line bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Receive-only,Transmit-only" rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" rbitfld.word 0x00 11. " CRCL ,CRC length" "8b CRC,16b CRC" bitfld.word 0x00 10. " RXONLY ,Receive only mode enabled" "Full duplex,Output disabled" textline " " bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master" endif if ((((per.l(ad:0x40003C00))&0x41)==0x01)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI3_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003C00))&0x41)==0x41)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI3_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003C00))&0x40)==0x0)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI3_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003C00))&0x40)==0x40)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x0)) group.word 0x04++0x01 line.word 0x00 "SPI3_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No NSS,NSS generated" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003C00))&0x40)==0x0)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI3_CR2,SPI Control Register 2" bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40003C00))&0x40)==0x40)&&(((per.l(ad:0x40003C00+0x04))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI3_CR2,SPI Control Register 2" rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" rbitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd" bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" ">=1/2,>=1/4" textline " " bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4b,5b,6b,7b,8b,9b,10b,11b,12b,13b,14b,15b,16b" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola,TI" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" endif if (((per.l(ad:0x40003C00))&0x2400)==0x2400) group.word 0x08++0x01 line.word 0x00 "SPI3_SR,SPI Status Register" rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" textline " " rbitfld.word 0x00 7. " BSY ,Busy flag" "Idle,Busy" rbitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" rbitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" else group.word 0x08++0x01 line.word 0x00 "SPI3_SR,SPI Status Register" rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,Full" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" textline " " rbitfld.word 0x00 7. " BSY ,Busy flag" "Idle,Busy" rbitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" rbitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif if (((per.l(ad:0x40003C00))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI3_DR,SPI Data Register" else group.word 0x0C++0x01 line.word 0x00 "SPI3_DR,SPI Data Register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data received or to be transmitted" endif group.word 0x10++0x01 line.word 0x00 "SPI3_CRCPR,SPI CRC Polynomial Register" if (((per.l(ad:0x40003C00))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI3_RXCRCR,SPI Rx CRC Register" rgroup.word 0x18++0x01 line.word 0x00 "SPI3_TXCRCR,SPI Tx CRC Register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI3_RXCRCR,SPI Rx CRC Register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI3_TXCRCR,SPI Tx CRC Register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif width 0x0B tree.end tree.end tree "SAI (Serial audio interface)" tree "SAI1" base ad:0x40015400 width 13. sif (!cpuis("STM32L432KC"))&&(!cpuis("STM32L442KC"))&&(!cpuis("STM32L433*"))&&(!cpuis("STM32L443*"))&&(!cpuis("STM32L451*"))&&(!cpuis("STM32L452*"))&&(!cpuis("STM32L462*")) group.long 0x00++0x03 line.long 0x00 "SAI1_GCR,Global Configuration Register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." sif (!cpuis("STM32L4?2*")&&!cpuis("STM32L4?3*")&&!cpuis("STM32L431*")) bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" ",SAI2 sync,?..." endif endif if (((per.l(ad:0x40015404+0x0))&0x10000)==0x0) group.long (0x0+0x04)++0x03 "Serial Audio Interface 1 Block A" line.long 0x00 "SAI1_ACR1,Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " NODIV ,No divider" "Divider ON,Divider OFF" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " OUTDRIV ,Output drive" "When SAIXEN set,Right after set" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32L4?2*")||cpuis("STM32L4?3*")||cpuis("STM32L431*")||cpuis("STM32L451*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." textline " " else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." textline " " endif bitfld.long 0x00 9. " CKSTR ,Clock strobing edge generated/received" "Rising/Falling,Falling/Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB first,LSB first" bitfld.long 0x00 5.--7. " DS ,Data size" ",,8b,10b,16b,20b,24b,32b" bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." textline " " bitfld.long 0x00 0.--1. " MODE ,SAIA audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" else group.long (0x0+0x04)++0x03 "Serial Audio Interface 1 Block A" line.long 0x00 "SAI1_ACR1,Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " NODIV ,No divider" "Divider ON,Divider OFF" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " OUTDRIV ,Output drive" "When SAIXEN set,Right after set" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32L4?2*")||cpuis("STM32L4?3*")||cpuis("STM32L431*")||cpuis("STM32L451*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." textline " " else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." textline " " endif bitfld.long 0x00 9. " CKSTR ,Clock strobing edge generated/received" "Rising/Falling,Falling/Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB first,LSB first" rbitfld.long 0x00 5.--7. " DS ,Data size" ",,8b,10b,16b,20b,24b,32b" rbitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." textline " " rbitfld.long 0x00 0.--1. " MODE ,SAIA audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" endif if (((per.l(ad:0x40015404+0x0))&0x3)==(0x1||0x3))&&(((per.l(ad:0x40015404+0x0))&0x0C)!=0x04) group.long (0x0+0x8)++0x03 line.long 0x00 "SAI1_ACR2,Configuration Register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "None,,Micro-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1,2" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" textline " " bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "No flush,Flush" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full FIFO,?..." elif (((per.l(ad:0x40015404+0x0))&0x3)==(0x0||0x2))&&(((per.l(ad:0x40015404+0x0))&0x0C)!=0x04) group.long (0x0+0x8)++0x03 line.long 0x00 "SAI1_ACR2,Configuration Register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "None,,Micro-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1,2" bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "No flush,Flush" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full FIFO,?..." elif (((per.l(ad:0x40015404+0x0))&0x3)==(0x1||0x3))&&(((per.l(ad:0x40015404+0x0))&0x0C)==0x04) group.long (0x0+0x8)++0x03 line.long 0x00 "SAI1_ACR2,Configuration Register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "None,,Micro-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1,2" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "No flush,Flush" textline " " bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full FIFO,?..." else group.long (0x0+0x8)++0x03 line.long 0x00 "SAI1_ACR2,Configuration Register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "None,,Micro-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1,2" bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "No flush,Flush" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full FIFO,?..." endif if (((per.l(ad:0x40015404+0x0))&0x0C)!=(0x04||0x08)) if (((per.l(ad:0x40015404+0x0))&0x10000)==0x0) group.long (0x0+0xC)++0x07 line.long 0x00 "SAI1_AFRCR,Frame Configuration Register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" textline " " hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI1_ASLOTR,Slot Register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " [14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " [13] ,Slot 13 enable" "Disabled,Enabled" bitfld.long 0x04 28. " [12] ,Slot 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " [11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " [10] ,Slot 10 enable" "Disabled,Enabled" bitfld.long 0x04 25. " [9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " [8] ,Slot 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " [7] ,Slot 7 enable" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " [3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " [1] ,Slot 1 enable" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16b,32b,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long (0x0+0xC)++0x07 line.long 0x00 "SAI1_AFRCR,Frame Configuration Register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" bitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" textline " " hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI1_ASLOTR,Slot Register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " [14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " [13] ,Slot 13 enable" "Disabled,Enabled" bitfld.long 0x04 28. " [12] ,Slot 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " [11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " [10] ,Slot 10 enable" "Disabled,Enabled" bitfld.long 0x04 25. " [9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " [8] ,Slot 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 23. " [7] ,Slot 7 enable" "Disabled,Enabled" bitfld.long 0x04 22. " [6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " [3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " [1] ,Slot 1 enable" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16b,32b,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else hgroup.long (0x0+0xC)++0x07 hide.long 0x00 "SAI1_AFRCR,Frame Configuration Register" hide.long 0x04 "SAI1_ASLOTR,Slot Register" endif group.long (0x0+0x14)++0x03 line.long 0x00 "SAI1_AIM,Interrupt Mask Register 2" bitfld.long 0x00 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " CNRDYIE ,Codec not ready interrupt enable (AC'97)" "Disabled,Enabled" bitfld.long 0x00 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015404+0x0))&0x3)==(0x0||0x2)) if ((per.l((ad:0x40015404+0x0))&0xC)==0x00) rgroup.long (0x0+0x18)++0x03 line.long 0x00 "SAI1_ASR,Status Register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,EmptyCard,Card->Controller" textline " " bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SDMMC_DCTRL,SDMMC Data Control Register" bitfld.long 0x00 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled" bitfld.long 0x00 10. " RWMOD ,Read wait mode" "Stopping SDMMC_D2,Using SDMMC_CK" bitfld.long 0x00 9. " RWSTOP ,Read wait stop" "In progress,Stopped" bitfld.long 0x00 8. " RWSTART ,Read wait stop" "Stopped,Started" textline " " bitfld.long 0x00 4.--7. " DBLOCKSIZE ,Data block size" "1byte,2bytes,4bytes,8bytes,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1024bytes,2048bytes,4096bytes,8192bytes,16384bytes,?..." bitfld.long 0x00 3. " DMAEN ,DMA enable bit" "Disabled,Enabled" bitfld.long 0x00 2. " DTMODE ,Data transfer mode selection" "Block,MultiMediaCard stream" bitfld.long 0x00 1. " DTDIR ,Data transfer direction selection" "Controller->Card,Card->Controller" textline " " bitfld.long 0x00 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled" endif rgroup.long 0x30++0x07 line.long 0x00 "SDMMC_DCOUNT,SDMMC Data Counter Register" hexmask.long 0x00 0.--24. 1. " DATACOUNT ,Data count value" line.long 0x04 "SDMMC_STA,SDMMC Status Register" bitfld.long 0x04 22. " SDIOIT ,SDIO interrupt received" "Not received,Received" bitfld.long 0x04 21. " RXDAVL ,Data available in receive FIFO" "No data,Data available" bitfld.long 0x04 20. " TXDAVL ,Data available in transmit FIFO" "No data,Data available" bitfld.long 0x04 19. " RXFIFOE ,Receive FIFO empty" "Not empty,Empty" textline " " bitfld.long 0x04 18. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty" bitfld.long 0x04 17. " RXFIFOF ,Receive FIFO full" "Not full,Full" bitfld.long 0x04 16. " TXFIFOF ,Transmit FIFO full" "Not full,Full" bitfld.long 0x04 15. " RXFIFOHF ,Receive FIFO half full: there are at least 8 words in the FIFO" "Not half full,Half full" textline " " bitfld.long 0x04 14. " TXFIFOHE ,Transmit FIFO half empty: there are at least 8 words in the FIFO" "Not half empty,Half empty" bitfld.long 0x04 13. " RXACT ,Data receive in progress" "Done,In progress" bitfld.long 0x04 12. " TXACT ,Data transmit in progress" "Done,In progress" bitfld.long 0x04 11. " CMDACT ,Command transfer in progress" "Done,In progress" textline " " bitfld.long 0x04 10. " DBCKEND ,Data block sent/received (CRC check passed)" "Sending/Receiving,Sent/Received" bitfld.long 0x04 8. " DATAEND ,Data end (data counter, SDIDCOUNT, is zero)" "No data end,Data end" bitfld.long 0x04 7. " CMDSENT ,Command sent (no response required)" "Not sent,Sent" bitfld.long 0x04 6. " CMDREND ,Command response received (CRC check passed)" "Not received,Received" textline " " bitfld.long 0x04 5. " RXOVERR ,Received FIFO overrun error" "No error,Error" bitfld.long 0x04 4. " TXUNDERR ,Transmit FIFO underrun error" "No error,Error" bitfld.long 0x04 3. " DTIMEOUT ,Data timeout" "No timeout,Timeout" bitfld.long 0x04 2. " CTIMEOUT ,Command response timeout" "No timeout,Timeout" textline " " bitfld.long 0x04 1. " DCRCFAIL ,Data block sent/received (CRC check failed)" "Sending/Receiving,Sent/Received" bitfld.long 0x04 0. " CCRCFAIL ,Command response received (CRC check failed)" "Not received,Received" group.long 0x38++0x07 line.long 0x00 "SDMMC_ICR,SDMMC Interrupt Clear Register" bitfld.long 0x00 22. " SDIOITC ,SDIOIT flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 10. " DBCKENDC ,DBCKEND flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 8. " DATAENDC ,DATAEND flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 7. " CMDSENTC ,CMDSENT flag clear bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 6. " CMDRENDC ,CMDREND flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 5. " RXOVERRC ,RXOVERR flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 4. " TXUNDERRC ,TXUNDERR flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 3. " DTIMEOUTC ,DTIMEOUT flag clear bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 2. " CTIMEOUTC ,CTIMEOUT flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 1. " DCRCFAILC ,DCRCFAIL flag clear bit" "Not cleared,Cleared" bitfld.long 0x00 0. " CCRCFAILC ,CCRCFAIL flag clear bit" "Not cleared,Cleared" line.long 0x04 "SDMMC_MASK,SDMMC Mask Register" bitfld.long 0x04 22. " SDIOITIE ,SDIO interrupt received interrupt enable" "Disabled,Enabled" bitfld.long 0x04 21. " RXDAVLIE ,Data available in receive FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x04 20. " TXDAVLIE ,Data available in transmit FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x04 19. " RXFIFOEIE ,Receive FIFO empty interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " TXFIFOEIE ,Transmit FIFO empty interrupt enable" "Disabled,Enabled" bitfld.long 0x04 17. " RXFIFOFIE ,Receive FIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x04 16. " TXFIFOFIE ,Transmit FIFO full interrupt enable" "Disabled,Enabled" bitfld.long 0x04 15. " RXFIFOHFIE ,Receive FIFO half full: there are at least 8 words in the FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " TXFIFOHEIE ,Transmit FIFO half empty: there are at least 8 words in the FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x04 13. " RXACTIE ,Data receive in progress interrupt enable" "Disabled,Enabled" bitfld.long 0x04 12. " TXACTIE ,Data transmit in progress interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " CMDACTIE ,Command transfer in progress interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " DBCKENDIE ,Data block sent/received (CRC check passed) interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " DATAENDIE ,Data end (data counter, SDIDCOUNT, is zero) interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " CMDSENTIE ,Command sent (no response required) interrupt enable" "Disabled,Enabled" bitfld.long 0x04 6. " CMDRENDIE ,Command response received (CRC check passed) interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " RXOVERRIE ,Received FIFO overrun error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 4. " TXUNDERRIE ,Transmit FIFO underrun error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 3. " DTIMEOUTIE ,Data timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " CTIMEOUTIE ,Command response timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " DCRCFAILIE ,Data block sent/received (CRC check failed) interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " CCRCFAILIE ,Command response received (CRC check failed) interrupt enable" "Disabled,Enabled" rgroup.long 0x48++0x03 line.long 0x00 "SDMMC_FIFOCNT,SDMMC FIFO Counter Register" hexmask.long.tbyte 0x00 0.--23. 1. " FIFOCOUNT ,Remaining number of words to be written to or read from the FIFO" hgroup.long 0x80++0x03 hide.long 0x00 "SDMMC_FIFO0,SDMMC Data FIFO Register 0" in hgroup.long 0x84++0x03 hide.long 0x00 "SDMMC_FIFO1,SDMMC Data FIFO Register 1" in hgroup.long 0x88++0x03 hide.long 0x00 "SDMMC_FIFO2,SDMMC Data FIFO Register 2" in hgroup.long 0x8C++0x03 hide.long 0x00 "SDMMC_FIFO3,SDMMC Data FIFO Register 3" in hgroup.long 0x90++0x03 hide.long 0x00 "SDMMC_FIFO4,SDMMC Data FIFO Register 4" in hgroup.long 0x94++0x03 hide.long 0x00 "SDMMC_FIFO5,SDMMC Data FIFO Register 5" in hgroup.long 0x98++0x03 hide.long 0x00 "SDMMC_FIFO6,SDMMC Data FIFO Register 6" in hgroup.long 0x9C++0x03 hide.long 0x00 "SDMMC_FIFO7,SDMMC Data FIFO Register 7" in hgroup.long 0xA0++0x03 hide.long 0x00 "SDMMC_FIFO8,SDMMC Data FIFO Register 8" in hgroup.long 0xA4++0x03 hide.long 0x00 "SDMMC_FIFO9,SDMMC Data FIFO Register 9" in hgroup.long 0xA8++0x03 hide.long 0x00 "SDMMC_FIFO10,SDMMC Data FIFO Register 10" in hgroup.long 0xAC++0x03 hide.long 0x00 "SDMMC_FIFO11,SDMMC Data FIFO Register 11" in hgroup.long 0xB0++0x03 hide.long 0x00 "SDMMC_FIFO12,SDMMC Data FIFO Register 12" in hgroup.long 0xB4++0x03 hide.long 0x00 "SDMMC_FIFO13,SDMMC Data FIFO Register 13" in hgroup.long 0xB8++0x03 hide.long 0x00 "SDMMC_FIFO14,SDMMC Data FIFO Register 14" in hgroup.long 0xBC++0x03 hide.long 0x00 "SDMMC_FIFO15,SDMMC Data FIFO Register 15" in hgroup.long 0xC0++0x03 hide.long 0x00 "SDMMC_FIFO16,SDMMC Data FIFO Register 16" in hgroup.long 0xC4++0x03 hide.long 0x00 "SDMMC_FIFO17,SDMMC Data FIFO Register 17" in hgroup.long 0xC8++0x03 hide.long 0x00 "SDMMC_FIFO18,SDMMC Data FIFO Register 18" in hgroup.long 0xCC++0x03 hide.long 0x00 "SDMMC_FIFO19,SDMMC Data FIFO Register 19" in hgroup.long 0xD0++0x03 hide.long 0x00 "SDMMC_FIFO20,SDMMC Data FIFO Register 20" in hgroup.long 0xD4++0x03 hide.long 0x00 "SDMMC_FIFO21,SDMMC Data FIFO Register 21" in hgroup.long 0xD8++0x03 hide.long 0x00 "SDMMC_FIFO22,SDMMC Data FIFO Register 22" in hgroup.long 0xDC++0x03 hide.long 0x00 "SDMMC_FIFO23,SDMMC Data FIFO Register 23" in hgroup.long 0xE0++0x03 hide.long 0x00 "SDMMC_FIFO24,SDMMC Data FIFO Register 24" in hgroup.long 0xE4++0x03 hide.long 0x00 "SDMMC_FIFO25,SDMMC Data FIFO Register 25" in hgroup.long 0xE8++0x03 hide.long 0x00 "SDMMC_FIFO26,SDMMC Data FIFO Register 26" in hgroup.long 0xEC++0x03 hide.long 0x00 "SDMMC_FIFO27,SDMMC Data FIFO Register 27" in hgroup.long 0xF0++0x03 hide.long 0x00 "SDMMC_FIFO28,SDMMC Data FIFO Register 28" in hgroup.long 0xF4++0x03 hide.long 0x00 "SDMMC_FIFO29,SDMMC Data FIFO Register 29" in hgroup.long 0xF8++0x03 hide.long 0x00 "SDMMC_FIFO30,SDMMC Data FIFO Register 30" in hgroup.long 0xFC++0x03 hide.long 0x00 "SDMMC_FIFO31,SDMMC Data FIFO Register 31" in width 0x0B tree.end endif tree "CAN (Controller area network)" base ad:0x40006400 sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) width 11. tree "CAN control and status registers" group.long 0x00++0x1f line.long 0x00 "CAN_MCR,CAN Master Control Register" bitfld.long 0x00 16. " DBF ,Debug freeze" "Working,Frozen" bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "Normal op,Master reset" bitfld.long 0x00 7. " TTCM ,Time triggered communication mode" "Disabled,Enabled" bitfld.long 0x00 6. " ABOM ,Automatic bus-off management" "Soft request,Auto" textline " " bitfld.long 0x00 5. " AWUM ,Automatic wakeup mode" "Soft request,Auto" bitfld.long 0x00 4. " NART ,No automatic retransmission" "Auto retransmit,Transmit once" bitfld.long 0x00 3. " RFLM ,Receive FIFO locked mode" "Not locked,Locked" bitfld.long 0x00 2. " TXFP ,Transmit FIFO priority" "By ID of message,By request order" textline " " bitfld.long 0x00 1. " SLEEP ,Sleep mode request" "No request,Request" bitfld.long 0x00 0. " INRQ ,Initialization request" "Normal,Initialization" line.long 0x04 "CAN_MSR,CAN Master Status Register" rbitfld.long 0x04 11. " RX ,CAN Rx signal" "0,1" rbitfld.long 0x04 10. " SAMP ,Last sample point" "0,1" rbitfld.long 0x04 9. " RXM ,Receive mode" "No effect,Receiver" rbitfld.long 0x04 8. " TXM ,Transmit mode" "No effect,Transmitter" textline " " eventfld.long 0x04 4. " SLAKI ,Sleep acknowledge interrupt" "No interrupt,Interrupt" eventfld.long 0x04 3. " WKUI ,Wakeup interrupt" "No interrupt,Interrupt" eventfld.long 0x04 2. " ERRI ,Error interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " SLAK ,Sleep acknowledge" "No sleep,Sleep" textline " " rbitfld.long 0x04 0. " INAK ,Initialization acknowledge" "No initialization,Initialization" line.long 0x08 "CAN_TSR,CAN Transmit Status Register" rbitfld.long 0x08 31. " LOW2 ,Lowest priority flag for mailbox 2" "0,Lowest" rbitfld.long 0x08 30. " LOW1 ,Lowest priority flag for mailbox 1" "0,Lowest" rbitfld.long 0x08 29. " LOW0 ,Lowest priority flag for mailbox 0" "0,Lowest" rbitfld.long 0x08 28. " TME2 ,Transmit mailbox 2 empty" "Not empty,Empty" textline " " rbitfld.long 0x08 27. " TME1 ,Transmit mailbox 1 empty" "Not empty,Empty" rbitfld.long 0x08 26. " TME0 ,Transmit mailbox 0 empty" "Not empty,Empty" rbitfld.long 0x08 24.--25. " CODE ,Mailbox code" "0,1,2,3" bitfld.long 0x08 23. " ABRQ2 ,Abort request for mailbox 2" "Not requested,Requested" textline " " eventfld.long 0x08 19. " TERR2 ,Transmission error of mailbox 2" "No error,Error" eventfld.long 0x08 18. " ALST2 ,Arbitration lost for mailbox 2" "Not lost,Lost" eventfld.long 0x08 17. " TXOK2 ,Transmission OK of mailbox 2" "Failed,Successful" eventfld.long 0x08 16. " RQCP2 ,Request completed mailbox2" "Not completed,Completed" textline " " bitfld.long 0x08 15. " ABRQ1 ,Abort request for mailbox 1" "Not requested,Requested" eventfld.long 0x08 11. " TERR1 ,Transmission error of mailbox1" "No error,Error" eventfld.long 0x08 10. " ALST1 ,Arbitration lost for mailbox1" "Not lost,Lost" eventfld.long 0x08 9. " TXOK1 ,Transmission OK of mailbox1" "Failed,Successful" textline " " eventfld.long 0x08 8. " RQCP1 ,Request completed mailbox1" "Not completed,Completed" bitfld.long 0x08 7. " ABRQ0 ,Abort request for mailbox 0" "Not requested,Requested" eventfld.long 0x08 3. " TERR0 ,Transmission error of mailbox 0" "No error,Error" eventfld.long 0x08 2. " ALST0 ,Arbitration lost for mailbox 0" "Not lost,Lost" textline " " eventfld.long 0x08 1. " TXOK0 ,Transmission OK of mailbox 0" "Failed,Successful" eventfld.long 0x08 0. " RQCP0 ,Request completed mailbox0" "Not completed,Completed" line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register" bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 output mailbox" "Not released,Released" eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 overrun" "No overrun,Overrun" eventfld.long 0x0C 3. " FULL0 ,FIFO 0 full" "Not full,Full" rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 message pending" "0,1,2,3" line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register" bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 output mailbox" "Not released,Released" eventfld.long 0x10 4. " FOVR1 ,FIFO 1 overrun" "No overrun,Overrun" eventfld.long 0x10 3. " FULL1 ,FIFO 1 full" "Not full,Full" rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 message pending" "0,1,2,3" line.long 0x14 "CAN_IER,CAN Interrupt Enable Register" bitfld.long 0x14 17. " SLKIE ,Sleep interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 16. " WKUIE ,Wakeup interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 15. " ERRIE ,Error interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 11. " LECIE ,Last error code interrupt enable" "Not set,Set" textline " " bitfld.long 0x14 10. " BOFIE ,Bus-off interrupt enable" "Not set,Set" bitfld.long 0x14 9. " EPVIE ,Error passive interrupt enable" "Not set,Set" bitfld.long 0x14 8. " EWGIE ,Error warning interrupt enable" "Not set,Set" bitfld.long 0x14 6. " FOVIE1 ,FIFO overrun interrupt enable" "No interrupt,Interrupt" textline " " bitfld.long 0x14 5. " FFIE1 ,FIFO full interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 4. " FMPIE1 ,FIFO message pending interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 3. " FOVIE0 ,FIFO overrun interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 2. " FFIE0 ,FIFO full interrupt enable" "No interrupt,Interrupt" textline " " bitfld.long 0x14 1. " FMPIE0 ,FIFO message pending interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 0. " TMEIE ,Transmit mailbox empty interrupt enable" "No interrupt,Interrupt" line.long 0x18 "CAN_ESR,CAN Error Status Register" hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive error counter" hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit transmit error counter" bitfld.long 0x18 4.--6. " LEC ,Last error code" "No error,Stuff error,Form error,Acknowledgment error,Bit recessive,Bit dominant,CRC error,Software" rbitfld.long 0x18 2. " BOFF ,Bus-off flag" "No bus-off,Bus-off" textline " " rbitfld.long 0x18 1. " EPVF ,Error passive flag" "No error,Error" rbitfld.long 0x18 0. " EWGF ,Error warning flag" "No error,Error" line.long 0x1C "CAN_BTR,CAN Bit Timing Register" bitfld.long 0x1C 31. " SILM ,Silent mode (debug)" "Normal,Silent" bitfld.long 0x1C 30. " LBKM ,Loop back mode (debug)" "Disabled,Enabled" bitfld.long 0x1C 24.--25. " SJW ,Resynchronization jump width" "0,1,2,3" bitfld.long 0x1C 20.--22. " TS2 ,Time segment 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 16.--19. " TS1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud rate prescaler" tree.end tree "CAN mailbox registers" if (((per.l(ad:0x40006400+0x08))&(1.<<26.))==0x0) if (((per.l(ad:0x40006400+0x180))&0x4)==0x0) rgroup.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" else rgroup.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif rgroup.long (0x180+0x08)++0x07 line.long 0x00 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH0R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else rgroup.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH0R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif else if (((per.l(ad:0x40006400+0x180))&0x4)==0x0) group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" else group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) group.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else group.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif group.long (0x180+0x08)++0x07 line.long 0x00 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH0R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else group.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH0R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif endif if (((per.l(ad:0x40006400+0x08))&(1.<<27.))==0x0) if (((per.l(ad:0x40006400+0x190))&0x4)==0x0) rgroup.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" else rgroup.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) rgroup.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else rgroup.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif rgroup.long (0x190+0x08)++0x07 line.long 0x00 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH1R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else rgroup.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH1R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif else if (((per.l(ad:0x40006400+0x190))&0x4)==0x0) group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" else group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) group.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else group.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif group.long (0x190+0x08)++0x07 line.long 0x00 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH1R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else group.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH1R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif endif if (((per.l(ad:0x40006400+0x08))&(1.<<28.))==0x0) if (((per.l(ad:0x40006400+0x1A0))&0x4)==0x0) rgroup.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" else rgroup.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) rgroup.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else rgroup.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif rgroup.long (0x1A0+0x08)++0x07 line.long 0x00 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH2R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else rgroup.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH2R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif else if (((per.l(ad:0x40006400+0x1A0))&0x4)==0x0) group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" else group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) group.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else group.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif group.long (0x1A0+0x08)++0x07 line.long 0x00 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH2R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else group.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH2R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif endif textline " " if (((per.l(ad:0x40006400+0x1B0))&0x4)==0x0) rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" else rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" endif rgroup.long (0x1B0+0x04)++0x03 line.long 0x00 "CAN_RDT0R,CAN Receive FIFO Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." hgroup.long (0x1B0+0x08)++0x03 hide.long 0x00 "CAN_RDL0R,CAN Receive FIFO Mailbox Data Low Register" in hgroup.long (0x1B0+0x0C)++0x03 hide.long 0x00 "CAN_RDH0R,CAN Receive FIFO Mailbox Data High Register" in if (((per.l(ad:0x40006400+0x1C0))&0x4)==0x0) rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" else rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" endif rgroup.long (0x1C0+0x04)++0x03 line.long 0x00 "CAN_RDT1R,CAN Receive FIFO Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." hgroup.long (0x1C0+0x08)++0x03 hide.long 0x00 "CAN_RDL1R,CAN Receive FIFO Mailbox Data Low Register" in hgroup.long (0x1C0+0x0C)++0x03 hide.long 0x00 "CAN_RDH1R,CAN Receive FIFO Mailbox Data High Register" in tree.end tree "CAN filter registers" group.long 0x200++0x03 line.long 0x00 "CAN_FMR,CAN Filter Master Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 8.--13. " CANSB ,CAN start bank" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,?..." textline " " endif bitfld.long 0x00 0. " FINIT ,Filter initialization mode" "Active filters,Initialization" if (((per.l(ad:0x40006400+0x200))&0x1)==0x1) group.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" sif (cpuis("STM32L4?6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FBM27 ,Filter mode" "Mask,List" bitfld.long 0x00 26. " FBM26 ,Filter mode" "Mask,List" bitfld.long 0x00 25. " FBM25 ,Filter mode" "Mask,List" bitfld.long 0x00 24. " FBM24 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 23. " FBM23 ,Filter mode" "Mask,List" bitfld.long 0x00 22. " FBM22 ,Filter mode" "Mask,List" bitfld.long 0x00 21. " FBM21 ,Filter mode" "Mask,List" bitfld.long 0x00 20. " FBM20 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 19. " FBM19 ,Filter mode" "Mask,List" bitfld.long 0x00 18. " FBM18 ,Filter mode" "Mask,List" bitfld.long 0x00 17. " FBM17 ,Filter mode" "Mask,List" bitfld.long 0x00 16. " FBM16 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 15. " FBM15 ,Filter mode" "Mask,List" bitfld.long 0x00 14. " FBM14 ,Filter mode" "Mask,List" textline " " endif bitfld.long 0x00 13. " FBM13 ,Filter mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter mode" "Mask,List" bitfld.long 0x00 10. " FBM10 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 9. " FBM9 ,Filter mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter mode" "Mask,List" bitfld.long 0x00 7. " FBM7 ,Filter mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 5. " FBM5 ,Filter mode" "Mask,List" bitfld.long 0x00 4. " FBM4 ,Filter mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter mode" "Mask,List" group.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FSC27 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 26. " FSC26 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 25. " FSC25 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 24. " FSC24 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 23. " FSC23 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 22. " FSC22 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 21. " FSC21 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 20. " FSC20 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 19. " FSC19 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 18. " FSC18 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 17. " FSC17 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 16. " FSC16 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 15. " FSC15 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 14. " FSC14 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " endif bitfld.long 0x00 13. " FSC13 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 12. " FSC12 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 11. " FSC11 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 10. " FSC10 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 9. " FSC9 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 8. " FSC8 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 7. " FSC7 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 6. " FSC6 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 5. " FSC5 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 4. " FSC4 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 3. " FSC3 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 2. " FSC2 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 1. " FSC1 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 0. " FSC0 ,Filter scale configuration" "Dual 16b,Single 32b" group.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FFA27 ,Filter FIFO assignment for filter 27" "FIFO 0,FIFO 1" bitfld.long 0x00 26. " FFA26 ,Filter FIFO assignment for filter 26" "FIFO 0,FIFO 1" bitfld.long 0x00 25. " FFA25 ,Filter FIFO assignment for filter 25" "FIFO 0,FIFO 1" bitfld.long 0x00 24. " FFA24 ,Filter FIFO assignment for filter 24" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 23. " FFA23 ,Filter FIFO assignment for filter 23" "FIFO 0,FIFO 1" bitfld.long 0x00 22. " FFA22 ,Filter FIFO assignment for filter 22" "FIFO 0,FIFO 1" bitfld.long 0x00 21. " FFA21 ,Filter FIFO assignment for filter 21" "FIFO 0,FIFO 1" bitfld.long 0x00 20. " FFA20 ,Filter FIFO assignment for filter 20" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 19. " FFA19 ,Filter FIFO assignment for filter 19" "FIFO 0,FIFO 1" bitfld.long 0x00 18. " FFA18 ,Filter FIFO assignment for filter 18" "FIFO 0,FIFO 1" bitfld.long 0x00 17. " FFA17 ,Filter FIFO assignment for filter 17" "FIFO 0,FIFO 1" bitfld.long 0x00 16. " FFA16 ,Filter FIFO assignment for filter 16" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 15. " FFA15 ,Filter FIFO assignment for filter 15" "FIFO 0,FIFO 1" bitfld.long 0x00 14. " FFA14 ,Filter FIFO assignment for filter 14" "FIFO 0,FIFO 1" textline " " endif bitfld.long 0x00 13. " FFA13 ,Filter FIFO assignment for filter 13" "FIFO 0,FIFO 1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO assignment for filter 12" "FIFO 0,FIFO 1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO assignment for filter 11" "FIFO 0,FIFO 1" bitfld.long 0x00 10. " FFA10 ,Filter FIFO assignment for filter 10" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 9. " FFA9 ,Filter FIFO assignment for filter 9" "FIFO 0,FIFO 1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO assignment for filter 8" "FIFO 0,FIFO 1" bitfld.long 0x00 7. " FFA7 ,Filter FIFO assignment for filter 7" "FIFO 0,FIFO 1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO assignment for filter 6" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 5. " FFA5 ,Filter FIFO assignment for filter 5" "FIFO 0,FIFO 1" bitfld.long 0x00 4. " FFA4 ,Filter FIFO assignment for filter 4" "FIFO 0,FIFO 1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO assignment for filter 3" "FIFO 0,FIFO 1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO assignment for filter 2" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO assignment for filter 1" "FIFO 0,FIFO 1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO assignment for filter 0" "FIFO 0,FIFO 1" else rgroup.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FBM27 ,Filter mode" "Mask,List" bitfld.long 0x00 26. " FBM26 ,Filter mode" "Mask,List" bitfld.long 0x00 25. " FBM25 ,Filter mode" "Mask,List" bitfld.long 0x00 24. " FBM24 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 23. " FBM23 ,Filter mode" "Mask,List" bitfld.long 0x00 22. " FBM22 ,Filter mode" "Mask,List" bitfld.long 0x00 21. " FBM21 ,Filter mode" "Mask,List" bitfld.long 0x00 20. " FBM20 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 19. " FBM19 ,Filter mode" "Mask,List" bitfld.long 0x00 18. " FBM18 ,Filter mode" "Mask,List" bitfld.long 0x00 17. " FBM17 ,Filter mode" "Mask,List" bitfld.long 0x00 16. " FBM16 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 15. " FBM15 ,Filter mode" "Mask,List" bitfld.long 0x00 14. " FBM14 ,Filter mode" "Mask,List" textline " " endif bitfld.long 0x00 13. " FBM13 ,Filter mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter mode" "Mask,List" bitfld.long 0x00 10. " FBM10 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 9. " FBM9 ,Filter mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter mode" "Mask,List" bitfld.long 0x00 7. " FBM7 ,Filter mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 5. " FBM5 ,Filter mode" "Mask,List" bitfld.long 0x00 4. " FBM4 ,Filter mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter mode" "Mask,List" rgroup.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FSC27 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 26. " FSC26 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 25. " FSC25 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 24. " FSC24 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 23. " FSC23 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 22. " FSC22 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 21. " FSC21 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 20. " FSC20 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 19. " FSC19 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 18. " FSC18 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 17. " FSC17 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 16. " FSC16 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 15. " FSC15 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 14. " FSC14 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " endif bitfld.long 0x00 13. " FSC13 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 12. " FSC12 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 11. " FSC11 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 10. " FSC10 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 9. " FSC9 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 8. " FSC8 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 7. " FSC7 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 6. " FSC6 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 5. " FSC5 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 4. " FSC4 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 3. " FSC3 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 2. " FSC2 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 1. " FSC1 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 0. " FSC0 ,Filter scale configuration" "Dual 16b,Single 32b" rgroup.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FFA27 ,Filter FIFO assignment for filter 27" "FIFO 0,FIFO 1" bitfld.long 0x00 26. " FFA26 ,Filter FIFO assignment for filter 26" "FIFO 0,FIFO 1" bitfld.long 0x00 25. " FFA25 ,Filter FIFO assignment for filter 25" "FIFO 0,FIFO 1" bitfld.long 0x00 24. " FFA24 ,Filter FIFO assignment for filter 24" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 23. " FFA23 ,Filter FIFO assignment for filter 23" "FIFO 0,FIFO 1" bitfld.long 0x00 22. " FFA22 ,Filter FIFO assignment for filter 22" "FIFO 0,FIFO 1" bitfld.long 0x00 21. " FFA21 ,Filter FIFO assignment for filter 21" "FIFO 0,FIFO 1" bitfld.long 0x00 20. " FFA20 ,Filter FIFO assignment for filter 20" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 19. " FFA19 ,Filter FIFO assignment for filter 19" "FIFO 0,FIFO 1" bitfld.long 0x00 18. " FFA18 ,Filter FIFO assignment for filter 18" "FIFO 0,FIFO 1" bitfld.long 0x00 17. " FFA17 ,Filter FIFO assignment for filter 17" "FIFO 0,FIFO 1" bitfld.long 0x00 16. " FFA16 ,Filter FIFO assignment for filter 16" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 15. " FFA15 ,Filter FIFO assignment for filter 15" "FIFO 0,FIFO 1" bitfld.long 0x00 14. " FFA14 ,Filter FIFO assignment for filter 14" "FIFO 0,FIFO 1" textline " " endif bitfld.long 0x00 13. " FFA13 ,Filter FIFO assignment for filter 13" "FIFO 0,FIFO 1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO assignment for filter 12" "FIFO 0,FIFO 1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO assignment for filter 11" "FIFO 0,FIFO 1" bitfld.long 0x00 10. " FFA10 ,Filter FIFO assignment for filter 10" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 9. " FFA9 ,Filter FIFO assignment for filter 9" "FIFO 0,FIFO 1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO assignment for filter 8" "FIFO 0,FIFO 1" bitfld.long 0x00 7. " FFA7 ,Filter FIFO assignment for filter 7" "FIFO 0,FIFO 1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO assignment for filter 6" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 5. " FFA5 ,Filter FIFO assignment for filter 5" "FIFO 0,FIFO 1" bitfld.long 0x00 4. " FFA4 ,Filter FIFO assignment for filter 4" "FIFO 0,FIFO 1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO assignment for filter 3" "FIFO 0,FIFO 1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO assignment for filter 2" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO assignment for filter 1" "FIFO 0,FIFO 1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO assignment for filter 0" "FIFO 0,FIFO 1" endif group.long 0x21C++0x03 line.long 0x00 "CAN_FA1R,CAN Filter Activation Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FACT27 ,Filter active" "Not active,Active" bitfld.long 0x00 26. " FACT26 ,Filter active" "Not active,Active" bitfld.long 0x00 25. " FACT25 ,Filter active" "Not active,Active" bitfld.long 0x00 24. " FACT24 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 23. " FACT23 ,Filter active" "Not active,Active" bitfld.long 0x00 22. " FACT22 ,Filter active" "Not active,Active" bitfld.long 0x00 21. " FACT21 ,Filter active" "Not active,Active" bitfld.long 0x00 20. " FACT20 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 19. " FACT19 ,Filter active" "Not active,Active" bitfld.long 0x00 18. " FACT18 ,Filter active" "Not active,Active" bitfld.long 0x00 17. " FACT17 ,Filter active" "Not active,Active" bitfld.long 0x00 16. " FACT16 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 15. " FACT15 ,Filter active" "Not active,Active" bitfld.long 0x00 14. " FACT14 ,Filter active" "Not active,Active" textline " " endif bitfld.long 0x00 13. " FACT13 ,Filter active" "Not active,Active" bitfld.long 0x00 12. " FACT12 ,Filter active" "Not active,Active" bitfld.long 0x00 11. " FACT11 ,Filter active" "Not active,Active" bitfld.long 0x00 10. " FACT10 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 9. " FACT9 ,Filter active" "Not active,Active" bitfld.long 0x00 8. " FACT8 ,Filter active" "Not active,Active" bitfld.long 0x00 7. " FACT7 ,Filter active" "Not active,Active" bitfld.long 0x00 6. " FACT6 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 5. " FACT5 ,Filter active" "Not active,Active" bitfld.long 0x00 4. " FACT4 ,Filter active" "Not active,Active" bitfld.long 0x00 3. " FACT3 ,Filter active" "Not active,Active" bitfld.long 0x00 2. " FACT2 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 1. " FACT1 ,Filter active" "Not active,Active" bitfld.long 0x00 0. " FACT0 ,Filter active" "Not active,Active" textline " " if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<0.))==0x0)) group.long 0x240++0x07 line.long 0x00 "CAN_F0R1,Filter Bank 0 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F0R2,Filter bank 0 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x240++0x07 line.long 0x00 "CAN_F0R1,Filter Bank 0 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F0R2,Filter bank 0 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<1.))==0x0)) group.long 0x248++0x07 line.long 0x00 "CAN_F1R1,Filter Bank 1 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F1R2,Filter bank 1 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x248++0x07 line.long 0x00 "CAN_F1R1,Filter Bank 1 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F1R2,Filter bank 1 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<2.))==0x0)) group.long 0x250++0x07 line.long 0x00 "CAN_F2R1,Filter Bank 2 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F2R2,Filter bank 2 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x250++0x07 line.long 0x00 "CAN_F2R1,Filter Bank 2 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F2R2,Filter bank 2 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<3.))==0x0)) group.long 0x258++0x07 line.long 0x00 "CAN_F3R1,Filter Bank 3 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F3R2,Filter bank 3 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x258++0x07 line.long 0x00 "CAN_F3R1,Filter Bank 3 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F3R2,Filter bank 3 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<4.))==0x0)) group.long 0x260++0x07 line.long 0x00 "CAN_F4R1,Filter Bank 4 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F4R2,Filter bank 4 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x260++0x07 line.long 0x00 "CAN_F4R1,Filter Bank 4 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F4R2,Filter bank 4 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<5.))==0x0)) group.long 0x268++0x07 line.long 0x00 "CAN_F5R1,Filter Bank 5 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F5R2,Filter bank 5 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x268++0x07 line.long 0x00 "CAN_F5R1,Filter Bank 5 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F5R2,Filter bank 5 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<6.))==0x0)) group.long 0x270++0x07 line.long 0x00 "CAN_F6R1,Filter Bank 6 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F6R2,Filter bank 6 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x270++0x07 line.long 0x00 "CAN_F6R1,Filter Bank 6 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F6R2,Filter bank 6 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<7.))==0x0)) group.long 0x278++0x07 line.long 0x00 "CAN_F7R1,Filter Bank 7 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F7R2,Filter bank 7 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x278++0x07 line.long 0x00 "CAN_F7R1,Filter Bank 7 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F7R2,Filter bank 7 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<8.))==0x0)) group.long 0x280++0x07 line.long 0x00 "CAN_F8R1,Filter Bank 8 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F8R2,Filter bank 8 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x280++0x07 line.long 0x00 "CAN_F8R1,Filter Bank 8 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F8R2,Filter bank 8 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<9.))==0x0)) group.long 0x288++0x07 line.long 0x00 "CAN_F9R1,Filter Bank 9 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F9R2,Filter bank 9 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x288++0x07 line.long 0x00 "CAN_F9R1,Filter Bank 9 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F9R2,Filter bank 9 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<10.))==0x0)) group.long 0x290++0x07 line.long 0x00 "CAN_F10R1,Filter Bank 10 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F10R2,Filter bank 10 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x290++0x07 line.long 0x00 "CAN_F10R1,Filter Bank 10 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F10R2,Filter bank 10 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<11.))==0x0)) group.long 0x298++0x07 line.long 0x00 "CAN_F11R1,Filter Bank 11 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F11R2,Filter bank 11 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x298++0x07 line.long 0x00 "CAN_F11R1,Filter Bank 11 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F11R2,Filter bank 11 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<12.))==0x0)) group.long 0x2A0++0x07 line.long 0x00 "CAN_F12R1,Filter Bank 12 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F12R2,Filter bank 12 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2A0++0x07 line.long 0x00 "CAN_F12R1,Filter Bank 12 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F12R2,Filter bank 12 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<13.))==0x0)) group.long 0x2A8++0x07 line.long 0x00 "CAN_F13R1,Filter Bank 13 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F13R2,Filter bank 13 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2A8++0x07 line.long 0x00 "CAN_F13R1,Filter Bank 13 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F13R2,Filter bank 13 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<14.))==0x0)) group.long 0x2B0++0x07 line.long 0x00 "CAN_F14R1,Filter Bank 14 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F14R2,Filter bank 14 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2B0++0x07 line.long 0x00 "CAN_F14R1,Filter Bank 14 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F14R2,Filter bank 14 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<15.))==0x0)) group.long 0x2B8++0x07 line.long 0x00 "CAN_F15R1,Filter Bank 15 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F15R2,Filter bank 15 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2B8++0x07 line.long 0x00 "CAN_F15R1,Filter Bank 15 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F15R2,Filter bank 15 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<16.))==0x0)) group.long 0x2C0++0x07 line.long 0x00 "CAN_F16R1,Filter Bank 16 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F16R2,Filter bank 16 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2C0++0x07 line.long 0x00 "CAN_F16R1,Filter Bank 16 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F16R2,Filter bank 16 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<17.))==0x0)) group.long 0x2C8++0x07 line.long 0x00 "CAN_F17R1,Filter Bank 17 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F17R2,Filter bank 17 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2C8++0x07 line.long 0x00 "CAN_F17R1,Filter Bank 17 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F17R2,Filter bank 17 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<18.))==0x0)) group.long 0x2D0++0x07 line.long 0x00 "CAN_F18R1,Filter Bank 18 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F18R2,Filter bank 18 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2D0++0x07 line.long 0x00 "CAN_F18R1,Filter Bank 18 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F18R2,Filter bank 18 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<19.))==0x0)) group.long 0x2D8++0x07 line.long 0x00 "CAN_F19R1,Filter Bank 19 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F19R2,Filter bank 19 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2D8++0x07 line.long 0x00 "CAN_F19R1,Filter Bank 19 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F19R2,Filter bank 19 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<20.))==0x0)) group.long 0x2E0++0x07 line.long 0x00 "CAN_F20R1,Filter Bank 20 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F20R2,Filter bank 20 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2E0++0x07 line.long 0x00 "CAN_F20R1,Filter Bank 20 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F20R2,Filter bank 20 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<21.))==0x0)) group.long 0x2E8++0x07 line.long 0x00 "CAN_F21R1,Filter Bank 21 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F21R2,Filter bank 21 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2E8++0x07 line.long 0x00 "CAN_F21R1,Filter Bank 21 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F21R2,Filter bank 21 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<22.))==0x0)) group.long 0x2F0++0x07 line.long 0x00 "CAN_F22R1,Filter Bank 22 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F22R2,Filter bank 22 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2F0++0x07 line.long 0x00 "CAN_F22R1,Filter Bank 22 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F22R2,Filter bank 22 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<23.))==0x0)) group.long 0x2F8++0x07 line.long 0x00 "CAN_F23R1,Filter Bank 23 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F23R2,Filter bank 23 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2F8++0x07 line.long 0x00 "CAN_F23R1,Filter Bank 23 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F23R2,Filter bank 23 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<24.))==0x0)) group.long 0x300++0x07 line.long 0x00 "CAN_F24R1,Filter Bank 24 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F24R2,Filter bank 24 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x300++0x07 line.long 0x00 "CAN_F24R1,Filter Bank 24 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F24R2,Filter bank 24 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<25.))==0x0)) group.long 0x308++0x07 line.long 0x00 "CAN_F25R1,Filter Bank 25 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F25R2,Filter bank 25 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x308++0x07 line.long 0x00 "CAN_F25R1,Filter Bank 25 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F25R2,Filter bank 25 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<26.))==0x0)) group.long 0x310++0x07 line.long 0x00 "CAN_F26R1,Filter Bank 26 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F26R2,Filter bank 26 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x310++0x07 line.long 0x00 "CAN_F26R1,Filter Bank 26 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F26R2,Filter bank 26 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<27.))==0x0)) group.long 0x318++0x07 line.long 0x00 "CAN_F27R1,Filter Bank 27 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F27R2,Filter bank 27 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x318++0x07 line.long 0x00 "CAN_F27R1,Filter Bank 27 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F27R2,Filter bank 27 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif tree.end width 0x0B else width 11. tree "CAN control and status registers" group.long 0x00++0x1f line.long 0x00 "CAN_MCR,CAN Master Control Register" bitfld.long 0x00 16. " DBF ,Debug freeze" "Working,Frozen" bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "Normal op,Master reset" bitfld.long 0x00 7. " TTCM ,Time triggered communication mode" "Disabled,Enabled" bitfld.long 0x00 6. " ABOM ,Automatic bus-off management" "Soft request,Auto" textline " " bitfld.long 0x00 5. " AWUM ,Automatic wakeup mode" "Soft request,Auto" bitfld.long 0x00 4. " NART ,No automatic retransmission" "Auto retransmit,Transmit once" bitfld.long 0x00 3. " RFLM ,Receive FIFO locked mode" "Not locked,Locked" bitfld.long 0x00 2. " TXFP ,Transmit FIFO priority" "By ID of message,By request order" textline " " bitfld.long 0x00 1. " SLEEP ,Sleep mode request" "No request,Request" bitfld.long 0x00 0. " INRQ ,Initialization request" "Normal,Initialization" line.long 0x04 "CAN_MSR,CAN Master Status Register" rbitfld.long 0x04 11. " RX ,CAN Rx signal" "0,1" rbitfld.long 0x04 10. " SAMP ,Last sample point" "0,1" rbitfld.long 0x04 9. " RXM ,Receive mode" "No effect,Receiver" rbitfld.long 0x04 8. " TXM ,Transmit mode" "No effect,Transmitter" textline " " eventfld.long 0x04 4. " SLAKI ,Sleep acknowledge interrupt" "No interrupt,Interrupt" eventfld.long 0x04 3. " WKUI ,Wakeup interrupt" "No interrupt,Interrupt" eventfld.long 0x04 2. " ERRI ,Error interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " SLAK ,Sleep acknowledge" "No sleep,Sleep" textline " " rbitfld.long 0x04 0. " INAK ,Initialization acknowledge" "No initialization,Initialization" line.long 0x08 "CAN_TSR,CAN Transmit Status Register" rbitfld.long 0x08 31. " LOW2 ,Lowest priority flag for mailbox 2" "0,Lowest" rbitfld.long 0x08 30. " LOW1 ,Lowest priority flag for mailbox 1" "0,Lowest" rbitfld.long 0x08 29. " LOW0 ,Lowest priority flag for mailbox 0" "0,Lowest" rbitfld.long 0x08 28. " TME2 ,Transmit mailbox 2 empty" "Not empty,Empty" textline " " rbitfld.long 0x08 27. " TME1 ,Transmit mailbox 1 empty" "Not empty,Empty" rbitfld.long 0x08 26. " TME0 ,Transmit mailbox 0 empty" "Not empty,Empty" rbitfld.long 0x08 24.--25. " CODE ,Mailbox code" "0,1,2,3" bitfld.long 0x08 23. " ABRQ2 ,Abort request for mailbox 2" "Not requested,Requested" textline " " eventfld.long 0x08 19. " TERR2 ,Transmission error of mailbox 2" "No error,Error" eventfld.long 0x08 18. " ALST2 ,Arbitration lost for mailbox 2" "Not lost,Lost" eventfld.long 0x08 17. " TXOK2 ,Transmission OK of mailbox 2" "Failed,Successful" eventfld.long 0x08 16. " RQCP2 ,Request completed mailbox2" "Not completed,Completed" textline " " bitfld.long 0x08 15. " ABRQ1 ,Abort request for mailbox 1" "Not requested,Requested" eventfld.long 0x08 11. " TERR1 ,Transmission error of mailbox1" "No error,Error" eventfld.long 0x08 10. " ALST1 ,Arbitration lost for mailbox1" "Not lost,Lost" eventfld.long 0x08 9. " TXOK1 ,Transmission OK of mailbox1" "Failed,Successful" textline " " eventfld.long 0x08 8. " RQCP1 ,Request completed mailbox1" "Not completed,Completed" bitfld.long 0x08 7. " ABRQ0 ,Abort request for mailbox 0" "Not requested,Requested" eventfld.long 0x08 3. " TERR0 ,Transmission error of mailbox 0" "No error,Error" eventfld.long 0x08 2. " ALST0 ,Arbitration lost for mailbox 0" "Not lost,Lost" textline " " eventfld.long 0x08 1. " TXOK0 ,Transmission OK of mailbox 0" "Failed,Successful" eventfld.long 0x08 0. " RQCP0 ,Request completed mailbox0" "Not completed,Completed" line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register" bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 output mailbox" "Not released,Released" eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 overrun" "No overrun,Overrun" eventfld.long 0x0C 3. " FULL0 ,FIFO 0 full" "Not full,Full" rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 message pending" "0,1,2,3" line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register" bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 output mailbox" "Not released,Released" eventfld.long 0x10 4. " FOVR1 ,FIFO 1 overrun" "No overrun,Overrun" eventfld.long 0x10 3. " FULL1 ,FIFO 1 full" "Not full,Full" rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 message pending" "0,1,2,3" line.long 0x14 "CAN_IER,CAN Interrupt Enable Register" bitfld.long 0x14 17. " SLKIE ,Sleep interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 16. " WKUIE ,Wakeup interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 15. " ERRIE ,Error interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 11. " LECIE ,Last error code interrupt enable" "Not set,Set" textline " " bitfld.long 0x14 10. " BOFIE ,Bus-off interrupt enable" "Not set,Set" bitfld.long 0x14 9. " EPVIE ,Error passive interrupt enable" "Not set,Set" bitfld.long 0x14 8. " EWGIE ,Error warning interrupt enable" "Not set,Set" bitfld.long 0x14 6. " FOVIE1 ,FIFO overrun interrupt enable" "No interrupt,Interrupt" textline " " bitfld.long 0x14 5. " FFIE1 ,FIFO full interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 4. " FMPIE1 ,FIFO message pending interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 3. " FOVIE0 ,FIFO overrun interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 2. " FFIE0 ,FIFO full interrupt enable" "No interrupt,Interrupt" textline " " bitfld.long 0x14 1. " FMPIE0 ,FIFO message pending interrupt enable" "No interrupt,Interrupt" bitfld.long 0x14 0. " TMEIE ,Transmit mailbox empty interrupt enable" "No interrupt,Interrupt" line.long 0x18 "CAN_ESR,CAN Error Status Register" hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive error counter" hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit transmit error counter" bitfld.long 0x18 4.--6. " LEC ,Last error code" "No error,Stuff error,Form error,Acknowledgment error,Bit recessive,Bit dominant,CRC error,Software" rbitfld.long 0x18 2. " BOFF ,Bus-off flag" "No bus-off,Bus-off" textline " " rbitfld.long 0x18 1. " EPVF ,Error passive flag" "No error,Error" rbitfld.long 0x18 0. " EWGF ,Error warning flag" "No error,Error" line.long 0x1C "CAN_BTR,CAN Bit Timing Register" bitfld.long 0x1C 31. " SILM ,Silent mode (debug)" "Normal,Silent" bitfld.long 0x1C 30. " LBKM ,Loop back mode (debug)" "Disabled,Enabled" bitfld.long 0x1C 24.--25. " SJW ,Resynchronization jump width" "0,1,2,3" bitfld.long 0x1C 20.--22. " TS2 ,Time segment 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 16.--19. " TS1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud rate prescaler" tree.end tree "CAN mailbox registers" if (((per.l(ad:0x40006400+0x08))&(1.<<26.))==0x0) if (((per.l(ad:0x40006400+0x180))&0x4)==0x0) rgroup.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" else rgroup.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else rgroup.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif rgroup.long (0x180+0x08)++0x07 line.long 0x00 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH0R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else rgroup.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH0R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif else if (((per.l(ad:0x40006400+0x180))&0x4)==0x0) group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" else group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) group.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else group.long (0x180+0x04)++0x03 line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif group.long (0x180+0x08)++0x07 line.long 0x00 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH0R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else group.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH0R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif endif if (((per.l(ad:0x40006400+0x08))&(1.<<27.))==0x0) if (((per.l(ad:0x40006400+0x190))&0x4)==0x0) rgroup.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" else rgroup.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) rgroup.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else rgroup.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif rgroup.long (0x190+0x08)++0x07 line.long 0x00 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH1R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else rgroup.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH1R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif else if (((per.l(ad:0x40006400+0x190))&0x4)==0x0) group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" else group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) group.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else group.long (0x190+0x04)++0x03 line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif group.long (0x190+0x08)++0x07 line.long 0x00 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH1R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else group.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH1R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif endif if (((per.l(ad:0x40006400+0x08))&(1.<<28.))==0x0) if (((per.l(ad:0x40006400+0x1A0))&0x4)==0x0) rgroup.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" else rgroup.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "Not requested,Requested" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) rgroup.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else rgroup.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif rgroup.long (0x1A0+0x08)++0x07 line.long 0x00 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH2R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else rgroup.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH2R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif else if (((per.l(ad:0x40006400+0x1A0))&0x4)==0x0) group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" textline " " bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" else group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,CAN TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" bitfld.long 0x00 0. " TXRQ ,Transmit mailbox request" "No request,Request" endif sif (cpuis("STM32L496*")||cpuis("STM32L4A6*")||cpuis("STM32L432*")||cpuis("STM32L433*")||cpuis("STM32L442*")||cpuis("STM32L443*")||cpuis("STM32L471*")||cpuis("STM32L475*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*")) if (((per.l(ad:0x40006400+0x00)&0x80)==0x80)) group.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." else group.long (0x1A0+0x04)++0x03 line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." endif group.long (0x1A0+0x08)++0x07 line.long 0x00 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x00 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x00 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x04 "CAN_TDH2R,CAN Mailbox Data High Register" hexmask.long.byte 0x04 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x04 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x04 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x04 0.--7. 1. " DATA4 ,Data byte 4" else group.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,CAN Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" bitfld.long 0x00 8. " TGT ,Transmit global time" "Not sent,Sent" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,CAN Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data byte 0" line.long 0x08 "CAN_TDH2R,CAN mailbox data high register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data byte 4" endif endif textline " " if (((per.l(ad:0x40006400+0x1B0))&0x4)==0x0) rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" else rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" endif rgroup.long (0x1B0+0x04)++0x03 line.long 0x00 "CAN_RDT0R,CAN Receive FIFO Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." hgroup.long (0x1B0+0x08)++0x03 hide.long 0x00 "CAN_RDL0R,CAN Receive FIFO Mailbox Data Low Register" in hgroup.long (0x1B0+0x0C)++0x03 hide.long 0x00 "CAN_RDH0R,CAN Receive FIFO Mailbox Data High Register" in if (((per.l(ad:0x40006400+0x1C0))&0x4)==0x0) rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard identifier or extended identifier" hexmask.long.tbyte 0x00 3.--20. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" else rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,CAN Receive FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended identifier" bitfld.long 0x00 2. " IDE ,Identifier extension" "Standard,Extended" bitfld.long 0x00 1. " RTR ,Remote transmission request" "Data frame,Remote frame" endif rgroup.long (0x1C0+0x04)++0x03 line.long 0x00 "CAN_RDT1R,CAN Receive FIFO Mailbox Data Length Control and Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message time stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter match index" bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,?..." hgroup.long (0x1C0+0x08)++0x03 hide.long 0x00 "CAN_RDL1R,CAN Receive FIFO Mailbox Data Low Register" in hgroup.long (0x1C0+0x0C)++0x03 hide.long 0x00 "CAN_RDH1R,CAN Receive FIFO Mailbox Data High Register" in tree.end tree "CAN filter registers" group.long 0x200++0x03 line.long 0x00 "CAN_FMR,CAN Filter Master Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 8.--13. " CANSB ,CAN start bank" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,?..." textline " " endif bitfld.long 0x00 0. " FINIT ,Filter initialization mode" "Active filters,Initialization" if (((per.l(ad:0x40006400+0x200))&0x1)==0x1) group.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" sif (cpuis("STM32L4?6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FBM27 ,Filter mode" "Mask,List" bitfld.long 0x00 26. " FBM26 ,Filter mode" "Mask,List" bitfld.long 0x00 25. " FBM25 ,Filter mode" "Mask,List" bitfld.long 0x00 24. " FBM24 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 23. " FBM23 ,Filter mode" "Mask,List" bitfld.long 0x00 22. " FBM22 ,Filter mode" "Mask,List" bitfld.long 0x00 21. " FBM21 ,Filter mode" "Mask,List" bitfld.long 0x00 20. " FBM20 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 19. " FBM19 ,Filter mode" "Mask,List" bitfld.long 0x00 18. " FBM18 ,Filter mode" "Mask,List" bitfld.long 0x00 17. " FBM17 ,Filter mode" "Mask,List" bitfld.long 0x00 16. " FBM16 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 15. " FBM15 ,Filter mode" "Mask,List" bitfld.long 0x00 14. " FBM14 ,Filter mode" "Mask,List" textline " " endif bitfld.long 0x00 13. " FBM13 ,Filter mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter mode" "Mask,List" bitfld.long 0x00 10. " FBM10 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 9. " FBM9 ,Filter mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter mode" "Mask,List" bitfld.long 0x00 7. " FBM7 ,Filter mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 5. " FBM5 ,Filter mode" "Mask,List" bitfld.long 0x00 4. " FBM4 ,Filter mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter mode" "Mask,List" group.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FSC27 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 26. " FSC26 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 25. " FSC25 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 24. " FSC24 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 23. " FSC23 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 22. " FSC22 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 21. " FSC21 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 20. " FSC20 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 19. " FSC19 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 18. " FSC18 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 17. " FSC17 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 16. " FSC16 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 15. " FSC15 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 14. " FSC14 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " endif bitfld.long 0x00 13. " FSC13 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 12. " FSC12 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 11. " FSC11 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 10. " FSC10 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 9. " FSC9 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 8. " FSC8 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 7. " FSC7 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 6. " FSC6 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 5. " FSC5 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 4. " FSC4 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 3. " FSC3 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 2. " FSC2 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 1. " FSC1 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 0. " FSC0 ,Filter scale configuration" "Dual 16b,Single 32b" group.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FFA27 ,Filter FIFO assignment for filter 27" "FIFO 0,FIFO 1" bitfld.long 0x00 26. " FFA26 ,Filter FIFO assignment for filter 26" "FIFO 0,FIFO 1" bitfld.long 0x00 25. " FFA25 ,Filter FIFO assignment for filter 25" "FIFO 0,FIFO 1" bitfld.long 0x00 24. " FFA24 ,Filter FIFO assignment for filter 24" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 23. " FFA23 ,Filter FIFO assignment for filter 23" "FIFO 0,FIFO 1" bitfld.long 0x00 22. " FFA22 ,Filter FIFO assignment for filter 22" "FIFO 0,FIFO 1" bitfld.long 0x00 21. " FFA21 ,Filter FIFO assignment for filter 21" "FIFO 0,FIFO 1" bitfld.long 0x00 20. " FFA20 ,Filter FIFO assignment for filter 20" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 19. " FFA19 ,Filter FIFO assignment for filter 19" "FIFO 0,FIFO 1" bitfld.long 0x00 18. " FFA18 ,Filter FIFO assignment for filter 18" "FIFO 0,FIFO 1" bitfld.long 0x00 17. " FFA17 ,Filter FIFO assignment for filter 17" "FIFO 0,FIFO 1" bitfld.long 0x00 16. " FFA16 ,Filter FIFO assignment for filter 16" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 15. " FFA15 ,Filter FIFO assignment for filter 15" "FIFO 0,FIFO 1" bitfld.long 0x00 14. " FFA14 ,Filter FIFO assignment for filter 14" "FIFO 0,FIFO 1" textline " " endif bitfld.long 0x00 13. " FFA13 ,Filter FIFO assignment for filter 13" "FIFO 0,FIFO 1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO assignment for filter 12" "FIFO 0,FIFO 1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO assignment for filter 11" "FIFO 0,FIFO 1" bitfld.long 0x00 10. " FFA10 ,Filter FIFO assignment for filter 10" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 9. " FFA9 ,Filter FIFO assignment for filter 9" "FIFO 0,FIFO 1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO assignment for filter 8" "FIFO 0,FIFO 1" bitfld.long 0x00 7. " FFA7 ,Filter FIFO assignment for filter 7" "FIFO 0,FIFO 1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO assignment for filter 6" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 5. " FFA5 ,Filter FIFO assignment for filter 5" "FIFO 0,FIFO 1" bitfld.long 0x00 4. " FFA4 ,Filter FIFO assignment for filter 4" "FIFO 0,FIFO 1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO assignment for filter 3" "FIFO 0,FIFO 1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO assignment for filter 2" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO assignment for filter 1" "FIFO 0,FIFO 1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO assignment for filter 0" "FIFO 0,FIFO 1" else rgroup.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FBM27 ,Filter mode" "Mask,List" bitfld.long 0x00 26. " FBM26 ,Filter mode" "Mask,List" bitfld.long 0x00 25. " FBM25 ,Filter mode" "Mask,List" bitfld.long 0x00 24. " FBM24 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 23. " FBM23 ,Filter mode" "Mask,List" bitfld.long 0x00 22. " FBM22 ,Filter mode" "Mask,List" bitfld.long 0x00 21. " FBM21 ,Filter mode" "Mask,List" bitfld.long 0x00 20. " FBM20 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 19. " FBM19 ,Filter mode" "Mask,List" bitfld.long 0x00 18. " FBM18 ,Filter mode" "Mask,List" bitfld.long 0x00 17. " FBM17 ,Filter mode" "Mask,List" bitfld.long 0x00 16. " FBM16 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 15. " FBM15 ,Filter mode" "Mask,List" bitfld.long 0x00 14. " FBM14 ,Filter mode" "Mask,List" textline " " endif bitfld.long 0x00 13. " FBM13 ,Filter mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter mode" "Mask,List" bitfld.long 0x00 10. " FBM10 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 9. " FBM9 ,Filter mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter mode" "Mask,List" bitfld.long 0x00 7. " FBM7 ,Filter mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 5. " FBM5 ,Filter mode" "Mask,List" bitfld.long 0x00 4. " FBM4 ,Filter mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter mode" "Mask,List" rgroup.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FSC27 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 26. " FSC26 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 25. " FSC25 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 24. " FSC24 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 23. " FSC23 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 22. " FSC22 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 21. " FSC21 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 20. " FSC20 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 19. " FSC19 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 18. " FSC18 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 17. " FSC17 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 16. " FSC16 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 15. " FSC15 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 14. " FSC14 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " endif bitfld.long 0x00 13. " FSC13 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 12. " FSC12 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 11. " FSC11 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 10. " FSC10 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 9. " FSC9 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 8. " FSC8 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 7. " FSC7 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 6. " FSC6 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 5. " FSC5 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 4. " FSC4 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 3. " FSC3 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 2. " FSC2 ,Filter scale configuration" "Dual 16b,Single 32b" textline " " bitfld.long 0x00 1. " FSC1 ,Filter scale configuration" "Dual 16b,Single 32b" bitfld.long 0x00 0. " FSC0 ,Filter scale configuration" "Dual 16b,Single 32b" rgroup.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FFA27 ,Filter FIFO assignment for filter 27" "FIFO 0,FIFO 1" bitfld.long 0x00 26. " FFA26 ,Filter FIFO assignment for filter 26" "FIFO 0,FIFO 1" bitfld.long 0x00 25. " FFA25 ,Filter FIFO assignment for filter 25" "FIFO 0,FIFO 1" bitfld.long 0x00 24. " FFA24 ,Filter FIFO assignment for filter 24" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 23. " FFA23 ,Filter FIFO assignment for filter 23" "FIFO 0,FIFO 1" bitfld.long 0x00 22. " FFA22 ,Filter FIFO assignment for filter 22" "FIFO 0,FIFO 1" bitfld.long 0x00 21. " FFA21 ,Filter FIFO assignment for filter 21" "FIFO 0,FIFO 1" bitfld.long 0x00 20. " FFA20 ,Filter FIFO assignment for filter 20" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 19. " FFA19 ,Filter FIFO assignment for filter 19" "FIFO 0,FIFO 1" bitfld.long 0x00 18. " FFA18 ,Filter FIFO assignment for filter 18" "FIFO 0,FIFO 1" bitfld.long 0x00 17. " FFA17 ,Filter FIFO assignment for filter 17" "FIFO 0,FIFO 1" bitfld.long 0x00 16. " FFA16 ,Filter FIFO assignment for filter 16" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 15. " FFA15 ,Filter FIFO assignment for filter 15" "FIFO 0,FIFO 1" bitfld.long 0x00 14. " FFA14 ,Filter FIFO assignment for filter 14" "FIFO 0,FIFO 1" textline " " endif bitfld.long 0x00 13. " FFA13 ,Filter FIFO assignment for filter 13" "FIFO 0,FIFO 1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO assignment for filter 12" "FIFO 0,FIFO 1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO assignment for filter 11" "FIFO 0,FIFO 1" bitfld.long 0x00 10. " FFA10 ,Filter FIFO assignment for filter 10" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 9. " FFA9 ,Filter FIFO assignment for filter 9" "FIFO 0,FIFO 1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO assignment for filter 8" "FIFO 0,FIFO 1" bitfld.long 0x00 7. " FFA7 ,Filter FIFO assignment for filter 7" "FIFO 0,FIFO 1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO assignment for filter 6" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 5. " FFA5 ,Filter FIFO assignment for filter 5" "FIFO 0,FIFO 1" bitfld.long 0x00 4. " FFA4 ,Filter FIFO assignment for filter 4" "FIFO 0,FIFO 1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO assignment for filter 3" "FIFO 0,FIFO 1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO assignment for filter 2" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO assignment for filter 1" "FIFO 0,FIFO 1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO assignment for filter 0" "FIFO 0,FIFO 1" endif group.long 0x21C++0x03 line.long 0x00 "CAN_FA1R,CAN Filter Activation Register" sif (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L475*")) bitfld.long 0x00 27. " FACT27 ,Filter active" "Not active,Active" bitfld.long 0x00 26. " FACT26 ,Filter active" "Not active,Active" bitfld.long 0x00 25. " FACT25 ,Filter active" "Not active,Active" bitfld.long 0x00 24. " FACT24 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 23. " FACT23 ,Filter active" "Not active,Active" bitfld.long 0x00 22. " FACT22 ,Filter active" "Not active,Active" bitfld.long 0x00 21. " FACT21 ,Filter active" "Not active,Active" bitfld.long 0x00 20. " FACT20 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 19. " FACT19 ,Filter active" "Not active,Active" bitfld.long 0x00 18. " FACT18 ,Filter active" "Not active,Active" bitfld.long 0x00 17. " FACT17 ,Filter active" "Not active,Active" bitfld.long 0x00 16. " FACT16 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 15. " FACT15 ,Filter active" "Not active,Active" bitfld.long 0x00 14. " FACT14 ,Filter active" "Not active,Active" textline " " endif bitfld.long 0x00 13. " FACT13 ,Filter active" "Not active,Active" bitfld.long 0x00 12. " FACT12 ,Filter active" "Not active,Active" bitfld.long 0x00 11. " FACT11 ,Filter active" "Not active,Active" bitfld.long 0x00 10. " FACT10 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 9. " FACT9 ,Filter active" "Not active,Active" bitfld.long 0x00 8. " FACT8 ,Filter active" "Not active,Active" bitfld.long 0x00 7. " FACT7 ,Filter active" "Not active,Active" bitfld.long 0x00 6. " FACT6 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 5. " FACT5 ,Filter active" "Not active,Active" bitfld.long 0x00 4. " FACT4 ,Filter active" "Not active,Active" bitfld.long 0x00 3. " FACT3 ,Filter active" "Not active,Active" bitfld.long 0x00 2. " FACT2 ,Filter active" "Not active,Active" textline " " bitfld.long 0x00 1. " FACT1 ,Filter active" "Not active,Active" bitfld.long 0x00 0. " FACT0 ,Filter active" "Not active,Active" textline " " if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<0.))==0x0)) group.long 0x240++0x07 line.long 0x00 "CAN_F0R1,Filter Bank 0 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F0R2,Filter bank 0 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x240++0x07 line.long 0x00 "CAN_F0R1,Filter Bank 0 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F0R2,Filter bank 0 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<1.))==0x0)) group.long 0x248++0x07 line.long 0x00 "CAN_F1R1,Filter Bank 1 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F1R2,Filter bank 1 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x248++0x07 line.long 0x00 "CAN_F1R1,Filter Bank 1 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F1R2,Filter bank 1 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<2.))==0x0)) group.long 0x250++0x07 line.long 0x00 "CAN_F2R1,Filter Bank 2 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F2R2,Filter bank 2 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x250++0x07 line.long 0x00 "CAN_F2R1,Filter Bank 2 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F2R2,Filter bank 2 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<3.))==0x0)) group.long 0x258++0x07 line.long 0x00 "CAN_F3R1,Filter Bank 3 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F3R2,Filter bank 3 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x258++0x07 line.long 0x00 "CAN_F3R1,Filter Bank 3 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F3R2,Filter bank 3 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<4.))==0x0)) group.long 0x260++0x07 line.long 0x00 "CAN_F4R1,Filter Bank 4 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F4R2,Filter bank 4 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x260++0x07 line.long 0x00 "CAN_F4R1,Filter Bank 4 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F4R2,Filter bank 4 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<5.))==0x0)) group.long 0x268++0x07 line.long 0x00 "CAN_F5R1,Filter Bank 5 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F5R2,Filter bank 5 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x268++0x07 line.long 0x00 "CAN_F5R1,Filter Bank 5 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F5R2,Filter bank 5 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<6.))==0x0)) group.long 0x270++0x07 line.long 0x00 "CAN_F6R1,Filter Bank 6 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F6R2,Filter bank 6 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x270++0x07 line.long 0x00 "CAN_F6R1,Filter Bank 6 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F6R2,Filter bank 6 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<7.))==0x0)) group.long 0x278++0x07 line.long 0x00 "CAN_F7R1,Filter Bank 7 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F7R2,Filter bank 7 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x278++0x07 line.long 0x00 "CAN_F7R1,Filter Bank 7 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F7R2,Filter bank 7 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<8.))==0x0)) group.long 0x280++0x07 line.long 0x00 "CAN_F8R1,Filter Bank 8 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F8R2,Filter bank 8 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x280++0x07 line.long 0x00 "CAN_F8R1,Filter Bank 8 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F8R2,Filter bank 8 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<9.))==0x0)) group.long 0x288++0x07 line.long 0x00 "CAN_F9R1,Filter Bank 9 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F9R2,Filter bank 9 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x288++0x07 line.long 0x00 "CAN_F9R1,Filter Bank 9 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F9R2,Filter bank 9 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<10.))==0x0)) group.long 0x290++0x07 line.long 0x00 "CAN_F10R1,Filter Bank 10 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F10R2,Filter bank 10 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x290++0x07 line.long 0x00 "CAN_F10R1,Filter Bank 10 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F10R2,Filter bank 10 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<11.))==0x0)) group.long 0x298++0x07 line.long 0x00 "CAN_F11R1,Filter Bank 11 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F11R2,Filter bank 11 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x298++0x07 line.long 0x00 "CAN_F11R1,Filter Bank 11 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F11R2,Filter bank 11 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<12.))==0x0)) group.long 0x2A0++0x07 line.long 0x00 "CAN_F12R1,Filter Bank 12 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F12R2,Filter bank 12 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2A0++0x07 line.long 0x00 "CAN_F12R1,Filter Bank 12 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F12R2,Filter bank 12 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif if ((((per.l(ad:0x40006400+0x200))&0x1)==0x1)||(((per.l(ad:0x40006400+0x21C))&(1.<<13.))==0x0)) group.long 0x2A8++0x07 line.long 0x00 "CAN_F13R1,Filter Bank 13 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F13R2,Filter bank 13 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" else rgroup.long 0x2A8++0x07 line.long 0x00 "CAN_F13R1,Filter Bank 13 Register 1" bitfld.long 0x00 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x00 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x00 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x00 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x00 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x00 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x00 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x00 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x00 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x00 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x00 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x00 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x00 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x00 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x00 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x00 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x00 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x00 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x00 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x00 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x00 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x00 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x00 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x00 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x00 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Filter bit 0" "0,1" line.long 0x04 "CAN_F13R2,Filter bank 13 register 2" bitfld.long 0x04 31. " FB[31] ,Filter bit 31" "0,1" bitfld.long 0x04 30. " [30] ,Filter bit 30" "0,1" bitfld.long 0x04 29. " [29] ,Filter bit 29" "0,1" bitfld.long 0x04 28. " [28] ,Filter bit 28" "0,1" textline " " bitfld.long 0x04 27. " [27] ,Filter bit 27" "0,1" bitfld.long 0x04 26. " [26] ,Filter bit 26" "0,1" bitfld.long 0x04 25. " [25] ,Filter bit 25" "0,1" bitfld.long 0x04 24. " [24] ,Filter bit 24" "0,1" textline " " bitfld.long 0x04 23. " [23] ,Filter bit 23" "0,1" bitfld.long 0x04 22. " [22] ,Filter bit 22" "0,1" bitfld.long 0x04 21. " [21] ,Filter bit 21" "0,1" bitfld.long 0x04 20. " [20] ,Filter bit 20" "0,1" textline " " bitfld.long 0x04 19. " [19] ,Filter bit 19" "0,1" bitfld.long 0x04 18. " [18] ,Filter bit 18" "0,1" bitfld.long 0x04 17. " [17] ,Filter bit 17" "0,1" bitfld.long 0x04 16. " [16] ,Filter bit 16" "0,1" textline " " bitfld.long 0x04 15. " [15] ,Filter bit 15" "0,1" bitfld.long 0x04 14. " [14] ,Filter bit 14" "0,1" bitfld.long 0x04 13. " [13] ,Filter bit 13" "0,1" bitfld.long 0x04 12. " [12] ,Filter bit 12" "0,1" textline " " bitfld.long 0x04 10. " [10] ,Filter bit 10" "0,1" bitfld.long 0x04 9. " [9] ,Filter bit 9" "0,1" bitfld.long 0x04 8. " [8] ,Filter bit 8" "0,1" bitfld.long 0x04 7. " [7] ,Filter bit 7" "0,1" textline " " bitfld.long 0x04 6. " [6] ,Filter bit 6" "0,1" bitfld.long 0x04 5. " [5] ,Filter bit 5" "0,1" bitfld.long 0x04 4. " [4] ,Filter bit 4" "0,1" bitfld.long 0x04 3. " [3] ,Filter bit 3" "0,1" textline " " bitfld.long 0x04 2. " [2] ,Filter bit 2" "0,1" bitfld.long 0x04 1. " [1] ,Filter bit 1" "0,1" bitfld.long 0x04 0. " [0] ,Filter bit 0" "0,1" endif tree.end width 0x0B endif tree.end sif (cpuis("STM32L4?2*")||cpuis("STM32L4?3*")) tree "USB (Universal serial bus)" base ad:0x40006800 width 12. group.long 0x40++0x07 line.long 0x00 "USB_CNTR,USB Control Register" bitfld.long 0x00 15. " CTRM ,Correct transfer interrupt mask" "Disabled,Enabled" bitfld.long 0x00 14. " PMAOVRM ,Packet memory area over/underrun interrupt mask" "Disabled,Enabled" bitfld.long 0x00 13. " ERRM ,Error interrupt mask" "Disabled,Enabled" bitfld.long 0x00 12. " WKUPM ,Wake-up interrupt mask" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SUSPM ,Suspend mode interrupt mask" "Disabled,Enabled" bitfld.long 0x00 10. " RESETM ,USB reset interrupt mask" "Disabled,Enabled" bitfld.long 0x00 9. " SOFM ,Start of frame interrupt mask" "Disabled,Enabled" bitfld.long 0x00 8. " ESOFM ,Expected start of frame interrupt mask" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " L1REQM ,LPM L1 state request interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " L1RESUME ,LPM L1 resume request" "Disabled,Enabled" bitfld.long 0x00 4. " RESUME ,Resume request" "No effect,Requested" bitfld.long 0x00 3. " FSUSP ,Force suspend" "No effect,Forced" textline " " bitfld.long 0x00 2. " LP_MODE ,Low-power mode" "No Low-power,Low-power" bitfld.long 0x00 1. " PDWN ,Power down" "Not powered down,Powered down" bitfld.long 0x00 0. " FRES ,Force USB reset" "Cleared,Reset" line.long 0x04 "USB_ISTR,USB Interrupt Status Register" rbitfld.long 0x04 15. " CTR ,Correct transfer" "Disabled,Enabled" bitfld.long 0x04 14. " PMAOVR ,Packet memory area over/underrun" "No over/Underrun,Over/Underrun" bitfld.long 0x04 13. " ERR ,Error" "No error,Error" bitfld.long 0x04 12. " WKUP ,Wakeup" "No wakeup,Wakeup" textline " " bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Not requested,Requested" bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset" bitfld.long 0x04 9. " SOF ,Start of frame" "No effect,Packet arrived" bitfld.long 0x04 8. " ESOF ,Expected start of frame" "No effect,Packet expected" textline " " bitfld.long 0x04 7. " L1REQ ,LPM L1 state request" "Not requested,Requested" rbitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT/2 pending transactions" rbitfld.long 0x04 0.--3. " EP_ID ,Endpoint identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x48++0x03 line.long 0x00 "USB_FNR,USB Frame Number Register" bitfld.long 0x00 15. " RXDP ,Receive data + line status" "No data,Data" bitfld.long 0x00 14. " RXDM ,Receive data - line status" "No data,Data" bitfld.long 0x00 13. " LCK ,Locked" "Unlocked,Locked" bitfld.long 0x00 11.--12. " LSOF ,Lost SOF" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--10. 1. " FN ,Frame number" group.long 0x4C++0x0F line.long 0x00 "USB_DADDR,USB Device Address" bitfld.long 0x00 7. " EF ,Enable function" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 0x01 " ADD ,Device address" line.long 0x04 "USB_BTABLE,Buffer Table Address" hexmask.long.word 0x04 3.--15. 1. " BTABLE ,Buffer table" line.long 0x08 "USB_LPMCSR,LPM Control And Status Register" rbitfld.long 0x08 4.--7. " BESL ,BESL value received with last ACKed LPM Token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 3. " REMWAKE ,bRemoteWake value received with last ACKed LPM Token" "0,1" bitfld.long 0x08 1. " LPMACK ,LPM token acknowledge enable" "NYET,ACK" bitfld.long 0x08 0. " LPMEN ,LPM support enable" "Disabled,Enabled" line.long 0x0C "USB_BCDR,Battery Charging Detector" bitfld.long 0x0C 15. " DPPU ,DP pull-up control" "Disabled,Enabled" rbitfld.long 0x0C 7. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port/Proprietary charger" rbitfld.long 0x0C 6. " SDET ,Secondary detection (SD) status" "CDP,DCP" rbitfld.long 0x0C 5. " PDET ,Primary detection (PD) status" "No BCD support,BCD support" textline " " rbitfld.long 0x0C 4. " DCDET ,Data contact detection" "Not detected,Detected" bitfld.long 0x0C 3. " SDEN ,Secondary detection (SD) mode" "Disabled,Enabled" bitfld.long 0x0C 2. " PDEN ,Primary detection (PD) mode" "Disabled,Enabled" bitfld.long 0x0C 1. " DCDEN ,Data contact detection (DCD) mode" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " BCDEN ,Battery charging detector" "Disabled,Enabled" group.long 0x0++0x03 line.long 0x00 "USB_EP0R,USB Endpoint 0 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4++0x03 line.long 0x00 "USB_EP1R,USB Endpoint 1 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x03 line.long 0x00 "USB_EP2R,USB Endpoint 2 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x03 line.long 0x00 "USB_EP3R,USB Endpoint 3 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "USB_EP4R,USB Endpoint 4 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x03 line.long 0x00 "USB_EP5R,USB Endpoint 5 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x03 line.long 0x00 "USB_EP6R,USB Endpoint 6 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "USB_EP7R,USB Endpoint 7 Register" bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" base ad:((per.l((ad:0x40006800+0x50))&0xFFF8))+ad:0x40006800 width 16. tree "USB Buffer Descriptor Table" group.word 0x0++0x01 line.word 0x00 "USB_ADDR0_TX,Transmission Buffer Address 0" hexmask.word 0x00 1.--15. 0x02 " ADDR0_TX ,Transmission buffer address" group.word (0x0+0x02)++0x01 line.word 0x00 "USB_COUNT0_TX,Transmission Byte Count 0" hexmask.word 0x00 0.--9. 1. " COUNT0_TX ,Transmission byte count" group.word (0x0+0x04)++0x01 line.word 0x00 "USB_ADDR0_RX,Reception Buffer Address 0" hexmask.word 0x00 1.--15. 0x02 " ADDR0_RX ,Reception buffer address" group.word (0x0+0x06)++0x01 line.word 0x00 "USB_COUNT0_RX,Reception Byte Count 0" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT0_RX ,Reception byte count" group.word 0x8++0x01 line.word 0x00 "USB_ADDR1_TX,Transmission Buffer Address 1" hexmask.word 0x00 1.--15. 0x02 " ADDR1_TX ,Transmission buffer address" group.word (0x8+0x02)++0x01 line.word 0x00 "USB_COUNT1_TX,Transmission Byte Count 1" hexmask.word 0x00 0.--9. 1. " COUNT1_TX ,Transmission byte count" group.word (0x8+0x04)++0x01 line.word 0x00 "USB_ADDR1_RX,Reception Buffer Address 1" hexmask.word 0x00 1.--15. 0x02 " ADDR1_RX ,Reception buffer address" group.word (0x8+0x06)++0x01 line.word 0x00 "USB_COUNT1_RX,Reception Byte Count 1" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT1_RX ,Reception byte count" group.word 0x10++0x01 line.word 0x00 "USB_ADDR2_TX,Transmission Buffer Address 2" hexmask.word 0x00 1.--15. 0x02 " ADDR2_TX ,Transmission buffer address" group.word (0x10+0x02)++0x01 line.word 0x00 "USB_COUNT2_TX,Transmission Byte Count 2" hexmask.word 0x00 0.--9. 1. " COUNT2_TX ,Transmission byte count" group.word (0x10+0x04)++0x01 line.word 0x00 "USB_ADDR2_RX,Reception Buffer Address 2" hexmask.word 0x00 1.--15. 0x02 " ADDR2_RX ,Reception buffer address" group.word (0x10+0x06)++0x01 line.word 0x00 "USB_COUNT2_RX,Reception Byte Count 2" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT2_RX ,Reception byte count" group.word 0x18++0x01 line.word 0x00 "USB_ADDR3_TX,Transmission Buffer Address 3" hexmask.word 0x00 1.--15. 0x02 " ADDR3_TX ,Transmission buffer address" group.word (0x18+0x02)++0x01 line.word 0x00 "USB_COUNT3_TX,Transmission Byte Count 3" hexmask.word 0x00 0.--9. 1. " COUNT3_TX ,Transmission byte count" group.word (0x18+0x04)++0x01 line.word 0x00 "USB_ADDR3_RX,Reception Buffer Address 3" hexmask.word 0x00 1.--15. 0x02 " ADDR3_RX ,Reception buffer address" group.word (0x18+0x06)++0x01 line.word 0x00 "USB_COUNT3_RX,Reception Byte Count 3" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT3_RX ,Reception byte count" group.word 0x20++0x01 line.word 0x00 "USB_ADDR4_TX,Transmission Buffer Address 4" hexmask.word 0x00 1.--15. 0x02 " ADDR4_TX ,Transmission buffer address" group.word (0x20+0x02)++0x01 line.word 0x00 "USB_COUNT4_TX,Transmission Byte Count 4" hexmask.word 0x00 0.--9. 1. " COUNT4_TX ,Transmission byte count" group.word (0x20+0x04)++0x01 line.word 0x00 "USB_ADDR4_RX,Reception Buffer Address 4" hexmask.word 0x00 1.--15. 0x02 " ADDR4_RX ,Reception buffer address" group.word (0x20+0x06)++0x01 line.word 0x00 "USB_COUNT4_RX,Reception Byte Count 4" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT4_RX ,Reception byte count" group.word 0x28++0x01 line.word 0x00 "USB_ADDR5_TX,Transmission Buffer Address 5" hexmask.word 0x00 1.--15. 0x02 " ADDR5_TX ,Transmission buffer address" group.word (0x28+0x02)++0x01 line.word 0x00 "USB_COUNT5_TX,Transmission Byte Count 5" hexmask.word 0x00 0.--9. 1. " COUNT5_TX ,Transmission byte count" group.word (0x28+0x04)++0x01 line.word 0x00 "USB_ADDR5_RX,Reception Buffer Address 5" hexmask.word 0x00 1.--15. 0x02 " ADDR5_RX ,Reception buffer address" group.word (0x28+0x06)++0x01 line.word 0x00 "USB_COUNT5_RX,Reception Byte Count 5" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT5_RX ,Reception byte count" group.word 0x30++0x01 line.word 0x00 "USB_ADDR6_TX,Transmission Buffer Address 6" hexmask.word 0x00 1.--15. 0x02 " ADDR6_TX ,Transmission buffer address" group.word (0x30+0x02)++0x01 line.word 0x00 "USB_COUNT6_TX,Transmission Byte Count 6" hexmask.word 0x00 0.--9. 1. " COUNT6_TX ,Transmission byte count" group.word (0x30+0x04)++0x01 line.word 0x00 "USB_ADDR6_RX,Reception Buffer Address 6" hexmask.word 0x00 1.--15. 0x02 " ADDR6_RX ,Reception buffer address" group.word (0x30+0x06)++0x01 line.word 0x00 "USB_COUNT6_RX,Reception Byte Count 6" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT6_RX ,Reception byte count" group.word 0x38++0x01 line.word 0x00 "USB_ADDR7_TX,Transmission Buffer Address 7" hexmask.word 0x00 1.--15. 0x02 " ADDR7_TX ,Transmission buffer address" group.word (0x38+0x02)++0x01 line.word 0x00 "USB_COUNT7_TX,Transmission Byte Count 7" hexmask.word 0x00 0.--9. 1. " COUNT7_TX ,Transmission byte count" group.word (0x38+0x04)++0x01 line.word 0x00 "USB_ADDR7_RX,Reception Buffer Address 7" hexmask.word 0x00 1.--15. 0x02 " ADDR7_RX ,Reception buffer address" group.word (0x38+0x06)++0x01 line.word 0x00 "USB_COUNT7_RX,Reception Byte Count 7" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 1. " COUNT7_RX ,Reception byte count" tree.end width 0x0B tree.end endif sif (cpuis("STM32L4?5*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) tree "OTG_FS (USB on-the-go full-speed)" base ad:0x50000000 width 16. tree "Common registers (Host&Device modes)" if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "OTG_GOTGCTL,OTG Control and Status Register" bitfld.long 0x00 20. " OTGVER ,OTG version" "Ver 1.3,Ver 2.0" rbitfld.long 0x00 19. " BSVLD ,B-session valid" "Invalid,Valid" rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-dev mode,B-dev mode" bitfld.long 0x00 12. " EHEN ,Embedded host enable" "OTG A device,Embedded host" textline " " bitfld.long 0x00 11. " DHNPEN ,Device HNP enabled" "Disabled,Enabled" bitfld.long 0x00 9. " HNPRQ ,HNP request" "Not requested,Requested" rbitfld.long 0x00 8. " HNGSCS ,Host negotiation success" "Failed,Succeed" textline " " sif ((!cpuis("STM32L4?5*"))||(cpuis("STM32L4?6*"))||(cpuis("STM32L475*"))) bitfld.long 0x00 7. " BVALOVAL ,B-peripheral session valid override value" "Valid 0,Valid 1" bitfld.long 0x00 6. " BVALOEN ,B-peripheral session valid override enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " SRQ ,Session request" "No request,Request" rbitfld.long 0x00 0. " SRQSCS ,Session request success" "Failed,Succeed" else group.long 0x00++0x03 line.long 0x00 "OTG_GOTGCTL,OTG Control and Status Register" bitfld.long 0x00 20. " OTGVER ,OTG version" "Ver 1.3,Ver 2.0" rbitfld.long 0x00 18. " ASVLD ,A-session valid" "Invalid,Valid" rbitfld.long 0x00 17. " DBCT ,Long/short debounce time" "Long,Short" rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-dev mode,B-dev mode" textline " " bitfld.long 0x00 12. " EHEN ,Embedded host enable" "OTG A device,Embedded host" bitfld.long 0x00 10. " HSHNPEN ,Host set HNP enable" "Disabled,Enabled" sif ((!cpuis("STM32L4?5*"))||(cpuis("STM32L4?6*"))||(cpuis("STM32L475*"))) textline " " bitfld.long 0x00 5. " AVALOVAL ,A-peripheral session valid override value" "Valid 0,Valid 1" bitfld.long 0x00 4. " AVALOEN ,A-peripheral session valid override enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " VBVALOVAL ,VBUS valid override value" "Valid 0,Valid 1" bitfld.long 0x00 2. " VBVALOEN ,VBUS valid override enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x04++0x03 line.long 0x00 "OTG_GOTGINT,OTG Interrupt Register" eventfld.long 0x00 20. " IDCHNG ,This bit when set indicates that there is a change in the value of the ID input pin" "No effect,Input ID changed" eventfld.long 0x00 18. " ADTOCHG ,A-device timeout change" "No effect,Timeout" eventfld.long 0x00 17. " HNGDET ,Host negotiation detected" "No effect,Host negotiation" eventfld.long 0x00 9. " HNSSCHG ,Host negotiation success status change" "No effect,Negotiation end" textline " " eventfld.long 0x00 8. " SRSSCHG ,Session request success status change" "No effect,Request done" eventfld.long 0x00 2. " SEDET ,Session end detected" "No effect,Voltage invalid" else group.long 0x04++0x03 line.long 0x00 "OTG_GOTGINT,OTG Interrupt Register" eventfld.long 0x00 20. " IDCHNG ,This bit when set indicates that there is a change in the value of the ID input pin" "No effect,Input ID changed" eventfld.long 0x00 19. " DBCDNE ,Debounce done" "No effect,Completed" eventfld.long 0x00 18. " ADTOCHG ,A-device timeout change" "No effect,Timeout" eventfld.long 0x00 17. " HNGDET ,Host negotiation detected" "No effect,Host negotiation" textline " " eventfld.long 0x00 9. " HNSSCHG ,Host negotiation success status change" "No effect,Negotiation end" eventfld.long 0x00 8. " SRSSCHG ,Session request success status change" "No effect,Request done" eventfld.long 0x00 2. " SEDET ,Session end detected" "No effect,Voltage invalid" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x08++0x03 line.long 0x00 "OTG_GAHBCFG,OTG AHB Configuration Register" bitfld.long 0x00 7. " TXFELVL ,Tx FIFO empty level (bit indicates when IN endpoint Transmit FIFO empty interrupt)" "Half empty,Completely empty" bitfld.long 0x00 0. " GINTMSK ,Global interrupt mask" "Masked,Unmasked" else group.long 0x08++0x03 line.long 0x00 "OTG_GAHBCFG,OTG AHB Configuration Register" bitfld.long 0x00 8. " PTXFELVL ,Periodic Tx FIFO empty level" "Half empty,Completely empty" bitfld.long 0x00 7. " TXFELVL ,Tx FIFO empty level (bit indicates when the nonperiodic Tx FIFO empty interrupt)" "Half empty,Completely empty" bitfld.long 0x00 0. " GINTMSK ,Global interrupt mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x0C++0x03 line.long 0x00 "OTG_GUSBCFG,OTG USB Configuration Register" bitfld.long 0x00 30. " FDMOD ,Force device mode" "Normal,Force device" bitfld.long 0x00 29. " FHMOD ,Force host mode" "Normal,Force host" bitfld.long 0x00 10.--13. " TRDT ,USB turnaround time" ",,,,,,32 MHz,27.5-32 MHz,24-27.5 MHz,21.8-24 MHz,20-21.8 MHz,18.5-20 MHz,17.2-18.5 MHz,16-17.2 MHz,15-16 MHz,14.2-15 MHz" bitfld.long 0x00 9. " HNPCAP ,HNP-capable enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " SRPCAP ,SRP-capable enabled" "Disabled,Enabled" rbitfld.long 0x00 6. " PHYSEL ,Full Speed serial transceiver select" "0,1" bitfld.long 0x00 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7" else group.long 0x0C++0x03 line.long 0x00 "OTG_GUSBCFG,OTG USB Configuration Register" bitfld.long 0x00 30. " FDMOD ,Force device mode" "Normal,Force device" bitfld.long 0x00 29. " FHMOD ,Force host mode" "Normal,Force host" bitfld.long 0x00 9. " HNPCAP ,HNP-capable enabled" "Disabled,Enabled" bitfld.long 0x00 8. " SRPCAP ,SRP-capable enabled" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " PHYSEL ,Full Speed serial transceiver select" "0,1" bitfld.long 0x00 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x10++0x03 line.long 0x00 "OTG_GRSTCTL,OTG Reset Register" rbitfld.long 0x00 31. " AHBIDL ,AHB master idle" "Busy,Idle" bitfld.long 0x00 6.--10. " TXFNUM ,This is the FIFO number that must be flushed using the Tx FIFO Flush bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,All,?..." bitfld.long 0x00 5. " TXFFLSH ,Tx FIFO flush" "No effect,Flush Tx" bitfld.long 0x00 4. " RXFFLSH ,Rx FIFO flush" "No effect,Flush Rx" textline " " sif (!cpuis("STM32L475*")) bitfld.long 0x00 1. " PSRST ,Partial soft reset" "No reset,Reset" endif textline " " bitfld.long 0x00 0. " CSRST ,Core soft reset" "No reset,Reset" else group.long 0x10++0x03 line.long 0x00 "OTG_GRSTCTL,OTG Reset Register" rbitfld.long 0x00 31. " AHBIDL ,AHB master idle" "Busy,Idle" bitfld.long 0x00 6.--10. " TXFNUM ,This is the FIFO number that must be flushed using the Tx FIFO Flush bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,All,?..." bitfld.long 0x00 5. " TXFFLSH ,Tx FIFO flush" "No effect,Flush Tx" bitfld.long 0x00 4. " RXFFLSH ,Rx FIFO flush" "No effect,Flush Rx" textline " " bitfld.long 0x00 2. " FCRST ,Host frame counter reset" "No reset,Reset" textline " " sif (!cpuis("STM32L475*")) bitfld.long 0x00 1. " PSRST ,Partial soft reset" "No reset,Reset" endif textline " " bitfld.long 0x00 0. " CSRST ,Core soft reset" "No reset,Reset" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) if (((per.l(ad:0x50000000+0x54))&0x1)==0x0) group.long 0x14++0x03 line.long 0x00 "OTG_GINTSTS,OTG Core Interrupt Register" eventfld.long 0x00 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" textline " " eventfld.long 0x00 23. " RSTDET ,Reset detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No effect,>1 isoch OUT" textline " " eventfld.long 0x00 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt" rbitfld.long 0x00 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x00 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " ENUMDNE ,Enumeration done" "Not completed,Completed" textline " " eventfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset" eventfld.long 0x00 11. " USBSUSP ,USB suspend" "No suspend,Suspend" eventfld.long 0x00 10. " ESUSP ,Early suspend" "No suspend,Suspend" rbitfld.long 0x00 7. " GONAKEFF ,Global OUT NAK effective" "No effect,Effect in core" textline " " rbitfld.long 0x00 6. " GINAKEFF ,Global IN non-periodic NAK effective" "No interrupt,Interrupt" rbitfld.long 0x00 4. " RXFLVL ,Rx FIFO non-empty" "Empty,Not empty" eventfld.long 0x00 3. " SOF ,Start of frame" "No start,Start" rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device,Host" else group.long 0x14++0x03 line.long 0x00 "OTG_GINTSTS,OTG Core Interrupt Register" eventfld.long 0x00 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" eventfld.long 0x00 27. " LPMINT ,LPM interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " RSTDET ,Reset detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No effect,>1 isoch OUT" textline " " eventfld.long 0x00 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt" rbitfld.long 0x00 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x00 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " ENUMDNE ,Enumeration done" "Not completed,Completed" textline " " eventfld.long 0x00 12. " USBRST ,USB reset" "No reset,Reset" eventfld.long 0x00 11. " USBSUSP ,USB suspend" "No suspend,Suspend" eventfld.long 0x00 10. " ESUSP ,Early suspend" "No suspend,Suspend" rbitfld.long 0x00 7. " GONAKEFF ,Global OUT NAK effective" "No effect,Effect in core" textline " " rbitfld.long 0x00 6. " GINAKEFF ,Global IN non-periodic NAK effective" "No interrupt,Interrupt" rbitfld.long 0x00 4. " RXFLVL ,Rx FIFO non-empty" "Empty,Not empty" eventfld.long 0x00 3. " SOF ,Start of frame" "No start,Start" rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device,Host" endif else if (((per.l(ad:0x50000000+0x54))&0x1)==0x0) group.long 0x14++0x03 line.long 0x00 "OTG_GINTSTS,OTG Core Interrupt Register" eventfld.long 0x00 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" textline " " rbitfld.long 0x00 26. " PTXFE ,Periodic Tx FIFO empty" "Not empty,Empty" rbitfld.long 0x00 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt" rbitfld.long 0x00 5. " NPTXFE ,Non-periodic Tx FIFO empty" "Not empty,Empty" rbitfld.long 0x00 4. " RXFLVL ,Rx FIFO non-empty" "Empty,Not empty" eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started" textline " " rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device,Host" else group.long 0x14++0x03 line.long 0x00 "OTG_GINTSTS,OTG Core Interrupt Register" eventfld.long 0x00 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" textline " " eventfld.long 0x00 27. " LPMINT ,LPM interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 26. " PTXFE ,Periodic Tx FIFO empty" "Not empty,Empty" rbitfld.long 0x00 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt" rbitfld.long 0x00 5. " NPTXFE ,Non-periodic Tx FIFO empty" "Not empty,Empty" rbitfld.long 0x00 4. " RXFLVL ,Rx FIFO non-empty" "Empty,Not empty" eventfld.long 0x00 3. " SOF ,Start of frame" "Not started,Started" textline " " rbitfld.long 0x00 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 0. " CMOD ,Current mode of operation" "Device,Host" endif endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x18++0x03 line.long 0x00 "OTG_GINTMSK,OTG Interrupt Mask Register" bitfld.long 0x00 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked" bitfld.long 0x00 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked" bitfld.long 0x00 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked" bitfld.long 0x00 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" textline " " bitfld.long 0x00 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked" bitfld.long 0x00 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked" bitfld.long 0x00 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked" bitfld.long 0x00 20. " IISOIXFRM ,Incomplete isochronous IN transfer mask" "Masked,Unmasked" textline " " bitfld.long 0x00 19. " OEPINT ,OUT endpoints interrupt mask" "Masked,Unmasked" bitfld.long 0x00 18. " IEPINT ,IN endpoints interrupt mask" "Masked,Unmasked" bitfld.long 0x00 15. " EOPFM ,End of periodic frame interrupt mask" "Masked,Unmasked" bitfld.long 0x00 14. " ISOODRPM ,Isochronous OUT packet dropped interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " ENUMDNEM ,Enumeration done mask" "Masked,Unmasked" bitfld.long 0x00 12. " USBRST ,USB reset mask" "Masked,Unmasked" bitfld.long 0x00 11. " USBSUSPM ,USB suspend mask" "Masked,Unmasked" bitfld.long 0x00 10. " ESUSPM ,Early suspend mask" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " GONAKEFFM ,Global OUT NAK effective mask" "Masked,Unmasked" bitfld.long 0x00 6. " GINAKEFFM ,Global non-periodic IN NAK effective mask" "Masked,Unmasked" bitfld.long 0x00 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" bitfld.long 0x00 3. " SOFM ,Start of frame mask" "Masked,Unmasked" textline " " bitfld.long 0x00 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked" else group.long 0x18++0x03 line.long 0x00 "OTG_GINTMSK,OTG Interrupt Mask Register" bitfld.long 0x00 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked" bitfld.long 0x00 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked" bitfld.long 0x00 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" bitfld.long 0x00 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 26. " PTXFEM ,Periodic Tx FIFO empty mask" "Masked,Unmasked" bitfld.long 0x00 25. " HCIM ,Host channels interrupt mask" "Masked,Unmasked" rbitfld.long 0x00 24. " PRTIM ,Host port interrupt mask" "Masked,Unmasked" bitfld.long 0x00 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " NPTXFEM ,Non-periodic Tx FIFO empty mask" "Masked,Unmasked" bitfld.long 0x00 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" bitfld.long 0x00 3. " SOFM ,Start of frame mask" "Masked,Unmasked" bitfld.long 0x00 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) rgroup.long 0x1C++0x03 line.long 0x00 "OTG_GRXSTSR,OTG Receive Status Debug Read" bitfld.long 0x00 21.--24. " FRMNUM ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",OUT NAK,OUT data packet received,OUT transfer completed,SETUP transaction completed,,SETUP data packet received,?..." bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,,DATA1," hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count" textline " " bitfld.long 0x00 0.--3. " EPNUM ,Endpoint number" "0,1,2,3,4,5,?..." else rgroup.long 0x1C++0x03 line.long 0x00 "OTG_GRXSTSR,OTG Receive Status Debug Read" bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..." bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,,DATA1," hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count" bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,?..." endif hgroup.long 0x20++0x03 hide.long 0x00 "OTG_GRXSTSP,OTG Status Read and Pop Register" in group.long 0x24++0x03 line.long 0x00 "OTG_GRXFSIZ,OTG Receive FIFO Size Register" hexmask.long.word 0x00 0.--15. 1. " RXFD ,Rx FIFO depth" if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x28++0x03 line.long 0x00 "OTG_DIEPTXF0,Endpoint 0 Transmit FIFO Size" hexmask.long.word 0x00 16.--31. 1. " TX0FD ,Endpoint 0 Tx FIFO depth" hexmask.long.word 0x00 0.--15. 1. " TX0FSA ,Endpoint 0 transmit RAM start address" else group.long 0x28++0x03 line.long 0x00 "OTG_HNPTXFSIZ,OTG Host Non-Periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic Tx FIFO depth" hexmask.long.word 0x00 0.--15. 1. " NPTXFSA ,Non-periodic transmit RAM start address" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) rgroup.long 0x2C++0x03 line.long 0x00 "OTG_HNPTXSTS,OTG Non-Periodic Transmit FIFO/Queue Status Register" bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Channel/Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Entry in the non-periodic Tx request queue that is currently being processed by the MAC" "IN/OUT token,Zero-length transmit packet,,Channel halt cmd" bitfld.long 0x00 24. " NPTXQTOP[24] ,Terminate (last entry for selected channel/endpoint)" "Not terminated,Terminated" hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available" textline " " hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic Tx FIFO space available" endif group.long 0x38++0x03 line.long 0x00 "OTG_GCCFG,OTG General Core Configuration Register" bitfld.long 0x00 21. " VBDEN ,USB VBUS detection enable" "Disabled,Enabled" bitfld.long 0x00 20. " SDEN ,Secondary detection (SD) mode enable" "Disabled,Enabled" bitfld.long 0x00 19. " PDEN ,Primary detection (PD) mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DCDEN ,Data contact detection (DCD) mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " BCDEN ,Battery charging detector (BCD) enable" "Disabled,Enabled" bitfld.long 0x00 16. " PWRDWN ,Power down control" "Disabled,Enabled" rbitfld.long 0x00 3. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port" rbitfld.long 0x00 2. " SDET ,Secondary detection (SD) status" "CDP,DCP" textline " " rbitfld.long 0x00 1. " PDET ,Primary detection (PD) status" "No BCD,BCD supp" rbitfld.long 0x00 0. " DCDET ,Data contact detection (DCD) status" "Not detected,Detected" rgroup.long 0x3C++0x03 line.long 0x00 "OTG_CID,OTG Core ID Register" if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x54++0x03 line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register" bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled" rbitfld.long 0x00 16. " L1RSMOK ,Sleep state resume OK" "Cannot start,Can start" rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "No sleep,Sleep" rbitfld.long 0x00 13.--14. " PMRST ,LPM response" "0,1,2,3" textline " " bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " L1SSEN ,L1 shallow sleep enable" "Disabled,Enabled" rbitfld.long 0x00 6. " REMWAKE ,RemoteWake value" "0,1" textline " " rbitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000" bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "NYET,ACK" bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register" bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled" rbitfld.long 0x00 25.--27. " LPMRCNTSTS ,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " SNDLPM ,Send LPM transaction" "Not sent,Sent" bitfld.long 0x00 21.--23. " LPMRCNT ,LPM retry count" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 17.--20. " LPMCHIDX ,LPM channel index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16. " L1RSMOK ,Sleep state resume OK" "Cannot start,Can start" rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Core not in L1,Core in L1" rbitfld.long 0x00 13.--14. " PMRST ,LPM response" "ERROR,STALL,NYET,ACK" textline " " bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..." bitfld.long 0x00 7. " L1SSEN ,L1 shallow sleep enable" "Disabled,Enabled" bitfld.long 0x00 6. " REMWAKE ,RemoteWake value" "0,1" textline " " bitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled" endif group.long 0x58++0x03 line.long 0x00 "OTG_GPWRDN,OTG Power Down Register" eventfld.long 0x00 23. " ADPIF ,ADP interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " ADPMEN ,ADP module enable" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "OTG_GADPCTL,OTG ADP Timer Control and Status Register" bitfld.long 0x00 27.--28. " AR ,Access request" "R/W valid,Read request,Write request,?..." bitfld.long 0x00 26. " ADPTOIM ,ADP timeout interrupt mask" "Masked,Unmasked" bitfld.long 0x00 25. " ADPSNSIM ,ADP sense interrupt mask" "Masked,Unmasked" bitfld.long 0x00 24. " ADPPRBIM ,ADP probe interrupt mask" "Masked,Unmasked" textline " " eventfld.long 0x00 23. " ADPTOIF ,ADP timeout interrupt flag" "No timeout,Timeout" eventfld.long 0x00 22. " ADPSNSIF ,ADP sense interrupt flag" "VBUSVADPSNS" eventfld.long 0x00 21. " ADPPRBIF ,ADP probe interrupt flag" "VBUSVADPPRB" bitfld.long 0x00 20. " ADPEN ,ADP enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " ADPRST ,ADP reset" "No reset,Reset" bitfld.long 0x00 18. " ENASNS ,Enable sense" "Disabled,Enabled" bitfld.long 0x00 17. " ENAPRB ,Enable probe" "Disabled,Enabled" hexmask.long.word 0x00 6.--16. 1. " RTIM ,Ramp time" textline " " bitfld.long 0x00 4.--5. " PRBPER ,Probe period" "0.625 - 0.925 sec,1.25 - 1.85 sec,1.9 - 2.6 sec,?..." bitfld.long 0x00 2.--3. " PRBDELTA ,Probe delta" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 0.--1. " PRBDSCHG ,Probe discharge" "4ms,8ms,16ms,32ms" textline " " group.long 0x100++0x03 line.long 0x00 "OTG_HPTXFSIZ,OTG Host Periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " PTXFD ,Host periodic Tx FIFO depth" hexmask.long.word 0x00 0.--15. 1. " PTXSA ,Host periodic Tx FIFO start address" group.long 0x104++0x03 line.long 0x00 "OTG_DIEPTXF1,OTG Device IN Endpoint Transmit FIFO Size Register 1" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint Tx FIFO depth" hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x108++0x03 line.long 0x00 "OTG_DIEPTXF2,OTG Device IN Endpoint Transmit FIFO Size Register 2" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint Tx FIFO depth" hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x10C++0x03 line.long 0x00 "OTG_DIEPTXF3,OTG Device IN Endpoint Transmit FIFO Size Register 3" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint Tx FIFO depth" hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x110++0x03 line.long 0x00 "OTG_DIEPTXF4,OTG Device IN Endpoint Transmit FIFO Size Register 4" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint Tx FIFO depth" hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x114++0x03 line.long 0x00 "OTG_DIEPTXF5,OTG Device IN Endpoint Transmit FIFO Size Register 5" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint Tx FIFO depth" hexmask.long.word 0x00 0.--15. 0x01 " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" tree.end tree "Host-mode registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x400++0x07 line.long 0x00 "OTG_HCFG,OTG Host Configuration Register" rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "All,FS/LS-only" bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,6 MHz PHY,?..." line.long 0x04 "OTG_HFIR,OTG Host Frame Interval Register" bitfld.long 0x04 16. " RLDCTRL ,Reload control" "Not dynamic,Dynamic" hexmask.long.word 0x04 0.--15. 1. " FRIVL ,Frame interval" rgroup.long 0x408++0x03 line.long 0x00 "OTG_HFNUM,OTG Host Frame Number/Frame Time Remaining Register" hexmask.long.word 0x00 16.--31. 1. " FTREM ,Frame time remaining" hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number" rgroup.long 0x410++0x07 line.long 0x00 "OTG_HPTXSTS,OTG Host Periodic Transmit FIFO/Queue Status Register" sif (!cpuis("STM32L4?6*"))&&(!cpuis("STM32L475*")) hexmask.long.byte 0x00 24.--31. 1. " PTXQTOP ,Top of the periodic transmit request queue" hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available" hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available" else bitfld.long 0x00 31. " PTXQTOP[3] ,Send Odd/Even frame" "Even,Odd" bitfld.long 0x00 27.--30. " [2] ,Channel/endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 25.--26. " [1] ,Type" "IN/OUT,Zero-length packet,,Disable channel command" bitfld.long 0x00 24. " [0] ,Terminate (last entry for the selected channel/endpoint)" "Not terminated,Terminated" textline " " hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available" hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available" endif line.long 0x04 "OTG_HAINT,OTG Host All Channels Interrupt Register" bitfld.long 0x04 15. " HAINT[15] ,Channel 15 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 14. " [14] ,Channel 14 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 13. " [13] ,Channel 13 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 12. " [12] ,Channel 12 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 11. " [11] ,Channel 11 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 10. " [10] ,Channel 10 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 9. " [9] ,Channel 9 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " [8] ,Channel 8 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 7. " [7] ,Channel 7 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 6. " [6] ,Channel 6 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 5. " [5] ,Channel 5 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 4. " [4] ,Channel 4 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 3. " [3] ,Channel 3 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " [2] ,Channel 2 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 1. " [1] ,Channel 1 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " [0] ,Channel 0 interrupt" "No interrupt,Interrupt" group.long 0x418++0x03 line.long 0x00 "OTG_HAINTMSK,OTG Host All Channels Interrupt Mask Register" bitfld.long 0x00 15. " HAINTM[15] ,Channel 15 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 14. " [14] ,Channel 14 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 13. " [13] ,Channel 13 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 12. " [12] ,Channel 12 interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " [11] ,Channel 11 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 10. " [10] ,Channel 10 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,Channel 9 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,Channel 8 interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " [7] ,Channel 7 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 6. " [6] ,Channel 6 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,Channel 5 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,Channel 4 interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 2. " [2] ,Channel 2 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,Channel 1 interrupt mask" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,Channel 0 interrupt mask" "Masked,Unmasked" group.long 0x440++0x03 line.long 0x00 "OTG_HPRT,OTG Host Port Control and Status Register" rbitfld.long 0x00 17.--18. " PSPD ,Port speed" ",Full speed,Low speed,?..." bitfld.long 0x00 13.--16. " PTCTL ,Port test control" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force,?..." bitfld.long 0x00 12. " PPWR ,Port power" "OFF,ON" rbitfld.long 0x00 10.--11. " PLSTS ,Port line status" ",,OTG_FS_DP,OTG_FS_DM" textline " " bitfld.long 0x00 8. " PRST ,Port reset" "No reset,Reset" bitfld.long 0x00 7. " PSUSP ,Port suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " PRES ,Port resume" "Not resumed,Resumed" eventfld.long 0x00 5. " POCCHNG ,Port overcurrent change" "Not changed,Changed" textline " " rbitfld.long 0x00 4. " POCA ,Port overcurrent active" "Not active,Active" eventfld.long 0x00 3. " PENCHNG ,Port enable/disable change" "Not changed,Changed" eventfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled" eventfld.long 0x00 1. " PCDET ,Port connect detected" "Not detected,Detected" textline " " rbitfld.long 0x00 0. " PCSTS ,Port connect status" "No device,Device attached" endif tree "Host channels characteristics registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x500++0x03 line.long 0x00 "OTG_HCCHAR0,OTG Host Channel-0 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x520++0x03 line.long 0x00 "OTG_HCCHAR1,OTG Host Channel-1 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x540++0x03 line.long 0x00 "OTG_HCCHAR2,OTG Host Channel-2 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x560++0x03 line.long 0x00 "OTG_HCCHAR3,OTG Host Channel-3 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x580++0x03 line.long 0x00 "OTG_HCCHAR4,OTG Host Channel-4 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5A0++0x03 line.long 0x00 "OTG_HCCHAR5,OTG Host Channel-5 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5C0++0x03 line.long 0x00 "OTG_HCCHAR6,OTG Host Channel-6 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5E0++0x03 line.long 0x00 "OTG_HCCHAR7,OTG Host Channel-7 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x600++0x03 line.long 0x00 "OTG_HCCHAR8,OTG Host Channel-8 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x620++0x03 line.long 0x00 "OTG_HCCHAR9,OTG Host Channel-9 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x640++0x03 line.long 0x00 "OTG_HCCHAR10,OTG Host Channel-10 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x660++0x03 line.long 0x00 "OTG_HCCHAR11,OTG Host Channel-11 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.byte 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No effect,Low-speed device" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif tree.end tree "Host channels interrupt registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x508++0x03 line.long 0x00 "OTG_HCINT0,OTG Host Channel-0 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x528++0x03 line.long 0x00 "OTG_HCINT1,OTG Host Channel-1 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x548++0x03 line.long 0x00 "OTG_HCINT2,OTG Host Channel-2 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x568++0x03 line.long 0x00 "OTG_HCINT3,OTG Host Channel-3 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x588++0x03 line.long 0x00 "OTG_HCINT4,OTG Host Channel-4 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5A8++0x03 line.long 0x00 "OTG_HCINT5,OTG Host Channel-5 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5C8++0x03 line.long 0x00 "OTG_HCINT6,OTG Host Channel-6 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5E8++0x03 line.long 0x00 "OTG_HCINT7,OTG Host Channel-7 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x608++0x03 line.long 0x00 "OTG_HCINT8,OTG Host Channel-8 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x628++0x03 line.long 0x00 "OTG_HCINT9,OTG Host Channel-9 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x648++0x03 line.long 0x00 "OTG_HCINT10,OTG Host Channel-10 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x668++0x03 line.long 0x00 "OTG_HCINT11,OTG Host Channel-11 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "No halt,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" endif tree.end tree "Host channels interrupt mask registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x50C++0x03 line.long 0x00 "OTG_HCINTMSK0,OTG Host Channel-0 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x52C++0x03 line.long 0x00 "OTG_HCINTMSK1,OTG Host Channel-1 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x54C++0x03 line.long 0x00 "OTG_HCINTMSK2,OTG Host Channel-2 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x56C++0x03 line.long 0x00 "OTG_HCINTMSK3,OTG Host Channel-3 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x58C++0x03 line.long 0x00 "OTG_HCINTMSK4,OTG Host Channel-4 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5AC++0x03 line.long 0x00 "OTG_HCINTMSK5,OTG Host Channel-5 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5CC++0x03 line.long 0x00 "OTG_HCINTMSK6,OTG Host Channel-6 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5EC++0x03 line.long 0x00 "OTG_HCINTMSK7,OTG Host Channel-7 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x60C++0x03 line.long 0x00 "OTG_HCINTMSK8,OTG Host Channel-8 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x62C++0x03 line.long 0x00 "OTG_HCINTMSK9,OTG Host Channel-9 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x64C++0x03 line.long 0x00 "OTG_HCINTMSK10,OTG Host Channel-10 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x66C++0x03 line.long 0x00 "OTG_HCINTMSK11,OTG Host Channel-11 Interrupt Mask Register" bitfld.long 0x00 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x00 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" bitfld.long 0x00 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x00 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" bitfld.long 0x00 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 3. " STAMLLM ,STALL response received interrupt mask" "Masked,Unmasked" bitfld.long 0x00 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" endif tree.end tree "Host channels transfer size registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x510++0x03 line.long 0x00 "OTG_HCTSIZ0,OTG Host Channel-0 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x530++0x03 line.long 0x00 "OTG_HCTSIZ1,OTG Host Channel-1 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x550++0x03 line.long 0x00 "OTG_HCTSIZ2,OTG Host Channel-2 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x570++0x03 line.long 0x00 "OTG_HCTSIZ3,OTG Host Channel-3 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x590++0x03 line.long 0x00 "OTG_HCTSIZ4,OTG Host Channel-4 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5B0++0x03 line.long 0x00 "OTG_HCTSIZ5,OTG Host Channel-5 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5D0++0x03 line.long 0x00 "OTG_HCTSIZ6,OTG Host Channel-6 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x5F0++0x03 line.long 0x00 "OTG_HCTSIZ7,OTG Host Channel-7 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x610++0x03 line.long 0x00 "OTG_HCTSIZ8,OTG Host Channel-8 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x630++0x03 line.long 0x00 "OTG_HCTSIZ9,OTG Host Channel-9 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x650++0x03 line.long 0x00 "OTG_HCTSIZ10,OTG Host Channel-10 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x1) group.long 0x670++0x03 line.long 0x00 "OTG_HCTSIZ11,OTG Host Channel-11 Transfer Size Register" bitfld.long 0x00 29.--30. " DPID ,Data PID" "DATA0,,DATA1,?..." hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif tree.end tree.end tree "Device-mode registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x800++0x07 line.long 0x00 "OTG_DCFG,OTG Device Configuration Register" sif (!cpuis("STM32L475*")) bitfld.long 0x00 15. " ERRATIM ,Erratic error interrupt mask" "Masked,Unmasked" endif textline " " bitfld.long 0x00 11.--12. " PFIVL ,Periodic frame interval" "80%,85%,90%,95%" hexmask.long.byte 0x00 4.--10. 0x10 " DAD ,Device address" textline " " bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "Received OUT,STALL" bitfld.long 0x00 0.--1. " DSPD ,Device speed" ",,,Full-speed" line.long 0x04 "OTG_DCTL,OTG Device Control Register" bitfld.long 0x04 18. " DSBESLRJCT ,Deep sleep BESL reject" "Not rejected,Rejected" bitfld.long 0x04 11. " POPRGDNE ,Power-on programming done - indicates that register programming is completed" "Not completed,Completed" bitfld.long 0x04 10. " CGONAK ,Clear global OUT NAK" "No effect,Clear" bitfld.long 0x04 9. " SGONAK ,Set global OUT NAK" "No effect,Set" textline " " bitfld.long 0x04 8. " CGINAK ,Clear global IN NAK" "No effect,Clear" bitfld.long 0x04 7. " SGINAK ,Set global IN NAK" "No effect,Set" bitfld.long 0x04 4.--6. " TCTL ,Test control" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." rbitfld.long 0x04 3. " GONSTS ,Global OUT NAK status" "Handshake sent,No data" textline " " rbitfld.long 0x04 2. " GINSTS ,Global IN NAK status" "Handshake sent,NAK handshake" bitfld.long 0x04 1. " SDIS ,Soft disconnect" "Normal op,Dev disconnect" bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "No rem wakeup,Rem wakeup" rgroup.long 0x808++0x03 line.long 0x00 "OTG_DSTS,OTG Device Status Register" bitfld.long 0x00 23. " DEVLNSTS ,Device line status. Logic level of D+" "0,1" bitfld.long 0x00 22. " DEVLNSTS ,Device line status. Logic level of D-" "0,1" hexmask.long.word 0x00 8.--21. 1. " FNSOF ,Frame number of the received SOF" textline " " bitfld.long 0x00 3. " EERR ,Erratic error" "No error,Error" bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" ",,,Full-speed" bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended" group.long 0x810++0x07 line.long 0x00 "OTG_DIEPMSK,OTG Device IN Endpoint Common Interrupt Mask Register" bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked" bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked" bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked" bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when Tx FIFO empty mask" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " TOM ,Timeout condition mask (Non-isochronous endpoints)" "Masked,Unmasked" bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" line.long 0x04 "OTG_DOEPMSK,OTG Device OUT Endpoint Common Interrupt Mask Register" bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked" bitfld.long 0x04 3. " STUPM ,SETUP phase done mask" "Masked,Unmasked" bitfld.long 0x04 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" rgroup.long 0x818++0x03 line.long 0x00 "OTG_DAINT,OTG Device All Endpoints Interrupt Register" bitfld.long 0x00 31. " OEPINT[15] ,OUT endpoint interrupt bit 15" "No interrupt,Interrupt" bitfld.long 0x00 30. " [14] ,OUT endpoint interrupt bit 14" "No interrupt,Interrupt" bitfld.long 0x00 29. " [13] ,OUT endpoint interrupt bit 13" "No interrupt,Interrupt" bitfld.long 0x00 28. " [12] ,OUT endpoint interrupt bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " [11] ,OUT endpoint interrupt bit 11" "No interrupt,Interrupt" bitfld.long 0x00 26. " [10] ,OUT endpoint interrupt bit 10" "No interrupt,Interrupt" bitfld.long 0x00 25. " [9] ,OUT endpoint interrupt bit 9" "No interrupt,Interrupt" bitfld.long 0x00 24. " [8] ,OUT endpoint interrupt bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " [7] ,OUT endpoint interrupt bit 7" "No interrupt,Interrupt" bitfld.long 0x00 22. " [6] ,OUT endpoint interrupt bit 6" "No interrupt,Interrupt" bitfld.long 0x00 21. " [5] ,OUT endpoint interrupt bit 5" "No interrupt,Interrupt" bitfld.long 0x00 20. " [4] ,OUT endpoint interrupt bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " [3] ,OUT endpoint interrupt bit 3" "No interrupt,Interrupt" bitfld.long 0x00 18. " [2] ,OUT endpoint interrupt bit 2" "No interrupt,Interrupt" bitfld.long 0x00 17. " [1] ,OUT endpoint interrupt bit 1" "No interrupt,Interrupt" bitfld.long 0x00 16. " [0] ,OUT endpoint interrupt bit 0" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IEPINT[15] ,IN endpoint interrupt bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,IN endpoint interrupt bit 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,IN endpoint interrupt bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,IN endpoint interrupt bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " [11] ,IN endpoint interrupt bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,IN endpoint interrupt bit 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,IN endpoint interrupt bit 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,IN endpoint interrupt bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " [7] ,IN endpoint interrupt bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,IN endpoint interrupt bit 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,IN endpoint interrupt bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,IN endpoint interrupt bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " [3] ,IN endpoint interrupt bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,IN endpoint interrupt bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,IN endpoint interrupt bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,IN endpoint interrupt bit 0" "No interrupt,Interrupt" group.long 0x81C++0x03 line.long 0x00 "OTG_DAINTMSK,OTG All Endpoints Interrupt Mask Register" bitfld.long 0x00 31. " OEPM[15] ,OUT EP interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 30. " [14] ,OUT EP interrupt mask bit 14" "Masked,Unmasked" bitfld.long 0x00 29. " [13] ,OUT EP interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 28. " [12] ,OUT EP interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 27. " [11] ,OUT EP interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 26. " [10] ,OUT EP interrupt mask bit 10" "Masked,Unmasked" bitfld.long 0x00 25. " [9] ,OUT EP interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 24. " [8] ,OUT EP interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 23. " [7] ,OUT EP interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 22. " [6] ,OUT EP interrupt mask bit 6" "Masked,Unmasked" bitfld.long 0x00 21. " [5] ,OUT EP interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 20. " [4] ,OUT EP interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 19. " [3] ,OUT EP interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 18. " [2] ,OUT EP interrupt mask bit 2" "Masked,Unmasked" bitfld.long 0x00 17. " [1] ,OUT EP interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 16. " [0] ,OUT EP interrupt mask bit 0" "Masked,Unmasked" textline " " bitfld.long 0x00 15. " IEPM[15] ,IN EP interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " [14] ,IN EP interrupt mask bit 14" "Masked,Unmasked" bitfld.long 0x00 13. " [13] ,IN EP interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " [12] ,IN EP interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " [11] ,IN EP interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " [10] ,IN EP interrupt mask bit 10" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,IN EP interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,IN EP interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " [7] ,IN EP interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " [6] ,IN EP interrupt mask bit 6" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,IN EP interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,IN EP interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " [3] ,IN EP interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " [2] ,IN EP interrupt mask bit 2" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,IN EP interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,IN EP interrupt mask bit 0" "Masked,Unmasked" group.long 0x828++0x07 line.long 0x00 "OTG_DVBUSDIS,OTG Device VBUS Discharge Time Register" hexmask.long.word 0x00 0.--15. 1. " VBUSDT ,Device VBUS discharge time" line.long 0x04 "OTG_DVBUSPULSE,OTG Device VBUS Pulsing Time Register" hexmask.long.word 0x04 0.--11. 1. " DVBUSP ,Device VBUS pulsing time" group.long 0x834++0x03 line.long 0x00 "OTG_DIEPEMPMSK,OTG Device IN Endpoint FIFO Empty Interrupt Mask Register" bitfld.long 0x00 15. " INEPTXFEM[15] ,IN EP Tx FIFO empty interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " [14] ,IN EP Tx FIFO empty interrupt mask bit 14" "Masked,Unmasked" bitfld.long 0x00 13. " [13] ,IN EP Tx FIFO empty interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " [12] ,IN EP Tx FIFO empty interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " [11] ,IN EP Tx FIFO empty interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " [10] ,IN EP Tx FIFO empty interrupt mask bit 10" "Masked,Unmasked" bitfld.long 0x00 9. " [9] ,IN EP Tx FIFO empty interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " [8] ,IN EP Tx FIFO empty interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " [7] ,IN EP Tx FIFO empty interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " [6] ,IN EP Tx FIFO empty interrupt mask bit 6" "Masked,Unmasked" bitfld.long 0x00 5. " [5] ,IN EP Tx FIFO empty interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " [4] ,IN EP Tx FIFO empty interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " [3] ,IN EP Tx FIFO empty interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " [2] ,IN EP Tx FIFO empty interrupt mask bit 2" "Masked,Unmasked" bitfld.long 0x00 1. " [1] ,IN EP Tx FIFO empty interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " [0] ,IN EP Tx FIFO empty interrupt mask bit 0" "Masked,Unmasked" endif tree "OTG device IN and OUT endpoints control registers" if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x900++0x03 line.long 0x00 "OTG_DIEPCTL0,OTG Device Control IN Endpoint 0 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake" rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "0,?..." rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" ",Always active" bitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64b,32b,16b,8b" endif if (((per.l(ad:0x50000000+0x920+0x0))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x920++0x03 line.long 0x00 "OTG_DIEPCTL1,OTG Device IN Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x0))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x920++0x03 line.long 0x00 "OTG_DIEPCTL1,OTG Device IN Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x0))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x920++0x03 line.long 0x00 "OTG_DIEPCTL1,OTG Device IN Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0x920+0x20))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x940++0x03 line.long 0x00 "OTG_DIEPCTL2,OTG Device IN Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x20))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x940++0x03 line.long 0x00 "OTG_DIEPCTL2,OTG Device IN Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x20))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x940++0x03 line.long 0x00 "OTG_DIEPCTL2,OTG Device IN Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0x920+0x40))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x960++0x03 line.long 0x00 "OTG_DIEPCTL3,OTG Device IN Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x40))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x960++0x03 line.long 0x00 "OTG_DIEPCTL3,OTG Device IN Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x40))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x960++0x03 line.long 0x00 "OTG_DIEPCTL3,OTG Device IN Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0x920+0x60))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x980++0x03 line.long 0x00 "OTG_DIEPCTL4,OTG Device IN Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x60))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x980++0x03 line.long 0x00 "OTG_DIEPCTL4,OTG Device IN Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x60))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x980++0x03 line.long 0x00 "OTG_DIEPCTL4,OTG Device IN Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0x920+0x80))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x9A0++0x03 line.long 0x00 "OTG_DIEPCTL5,OTG Device IN Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x80))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x9A0++0x03 line.long 0x00 "OTG_DIEPCTL5,OTG Device IN Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0x920+0x80))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x9A0++0x03 line.long 0x00 "OTG_DIEPCTL5,OTG Device IN Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,Tx FIFO number" "0,1,2,3,4,5,?..." bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB00++0x03 line.long 0x00 "OTG_DOEPCTL0,OTG Device Control OUT Endpoint 0 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "Enabled,Disabled" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No STALL,STALL handshake" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "0,?..." rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" ",Always active" rbitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64b,32b,16b,8b" endif if (((per.l(ad:0x50000000+0xB20+0x0))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB20++0x03 line.long 0x00 "OTG_DOEPCTL1,OTG Device OUT Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x0))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB20++0x03 line.long 0x00 "OTG_DOEPCTL1,OTG Device OUT Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "No effect,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "No effect,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x0))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB20++0x03 line.long 0x00 "OTG_DOEPCTL1,OTG Device OUT Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0xB20+0x20))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB40++0x03 line.long 0x00 "OTG_DOEPCTL2,OTG Device OUT Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x20))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB40++0x03 line.long 0x00 "OTG_DOEPCTL2,OTG Device OUT Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "No effect,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "No effect,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x20))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB40++0x03 line.long 0x00 "OTG_DOEPCTL2,OTG Device OUT Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0xB20+0x40))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB60++0x03 line.long 0x00 "OTG_DOEPCTL3,OTG Device OUT Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x40))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB60++0x03 line.long 0x00 "OTG_DOEPCTL3,OTG Device OUT Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "No effect,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "No effect,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x40))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB60++0x03 line.long 0x00 "OTG_DOEPCTL3,OTG Device OUT Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0xB20+0x60))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB80++0x03 line.long 0x00 "OTG_DOEPCTL4,OTG Device OUT Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x60))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB80++0x03 line.long 0x00 "OTG_DOEPCTL4,OTG Device OUT Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "No effect,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "No effect,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x60))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xB80++0x03 line.long 0x00 "OTG_DOEPCTL4,OTG Device OUT Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif if (((per.l(ad:0x50000000+0xB20+0x80))&0xC0000)==0x40000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xBA0++0x03 line.long 0x00 "OTG_DOEPCTL5,OTG Device OUT Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "No effect,Odd frame set" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "No effect,Even frame set" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x80))&0x80000)==0x80000) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xBA0++0x03 line.long 0x00 "OTG_DOEPCTL5,OTG Device OUT Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "No effect,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "No effect,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif (((per.l(ad:0x50000000+0xB20+0x80))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0xBA0++0x03 line.long 0x00 "OTG_DOEPCTL5,OTG Device OUT Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No priority,STALL priority" bitfld.long 0x00 20. " SNPM ,Snoop mode" "No Snoop,Snoop mode" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK handshakes,NAK handshakes" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Inactive,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif tree.end tree "OTG_FS device IN and OUT endpoints interrupt registers" if (((per.l((ad:0x50000000+0x900+0x0)))&0xC0000)==0x0) if (((per.l(ad:0x50000000+0x14))&0x1)==0x0) group.long 0x908++0x03 line.long 0x00 "OTG_DIEPINT0,OTG Device IN Endpoint-0 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" ">Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=Half full,=