; -------------------------------------------------------------------------------- ; @Title: STM32L0 On-Chip Peripherals ; @Props: Released ; @Author: KNO, BGA, STR, JAM ; @Changelog: 2016-11-07 BGA ; 2017-05-20 STR ; 2019-01-23 JAM ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: 13902.pdf ; 15056.pdf ; 13259.pdf ; 14610.pdf ; 14611.pdf ; 13587.pdf ; 13586.pdf ; 15057.pdf ; 15058.pdf ; 15060.pdf ; 13902.pdf ; 16188.pdf ; 13259.pdf ; 16211.pdf ; 16455.pdf ; 17143.pdf ; 17144.pdf ; CD00264852.pdf ; 15274.pdf ; RM0008_STM32_connectivity_02.pdf ; CD00161561.pdf (2011-04) ; CD00161566.pdf (2011-04) ; CD00171190.pdf (2011-10) ; CD00212417.pdf (2012-06) ; CD00246267.pdf (2012-07) ; @Core: Cortex-M0+ ; @Chip: STM32L011D3, STM32L011D4, STM32L011E3, STM32L011E4, STM32L011F3, ; STM32L011F4, STM32L011G3, STM32L011G4, STM32L011K3, STM32L011K4, ; STM32L021D4, STM32L021F4, STM32L021G4, STM32L021K4, STM32L031C4, ; STM32L031C6, STM32L031E4, STM32L031E6, STM32L031F4, STM32L031F6, ; STM32L031G4, STM32L031G6, STM32L031K4, STM32L031K6, STM32L041C6, ; STM32L041F6, STM32L041G6, STM32L041K6, STM32L071C8, STM32L071CB, ; STM32L071CZ, STM32L071K8, STM32L071KB, STM32L071KZ, STM32L071RB, ; STM32L071RZ, STM32L071V8, STM32L071VB, STM32L071VZ, STM32L072CB, ; STM32L072KB, STM32L072KZ, STM32L072RB, STM32L072RZ, STM32L072V8, ; STM32L072VB, STM32L072VZ, STM32L073CB, STM32L073CZ, STM32L073RB, ; STM32L073RZ, STM32L073V8, STM32L073VB, STM32L073VZ, STM32L081CZ, ; STM32L081KZ, STM32L082KB, STM32L082KZ, STM32L083CB, STM32L083CZ, ; STM32L083RB, STM32L083RZ ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32l0.per 10148 2019-01-31 15:57:05Z mkolodziejczyk $ ; Known problems: ; MODULE REGISTER DESCRIPTION ; COMP Missing BASEADRESS - module commented ; GPIO A Pin number differences, depending on chip package. Unable to define completely due to limited chip number. Highest possible number of pins listed. ; GPIO B Pin number differences, depending on chip package. Unable to define completely due to limited chip number. Highest possible number of pins listed ; TSC No convinient information about number of channels. Highest possible number listed config 16. 8. tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "FLASH (Flash Memory and data EEPROM)" base ad:0x40022000 width 15. group.long 0x00++0x03 line.long 0x00 "FLASH_ACR,Flash access control register" bitfld.long 0x00 6. " PRE_READ ,Memory interface stores the last address read as data and tries to read the next one when no other read or write or prefetch operation is ongoing" "Disabled,Enabled" bitfld.long 0x00 5. " DISAB_BUF ,Buffers used as cache during a read disable" "No,Yes" bitfld.long 0x00 4. " RUN_PD ,NVM working mode when device is in run mode" "Idle,Power-down" bitfld.long 0x00 3. " SLEEP_PD ,NVM working mode when device is in sleep mode" "Idle,Power-down" textline " " bitfld.long 0x00 1. " PRFTEN ,Prefetch" "Disabled,Enabled" bitfld.long 0x00 0. " LATENCY ,Latency" "Zero wait state,One wait state" if ((per.l(ad:0x40022000+0x04)&0x05)==0x00) group.long 0x04++0x03 line.long 0x00 "FLASH_PECR,Program and erase control register" sif ((!cpuis("STM32L051*"))&&(!cpuis("STM32L052*"))&&(!cpuis("STM32L053*"))&&(!cpuis("STM32L062*"))&&(!cpuis("STM32L063*"))) bitfld.long 0x00 23. " NZDISABLE ,Non-Zero check notification disable" "No,Yes" textline " " endif bitfld.long 0x00 18. " OBL_LAUNCH ,Option byte loading" "Completed,Not completed" bitfld.long 0x00 17. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " EOPIE ,End of programming interrupt enable" "Disabled,Enabled" textline " " sif ((cpuis("STM32L07*"))||(cpuis("STM32L08*"))) bitfld.long 0x00 15. " PARALLELBANK ,Parallel bank programming mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 10. " FPRG ,Half Page programming mode" "Disabled,Enabled" bitfld.long 0x00 9. " ERASE ,Erase operation request" "Not requested,Requested" bitfld.long 0x00 8. " FIX ,Erase phase" "When necessary,Always" textline " " bitfld.long 0x00 4. " DATA ,Data EEPROM" "Not selected,Selected" bitfld.long 0x00 3. " PROG ,The Flash program memory" "Not selected,Selected" bitfld.long 0x00 2. " OPT_LOCK ,The write and erase operations in the Option bytes area" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PRG_LOCK ,The write and erase operations in the Flash program memory" "Disabled,Enabled" bitfld.long 0x00 0. " PE_LOCK ,FLASH_PECR lock" "Unlocked,Locked" elif ((per.l(ad:0x40022000+0x04)&0x05)==0x04) group.long 0x04++0x03 line.long 0x00 "FLASH_PECR,Program and erase control register" sif ((!cpuis("STM32L051*"))&&(!cpuis("STM32L052*"))&&(!cpuis("STM32L053*"))&&(!cpuis("STM32L062*"))&&(!cpuis("STM32L063*"))) bitfld.long 0x00 23. " NZDISABLE ,Non-Zero check notification disable" "No,Yes" textline " " endif rbitfld.long 0x00 18. " OBL_LAUNCH ,Option byte loading" "Completed,Not completed" bitfld.long 0x00 17. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " EOPIE ,End of programming interrupt enable" "Disabled,Enabled" textline " " sif ((cpuis("STM32L07*"))||(cpuis("STM32L08*"))) bitfld.long 0x00 15. " PARALLELBANK ,Parallel bank programming mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 10. " FPRG ,Half Page programming mode" "Disabled,Enabled" bitfld.long 0x00 9. " ERASE ,Erase operation request" "Not requested,Requested" bitfld.long 0x00 8. " FIX ,Erase phase" "When necessary,Always" textline " " bitfld.long 0x00 4. " DATA ,Data EEPROM" "Not selected,Selected" bitfld.long 0x00 3. " PROG ,The Flash program memory" "Not selected,Selected" bitfld.long 0x00 2. " OPT_LOCK ,The write and erase operations in the Option bytes area" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PRG_LOCK ,The write and erase operations in the Flash program memory" "Disabled,Enabled" bitfld.long 0x00 0. " PE_LOCK ,FLASH_PECR lock" "Unlocked,Locked" else group.long 0x04++0x03 line.long 0x00 "FLASH_PECR,Program and erase control register" sif ((!cpuis("STM32L051*"))&&(!cpuis("STM32L052*"))&&(!cpuis("STM32L053*"))&&(!cpuis("STM32L062*"))&&(!cpuis("STM32L063*"))) rbitfld.long 0x00 23. " NZDISABLE ,Non-Zero check notification disable" "No,Yes" textline " " endif rbitfld.long 0x00 18. " OBL_LAUNCH ,Option byte loading" "Completed,Not completed" rbitfld.long 0x00 17. " ERRIE ,Error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16. " EOPIE ,End of programming interrupt enable" "Disabled,Enabled" textline " " sif ((cpuis("STM32L07*"))||(cpuis("STM32L08*"))) bitfld.long 0x00 15. " PARALLELBANK ,Parallel bank programming mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 10. " FPRG ,Half Page programming mode" "Disabled,Enabled" rbitfld.long 0x00 9. " ERASE ,Erase operation request" "Not requested,Requested" rbitfld.long 0x00 8. " FIX ,Erase phase" "When necessary,Always" textline " " rbitfld.long 0x00 4. " DATA ,Data EEPROM" "Not selected,Selected" rbitfld.long 0x00 3. " PROG ,The Flash program memory" "Not selected,Selected" bitfld.long 0x00 2. " OPT_LOCK ,The write and erase operations in the Option bytes area" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PRG_LOCK ,The write and erase operations in the Flash program memory" "Disabled,Enabled" bitfld.long 0x00 0. " PE_LOCK ,FLASH_PECR lock" "Unlocked,Locked" endif wgroup.long 0x08++0x0F line.long 0x00 "FLASH_PDKEYR,Power-down key register" line.long 0x04 "FLASH_PEKEYR,PECR unlock key register" line.long 0x08 "FLASH_PRGKEYR,Program and erase key register" line.long 0x0C "FLASH_OPTKEYR,Option bytes unlock key register" group.long 0x18++0x03 line.long 0x00 "FLASH_SR,Status register" eventfld.long 0x00 17. " FWWERR ,Write/Erase operation abort to perform a fetch" "Disabled,Enabled" eventfld.long 0x00 16. " NOTZEROERR ,Region of memory where write operation is performed" "In erased region,In not erased region" eventfld.long 0x00 13. " RDERR ,Read protection error" "Not occurred,One occurred" eventfld.long 0x00 12. " OPTVERRUSR ,Error during the Option byte User loading" "Not occurred,At least one occurred" eventfld.long 0x00 11. " OPTVERR ,Error during the Option bytes loading" "Not occurred,At least one occurred" textline " " eventfld.long 0x00 10. " SIZERR ,Size error" "Not occurred,Occurred" eventfld.long 0x00 9. " PGAERR ,Programming alignment error" "Not occurred,Occurred" eventfld.long 0x00 8. " WRPERR ,Write protection error" "Not occurred,One occurred" rbitfld.long 0x00 3. " READY ,NVM readiness for read and write/erase operations" "Disabled,Enabled" textline " " rbitfld.long 0x00 2. " ENDHV ,High voltage for write/erase operations execution" "On,Off" eventfld.long 0x00 1. " EOP ,End of program" "Not occurred,One occurred" rbitfld.long 0x00 0. " BSY ,Memory interface busy" "Not busy,Busy" sif ((cpuis("STM32L011*"))||cpuis("STM32L021*")) if (((per.l(ad:0x40022000+0x1C))&0x20000000)==0x20000000) rgroup.long 0x1C++0x03 line.long 0x00 "FLASH_OPTR,Option bytes register" bitfld.long 0x00 30.--31. " NBOOT ,Memory boot source" "Embedded SRAM,Flash,System memory,Flash" bitfld.long 0x00 29. " NBOOT_SEL ,BOOT0 Signal Definition Selcection" "BOOT0 pin,nBOOT" textline " " bitfld.long 0x00 23. " BFB2 ,BOOT Source Selection" "User flash memory,System memory" bitfld.long 0x00 22. " NRST_STDBY ,Reset generation" "Standby enter,No reset" bitfld.long 0x00 21. " NRST_STOP ,Reset generation" "Stop mode enter,No reset" bitfld.long 0x00 20. " WDG_SW ,Watchdog Configuration" "Hardware,Software" textline " " bitfld.long 0x00 16.--19. " BOR_LEV ,Brown out reset threshold level" "Off,Off,Off,Off,Off,Off,Off,Off,Level 0,Level 1,Level 2,Level 3,Level 4,?..." bitfld.long 0x00 8. " WPRMOD ,Write and read protection of Flash program memory sectors" "Write protection,Read protection" hexmask.long.byte 0x00 0.--7. 0x01 " RDPROT ,Read protection" else rgroup.long 0x1C++0x03 line.long 0x00 "FLASH_OPTR,Option bytes register" bitfld.long 0x00 31. " NBOOT1 ,Memory boot source [BOOT0 pin == 0/BOOT0 pin == 1]" "Flash/Embedded SRAM,Flash/System memory" textline " " bitfld.long 0x00 23. " BFB2 ,BOOT Source Selection" "User flash memory,System memory" bitfld.long 0x00 22. " NRST_STDBY ,Reset generation" "Standby enter,No reset" bitfld.long 0x00 21. " NRST_STOP ,Reset generation" "Stop mode enter,No reset" bitfld.long 0x00 20. " WDG_SW ,Watchdog Configuration" "Hardware,Software" textline " " bitfld.long 0x00 16.--19. " BOR_LEV ,Brown out reset threshold level" "Off,Off,Off,Off,Off,Off,Off,Off,Level 0,Level 1,Level 2,Level 3,Level 4,?..." bitfld.long 0x00 8. " WPRMOD ,Write and read protection of Flash program memory sectors" "Write protection,Read protection" hexmask.long.byte 0x00 0.--7. 0x01 " RDPROT ,Read protection" endif else rgroup.long 0x1C++0x03 line.long 0x00 "FLASH_OPTR,Option bytes register" bitfld.long 0x00 31. " NBOOT1 ,Memory boot source [BOOT0 pin == 0/BOOT0 pin == 1]" "Flash/Embedded SRAM,Flash/System memory" sif ((cpuis("STM32L07*"))||(cpuis("STM32L08*"))) bitfld.long 0x00 23. " BFB2 ,BOOT Source Selection" "Bank 1,System memory" else bitfld.long 0x00 23. " BFB2 ,BOOT Source Selection" "USER flash memory,System memory" endif textline " " bitfld.long 0x00 22. " NRST_STDBY ,Reset generation" "Standby enter,No reset" bitfld.long 0x00 21. " NRST_STOP ,Reset generation" "Stop mode enter,No reset" bitfld.long 0x00 20. " WDG_SW ,Watchdog Configuration" "Hardware,Software" textline " " bitfld.long 0x00 16.--19. " BOR_LEV ,Brown out reset threshold level" "Off,Off,Off,Off,Off,Off,Off,Off,Level 0,Level 1,Level 2,Level 3,Level 4,?..." bitfld.long 0x00 8. " WPRMOD ,Write and read protection of Flash program memory sectors" "Write protection,Read protection" hexmask.long.byte 0x00 0.--7. 0x01 " RDPROT ,Read protection" endif rgroup.long 0x20++0x03 line.long 0x00 "FLASH_WRPROT1,Write protection register 1" rgroup.long 0x80++0x03 line.long 0x00 "FLASH_WRPROT1,Write protection register 2" width 0x0B tree.end tree "CRC (Cyclic redundancy check calculation unit)" base ad:0x40023000 width 10. group.long 0x00++0x0B line.long 0x00 "CRC_DR, Data register" line.long 0x04 "CRC_IDR, Independent data register" hexmask.byte 0x04 0.--7. 0x01 " IDR[7:0] ,General-purpose 8-bit data register bits" line.long 0x08 "CRC_CR, Control register" bitfld.long 0x08 7. " REV_OUT ,Reverse output data" "Not affected,Reversed" bitfld.long 0x08 5.--6. " REV_IN[1:0] ,Reverse input data" "Not affected,By byte,By half-word,By word" bitfld.long 0x08 3.--4. " POLYSIZE[1:0] ,Polynomial size" "32 bit,16-bit,8-bit,7-bit" bitfld.long 0x08 0. " RESET , Reset CRC bit" "No reset,Reset" group.long 0x10++0x07 line.long 0x00 "CRC_INIT,Initial CRC value" line.long 0x04 "CRC_POL,CRC polynomial" width 0xB tree.end sif ((cpuis("STM32L051*"))||(cpuis("STM32L052*"))||(cpuis("STM32L053*"))||(cpuis("STM32L062*"))||(cpuis("STM32L063*"))||(cpuis("STM32L07*"))||(cpuis("STM32L08*"))) tree "FW (Firewall)" base ad:0x40011C00 width 10. group.long 0x00++0x17 line.long 0x00 "FW_CSSA,Code segment start address" hexmask.long.word 0x00 8.--23. 0x01 " ADD[23:8] ,Code segment start address" line.long 0x04 "FW_CSL,Code segment length" hexmask.long.word 0x04 8.--21. 0x01 " LENG[23:8] ,Code segment length" line.long 0x08 "FW_NVDSSA,Non-volatile data segment start address" hexmask.long.word 0x08 8.--23. 0x01 " ADD[23:8] ,Non-volatile data segment start address" line.long 0x0C "FW_NVDSL,Non-volatile data segment length" hexmask.long.word 0x0C 8.--23. 0x01 " LENG[21:8] ,Non-volatile data segment length" line.long 0x10 "FW_VDSSA,Volatile data segment start address" hexmask.long.word 0x10 6.--15. 0x40 " ADD[15:6] ,Volatile data segment start address" line.long 0x14 "FW_VDSL,Volatile data segment length" hexmask.long.word 0x14 6.--15. 0x40 " LENG[15:6] ,Non-volatile data segment length" if ((per.l(ad:0x40011C00+0x20))&0x02)==0x02 group.long 0x20++0x03 line.long 0x00 "FW_CR,Configuration register" bitfld.long 0x00 1. " VDS ,Volatile data shared" "Not shared,Shared" bitfld.long 0x00 0. " FPA ,Firewall pre alarm" "Disabled(Reset),Enabled" else group.long 0x20++0x03 line.long 0x00 "FW_CR,Configuration register" bitfld.long 0x00 2. " VDE ,Volatile data execution enable" "Disabled,Enabled" bitfld.long 0x00 1. " VDS ,Volatile data shared" "Not shared,Shared" bitfld.long 0x00 0. " FPA ,Firewall pre alarm" "Disabled(Reset),Enabled" endif width 0x0B tree.end endif tree "PWR (Power Control Register)" base ad:0x40007000 width 9. sif CPUIS("STM32L0?1*") if ((per.l(ad:0x40007000))&0x01)==0x01 group.long 0x00++0x03 line.long 0x00 "PWR_CR,Power control register" textline " " bitfld.long 0x00 14. " LPRUN ,Voltage regulator low power run mode" "Main mode,Low power mode" bitfld.long 0x00 13. " DS_EE_KOFF ,Deep-sleep mode with Flash memory kept off" "Disabled,Enabled" bitfld.long 0x00 11.--12. " VOS[1:0] ,Voltage scaling range selection" ",1.8V,1.5V,1.2V" bitfld.long 0x00 10. " FWU ,Fast wakeup" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ULP ,Ultralow power mode" "VREFINT on,VREFINT off" bitfld.long 0x00 8. " DBP ,Backup Domain write protection" "Enabled,Disabled" bitfld.long 0x00 5.--7. " PLS ,PVD Level Selection" "1.9 V,2.1 V,2.3 V,2.5 V,2.7 V,2.9 V,3.1 V,External" bitfld.long 0x00 4. " PVDE ,Power Voltage Detector Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Clear" eventfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Clear" bitfld.long 0x00 1. " PDDS ,Power Down Deepsleep" "Stop,Standby" bitfld.long 0x00 0. " LPSDSR ,Low-power deepsleep/sleep/low power run" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "PWR_CR,Power control register" bitfld.long 0x00 16. " LPDS ,Low-power deepsleep regulator mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " LPRUN ,Voltage regulator low power run mode" "Main mode,Low power mode" bitfld.long 0x00 13. " DS_EE_KOFF ,Deep-sleep mode with Flash memory kept off" "Disabled,Enabled" bitfld.long 0x00 11.--12. " VOS[1:0] ,Voltage scaling range selection" ",1.8V,1.5V,1.2V" bitfld.long 0x00 10. " FWU ,Fast wakeup" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ULP ,Ultralow power mode" "VREFINT on,VREFINT off" bitfld.long 0x00 8. " DBP ,Backup Domain write protection" "Enabled,Disabled" bitfld.long 0x00 5.--7. " PLS ,PVD Level Selection" "1.9 V,2.1 V,2.3 V,2.5 V,2.7 V,2.9 V,3.1 V,External" bitfld.long 0x00 4. " PVDE ,Power Voltage Detector Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Clear" eventfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Clear" bitfld.long 0x00 1. " PDDS ,Power Down Deepsleep" "Stop,Standby" bitfld.long 0x00 0. " LPSDSR ,Low-power deepsleep/sleep/low power run" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "PWR_CR,Power control register" bitfld.long 0x00 14. " LPRUN ,Voltage regulator low power run mode" "Main mode,Low power mode" bitfld.long 0x00 13. " DS_EE_KOFF ,Deep-sleep mode with Flash memory kept off" "Disabled,Enabled" bitfld.long 0x00 11.--12. " VOS[1:0] ,Voltage scaling range selection" ",1.8V,1.5V,1.2V" bitfld.long 0x00 10. " FWU ,Fast wakeup" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ULP ,Ultralow power mode" "VREFINT on,VREFINT off" bitfld.long 0x00 8. " DBP ,Backup Domain write protection" "Enabled,Disabled" bitfld.long 0x00 5.--7. " PLS ,PVD Level Selection" "1.9 V,2.1 V,2.3 V,2.5 V,2.7 V,2.9 V,3.1 V,External" bitfld.long 0x00 4. " PVDE ,Power Voltage Detector Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Clear" eventfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Clear" bitfld.long 0x00 1. " PDDS ,Power Down Deepsleep" "Stop,Standby" bitfld.long 0x00 0. " LPSDSR ,Low-power deepsleep/sleep/low power run" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "PWR_CSR,Power control/status register" bitfld.long 0x00 10. " EWUP3 ,WKUP pin 3 purpose" "GPIO,Wake-up" bitfld.long 0x00 9. " EWUP2 ,Enable WKUP pin 2 purpose" "GPIO,Wake-up" bitfld.long 0x00 8. " EWUP1 ,Enable WKUP pin 1 purpose" "GPIO,Wake-up" rbitfld.long 0x00 5. " REGLPF ,Regulator LP flag" "Main mode,Low-power mode" textline " " rbitfld.long 0x00 4. " VOSF ,Voltage Scaling select flag" "Ready,Changing" rbitfld.long 0x00 3. " VREFINTRDYF ,Internal voltage reference" "OFF,Ready" rbitfld.long 0x00 2. " PVDO ,PVD Output" "VDD>PVD threshold,VDD=0x101)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000000+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000000)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " endif if ((((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000000+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000000+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif if ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Output compare ch1 ch2 ch3 ch4 enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM2_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM2_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM2_ARR,Auto-reload register" if (((per.w((ad:0x40000000+0x18)))&0x03)!=0x00) group.word 0x34++0x1 line.word 0x00 "TIM2_CCR1,Low input capture register 1" else group.word 0x34++0x1 line.word 0x00 "TIM2_CCR1,Low output compare register 1" endif if (((per.w((ad:0x40000000+0x18)))&0x300)!=0x000) group.word 0x38++0x1 line.word 0x00 "TIM2_CCR2,Low input capture register 2" else group.word 0x38++0x1 line.word 0x00 "TIM2_CCR2,Low output compare register 2" endif if (((per.w((ad:0x40000000+0x1C)))&0x3)!=0x00) group.word 0x3C++0x1 line.word 0x00 "TIM2_CCR3,Low input capture register 3" else group.word 0x3C++0x1 line.word 0x00 "TIM2_CCR3,Low output compare register 3" endif if (((per.w((ad:0x40000000+0x1C)))&0x300)!=0x000) group.word 0x3C++0x1 line.word 0x00 "TIM2_CCR4,Low input capture register 4" else group.word 0x3C++0x1 line.word 0x00 "TIM2_CCR4,Low output compare register 4" endif group.word 0x48++0x1 line.word 0x00 "TIM2_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,..." group.word 0x4C++0x1 line.word 0x00 "TIM2_DMAR,DMA address for full transfer" group.word 0x50++0x1 line.word 0x00 "TIM2_OR,TIM2 option register" bitfld.word 0x00 3.--4. " TI4_RMP ,Internal trigger remap" "TI4 input connected to ORed GPIOs,TI4 input connected to COMP2_OUT,TI4 input connected to COMP1_OUT,TI4 input connected to ORed GPIOs" bitfld.word 0x00 0.--2. " ETR_RMP ,Timer2 ETR remap" "ORed GPIOs,ORed GPIOs,ORed GPIOs,HSI16,HSI48,LSE,COMP2_OUT,COMP1_OUT" width 0xB tree.end sif ((cpu()=="STM32L071C8")||(cpu()=="STM32L071CB")||(cpu()=="STM32L071CZ")||(cpu()=="STM32L071K8")||(cpu()=="STM32L071KB")||(cpu()=="STM32L071KZ")||(cpu()=="STM32L071RB")||(cpu()=="STM32L071RZ")||(cpu()=="STM32L071V8")||(cpu()=="STM32L071VB")||(cpu()=="STM32L071VZ")||(cpu()=="STM32L072CB")||(cpu()=="STM32L072KB")||(cpu()=="STM32L072KZ")||(cpu()=="STM32L072RB")||(cpu()=="STM32L072RZ")||(cpu()=="STM32L072V8")||(cpu()=="STM32L072VB")||(cpu()=="STM32L072VZ")||(cpu()=="STM32L073CB")||(cpu()=="STM32L073CZ")||(cpu()=="STM32L073RB")||(cpu()=="STM32L073RZ")||(cpu()=="STM32L073V8")||(cpu()=="STM32L073VB")||(cpu()=="STM32L073VZ")||(cpu()=="STM32L081CZ")||(cpu()=="STM32L081KZ")||(cpu()=="STM32L082KB")||(cpu()=="STM32L082KZ")||(cpu()=="STM32L083CB")||(cpu()=="STM32L083CZ")||(cpu()=="STM32L083RB")||(cpu()=="STM32L083RZ")) tree "TIMER 3" base ad:0x40000400 width 12. group.word 0x00++0x1 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT," bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Align mode selection" "Edge,Center1,Center2,Center3" bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" textline " " bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request" bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x1 line.word 0x00 "TIM3_CR2,TIM3 Control register 2" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1 directly,CH1/CH2/CH3 xored" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC3,Update" if (((per.w((ad:0x40000400)+0x08))&0x07)==0x00) group.word 0x08++0x1 line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2,ETRF" bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM3_DIER,TIM3 DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM3_SR,TIM3 Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM3_EGR,TIM3 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/Compare 4" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/Compare 3" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/Compare 2" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/Compare 1" bitfld.word 0x00 0. " UG ,Update Generation" "Not generate,Generate" if ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output Compare 2 and Output Compare 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input Capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " elif ((((per.w((ad:0x40000400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40000400)+0x20))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Input capture 2 and input capture 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" textline " " endif if ((((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x00)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1000)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Output compare 3 and Input Capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and output compare 4 mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif ((((per.w((ad:0x40000400+0x1C)))&0x303)>=0x101)&&(((per.w((ad:0x40000400+0x20)))&0x1100)==0x1100)) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Input Capture 3 and input capture 4 mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif if ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Output compare ch1 ch2 ch3 ch4 enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Output compare 4 complementary Polarity" "Output,Input" bitfld.word 0x00 13. " CC4P ,Output Compare 4 Polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Output Compare 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Output Compare 3 complementary Polarity" "Output,Input" bitfld.word 0x00 9. " CC3P ,Output Compare 3 Polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Output Compare 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Input Capture 4 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Input Capture 4 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Input capture 3 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Input capture 3 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM3_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM3_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM3_ARR,Auto-reload register" if (((per.w((ad:0x40000400+0x18)))&0x03)!=0x00) group.word 0x34++0x1 line.word 0x00 "TIM3_CCR1,Low input capture register 1" else group.word 0x34++0x1 line.word 0x00 "TIM3_CCR1,Low output compare register 1" endif if (((per.w((ad:0x40000400+0x18)))&0x300)!=0x000) group.word 0x38++0x1 line.word 0x00 "TIM3_CCR2,Low input capture register 2" else group.word 0x38++0x1 line.word 0x00 "TIM3_CCR2,Low output compare register 2" endif if (((per.w((ad:0x40000400+0x1C)))&0x3)!=0x00) group.word 0x3C++0x1 line.word 0x00 "TIM3_CCR3,Low input capture register 3" else group.word 0x3C++0x1 line.word 0x00 "TIM3_CCR3,Low output compare register 3" endif if (((per.w((ad:0x40000400+0x1C)))&0x300)!=0x000) group.word 0x3C++0x1 line.word 0x00 "TIM3_CCR4,Low input capture register 4" else group.word 0x3C++0x1 line.word 0x00 "TIM3_CCR4,Low output compare register 4" endif group.word 0x48++0x1 line.word 0x00 "TIM3_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,..." group.word 0x4C++0x1 line.word 0x00 "TIM3_DMAR,DMA address for full transfer" group.word 0x50++0x1 line.word 0x00 "TIM3_OR,TIM3 option register" bitfld.word 0x00 4. " TI_RMP[2] ,Timer 3 remapping on PC9" "OSB_OE,TIM3_CH4" bitfld.word 0x00 3. " TI_RMP[1] ,Timer 3 remapping on PB5" "OTIM22_CH2,TIM3_CH2" bitfld.word 0x00 2. " TI_RMP[0] ,Timer 3 TI remap" "USB_SOF,PE3/PA6/PC6/PB4" bitfld.word 0x00 0.--1. " ETR_RMP ,Timer2 ETR remap" "PE2/PD2,PE2/PD2,HSI48/6,PE2/PD2" width 0xB tree.end endif tree "TIMER 21" base ad:0x40010800 width 12. group.word 0x00++0x1 line.word 0x00 "TIM21_CR1,TIM21 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT," bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Align mode selection" "Edge,Center1,Center2,Center3" bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" textline " " bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request" bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x1 line.word 0x00 "TIM21_CR2,TIM21 Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,..." if (((per.w((ad:0x40010800)+0x08))&0x07)==0x00) group.word 0x08++0x1 line.word 0x00 "TIM21_SMCR,TIM21 Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2," bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger," else group.word 0x08++0x1 line.word 0x00 "TIM21_SMCR,TIM21 Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2," bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger," endif group.word 0x0C++0x1 line.word 0x00 "TIM21_DIER,TIM21 DMA/Interrupt enable register" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM21_SR,TIM21 Status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM21_EGR,TIM21 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/Compare 2" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/Compare 1" bitfld.word 0x00 0. " UG ,Update Generation" "Not generate,Generate" if ((((per.w((ad:0x40010800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" rbitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40010800+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40010800+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM21_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif if ((((per.w((ad:0x40010800+0x18)))&0x303)==0x00)) group.word 0x20++0x01 line.word 0x00 "TIM21_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif (((per.w((ad:0x40010800+0x18)))&0x300)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM21_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif (((per.w((ad:0x40010800+0x18)))&0x03)==0x00) group.word 0x20++0x01 line.word 0x00 "TIM21_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif (((per.w((ad:0x40010800+0x18)))&0x303)!=0x00) group.word 0x20++0x01 line.word 0x00 "TIM21_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM21_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM21_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM21_ARR,Auto-reload register" if (((per.w((ad:0x40010800+0x18)))&0x03)!=0x00) group.word 0x34++0x1 line.word 0x00 "TIM21_CCR1,Low input capture register 1" else group.word 0x34++0x1 line.word 0x00 "TIM21_CCR1,Low output compare register 1" endif if (((per.w((ad:0x40010800+0x18)))&0x300)!=0x000) group.word 0x38++0x1 line.word 0x00 "TIM21_CCR2,Low input capture register 2" else group.word 0x38++0x1 line.word 0x00 "TIM21_CCR2,Low output compare register 2" endif group.word 0x50++0x1 line.word 0x00 "TIM21_OR,TIM21 option register" bitfld.word 0x00 5. " TI2_RMP ,Timer21 TI2 (connected to TIM21_CH1) remap" "GPIO,COMP2_OUT" bitfld.word 0x00 2.--4. " TI1_RMP ,Timer21 TI1 (connected to TIM21_CH1) remap" "GPIO,RTC WAKEUP,HSE_RTC,MSI,LSE,LSI,COMP1_OUT,MCO" bitfld.word 0x00 0.--1. " ETR_RMP ,Timer21 ETR remap" "GPIO,COMP2_OUT,COMP1_OUT,LSE" width 0xB tree.end sif ((cpu()!="STM32L011D3")&&(cpu()!="STM32L011D4")&&(cpu()!="STM32L011E3")&&(cpu()!="STM32L011E4")&&(cpu()!="STM32L011F3")&&(cpu()!="STM32L011F4")&&(cpu()!="STM32L011G3")&&(cpu()!="STM32L011G4")&&(cpu()!="STM32L011K3")&&(cpu()!="STM32L011K4")&&(cpu()!="STM32L021D4")&&(cpu()!="STM32L021F4")&&(cpu()!="STM32L021G4")&&(cpu()!="STM32L021K4")) tree "TIMER 22" base ad:0x40011400 width 12. group.word 0x00++0x1 line.word 0x00 "TIM22_CR1,TIM22 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT," bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Align mode selection" "Edge,Center1,Center2,Center3" bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" textline " " bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request" bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x1 line.word 0x00 "TIM22_CR2,TIM22 Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,..." if (((per.w((ad:0x40011400)+0x08))&0x07)==0x00) group.word 0x08++0x1 line.word 0x00 "TIM22_SMCR,TIM22 Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2," bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger," else group.word 0x08++0x1 line.word 0x00 "TIM22_SMCR,TIM22 Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,,,TI1F_ED,TI1FP1,TI2FP2," bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger," endif group.word 0x0C++0x1 line.word 0x00 "TIM22_DIER,TIM22 DMA/Interrupt enable register" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM22_SR,TIM22 Status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM22_EGR,TIM22 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enable" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/Compare 2" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/Compare 1" bitfld.word 0x00 0. " UG ,Update Generation" "Not generate,Generate" if ((((per.w((ad:0x40011400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x00)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x01)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x10)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" rbitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x100||0x200||0x300))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 2 and Output compare 1 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)==(0x001||0x002||0x003))&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Output compare 2 and Input capture 1 mode register 1" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif ((((per.w((ad:0x40011400+0x18)))&0x303)>=0x101)&&(((per.w((ad:0x40011400+0x20)))&0x11)==0x11)) group.word 0x18++0x1 line.word 0x00 "TIM22_CCMR1,Input capture 1 and Input capture 2 mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif if ((((per.w((ad:0x40011400+0x18)))&0x303)==0x00)) group.word 0x20++0x01 line.word 0x00 "TIM22_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif (((per.w((ad:0x40011400+0x18)))&0x300)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM22_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Output Compare 2 complementary Polarity" "Output,Input" bitfld.word 0x00 5. " CC2P ,Output Compare 2 Polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Output Compare 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" elif (((per.w((ad:0x40011400+0x18)))&0x03)==0x00) group.word 0x20++0x01 line.word 0x00 "TIM22_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Output compare 1 complementary Polarity" "Output,Input" bitfld.word 0x00 1. " CC1P ,Output Compare 1 Polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Output Compare 1 enable" "Disabled,Enabled" elif (((per.w((ad:0x40011400+0x18)))&0x303)!=0x00) group.word 0x20++0x01 line.word 0x00 "TIM22_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Input Capture 2 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Input Capture 2 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Input Capture 1 polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Input Capture 1 enable" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM22_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM22_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM22_ARR,Auto-reload register" if (((per.w((ad:0x40011400+0x18)))&0x03)!=0x00) group.word 0x34++0x1 line.word 0x00 "TIM22_CCR1,Low input capture register 1" else group.word 0x34++0x1 line.word 0x00 "TIM22_CCR1,Low output compare register 1" endif if (((per.w((ad:0x40011400+0x18)))&0x300)!=0x000) group.word 0x38++0x1 line.word 0x00 "TIM22_CCR2,Low input capture register 2" else group.word 0x38++0x1 line.word 0x00 "TIM22_CCR2,Low output compare register 2" endif group.word 0x50++0x1 line.word 0x00 "TIM22_OR,TIM22 option register" bitfld.word 0x00 2.--3. " TI1_RMP ,Timer22 TI1 (connected to TIM22_CH1) remap" "GPIO,COMP2_OUT,COMP1_OUT,GPIO" bitfld.word 0x00 0.--1. " ETR_RMP ,Timer21 ETR remap" "GPIO,COMP2_OUT,COMP1_OUT,LSE" width 0xB tree.end endif tree.end sif ((cpu()!="STM32L011D3")&&(cpu()!="STM32L011D4")&&(cpu()!="STM32L011E3")&&(cpu()!="STM32L011E4")&&(cpu()!="STM32L011F3")&&(cpu()!="STM32L011F4")&&(cpu()!="STM32L011G3")&&(cpu()!="STM32L011G4")&&(cpu()!="STM32L011K3")&&(cpu()!="STM32L011K4")&&(cpu()!="STM32L021D4")&&(cpu()!="STM32L021F4")&&(cpu()!="STM32L021G4")&&(cpu()!="STM32L021K4")&&(cpu()!="STM32L031C4")&&(cpu()!="STM32L031C6")&&(cpu()!="STM32L031E4")&&(cpu()!="STM32L031E6")&&(cpu()!="STM32L031F4")&&(cpu()!="STM32L031F6")&&(cpu()!="STM32L031G4")&&(cpu()!="STM32L031G6")&&(cpu()!="STM32L031K4")&&(cpu()!="STM32L031K6")&&(cpu()!="STM32L041C6")&&(cpu()!="STM32L041F6")&&(cpu()!="STM32L041G6")&&(cpu()!="STM32L041K6")) tree.open "Basic timers" tree "TIMER 6" base ad:0x40001000 width 12. group.word 0x00++0x01 line.word 0x00 "TIM6_CR1,TIM6 control register 1" bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request" bitfld.word 0x00 1. " UDIS ,Update disable" "Enabled,Disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x01 line.word 0x00 "TIM6_CR2,TIM6 Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..." group.word 0x0C++0x01 line.word 0x00 "TIM6_DIER,TIM6 DMA/Interrupt enable register" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM6_SR,TIM6 Status register" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No effect,Update" wgroup.word 0x14++0x01 line.word 0x00 "TIM6_EGR,TIM6 Event generation register" bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated" group.word 0x24++0x01 line.word 0x00 "TIM6_CNT,Counter" group.word 0x28++0x01 line.word 0x00 "TIM6_PSC,Prescaler" group.word 0x2C++0x01 line.word 0x00 "TIM6_ARR,Auto-reload register" width 0x0B tree.end sif ((cpu()=="STM32L071C8")||(cpu()=="STM32L071CB")||(cpu()=="STM32L071CZ")||(cpu()=="STM32L071K8")||(cpu()=="STM32L071KB")||(cpu()=="STM32L071KZ")||(cpu()=="STM32L071RB")||(cpu()=="STM32L071RZ")||(cpu()=="STM32L071V8")||(cpu()=="STM32L071VB")||(cpu()=="STM32L071VZ")||(cpu()=="STM32L072CB")||(cpu()=="STM32L072KB")||(cpu()=="STM32L072KZ")||(cpu()=="STM32L072RB")||(cpu()=="STM32L072RZ")||(cpu()=="STM32L072V8")||(cpu()=="STM32L072VB")||(cpu()=="STM32L072VZ")||(cpu()=="STM32L073CB")||(cpu()=="STM32L073CZ")||(cpu()=="STM32L073RB")||(cpu()=="STM32L073RZ")||(cpu()=="STM32L073V8")||(cpu()=="STM32L073VB")||(cpu()=="STM32L073VZ")||(cpu()=="STM32L081CZ")||(cpu()=="STM32L081KZ")||(cpu()=="STM32L082KB")||(cpu()=="STM32L082KZ")||(cpu()=="STM32L083CB")||(cpu()=="STM32L083CZ")||(cpu()=="STM32L083RB")||(cpu()=="STM32L083RZ")) tree "TIMER 7" base ad:0x40001400 width 12. group.word 0x00++0x01 line.word 0x00 "TIM7_CR1,TIM7 control register 1" bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 3. " OPM ,One pulse mode" "Disabled,Enabled" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set,Overflow/Underflow/DMA request" bitfld.word 0x00 1. " UDIS ,Update disable" "Enabled,Disabled" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.word 0x04++0x01 line.word 0x00 "TIM7_CR2,TIM7 Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..." group.word 0x0C++0x01 line.word 0x00 "TIM7_DIER,TIM7 DMA/Interrupt enable register" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM7_SR,TIM7 Status register" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No effect,Update" wgroup.word 0x14++0x01 line.word 0x00 "TIM7_EGR,TIM7 Event generation register" bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated" group.word 0x24++0x01 line.word 0x00 "TIM7_CNT,Counter" group.word 0x28++0x01 line.word 0x00 "TIM7_PSC,Prescaler" group.word 0x2C++0x01 line.word 0x00 "TIM7_ARR,Auto-reload register" width 0x0B tree.end endif tree.end endif tree "LPTIM1 (Low power timer 1)" base ad:0x40007C00 width 6. group.long 0x00++0x0B line.long 0x00 "ISR,LPTIM Interrupt and Status Register" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " DOWN_set/clr ,Counter direction change up to down" "Not changed,Changed" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " UP_set/clr ,Counter direction change down to up" "Changed,Not changed" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ARROK_set/clr ,Autoreload register update OK" "False,True" setclrfld.long 0x00 3. 0x08 3. 0x04 3. " CMPOK ,Compare register update OK" "False,True" textline " " setclrfld.long 0x00 2. 0x08 2. 0x04 2. " EXTTRIG_set/clr ,External trigger edge event" "Not occurred,Occurred" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " ARRM_set/clr ,Autoreload match" "Not matched,Matched" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CMPM_set/clr ,Compare match" "Not matched,Matched" if ((per.l(ad:0x40007C00+0x0C)&0x1000000)==0x00) group.long 0x0C++0x03 line.long 0x00 "CFGR,LPTIM Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Internal,LPTIM" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After each APB bus write access,End of the current LPTIM period" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inversed,Inversed" textline " " bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM/One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "SW,Rising,Falling,Both" bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "EXT_TRIG0,EXT_TRIG1,EXT_TRIG2,EXT_TRIG3,EXT_TRIG4,,EXT_TRIG6,EXT_TRIG7" textline " " bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "No filter,2 clocks,4 clocks,8 clocks" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "No filter,2 clocks,4 clocks,8 clocks" bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Rising edge,Falling edge,Both edges," textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" else group.long 0x0C++0x03 line.long 0x00 "CFGR,LPTIM Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Internal,LPTIM" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After each APB bus write access,End of the current LPTIM period" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" textline " " bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM/One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "SW,Rising,Falling,Both" bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "EXT_TRIG0,EXT_TRIG1,EXT_TRIG2,EXT_TRIG3,EXT_TRIG4,,EXT_TRIG6,EXT_TRIG7" textline " " bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "No filter,2 clocks,4 clocks,8 clocks" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "No filter,2 clocks,4 clocks,8 clocks" bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3," textline " " bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" endif group.long 0x10++0x0B line.long 0x00 "CR,LPTIM Control Register" bitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "Not started,Started" bitfld.long 0x00 1. " SNGSTRT ,LPTIM start in single mode" "Not started,Started" bitfld.long 0x00 0. " ENABLE ,LPTIM Enable" "Disabled,Enabled" line.long 0x04 "CMP,LPTIM Compare Register" hexmask.long.word 0x04 0.--15. 1. " CMP ,Compare value" line.long 0x08 "ARR,LPTIM Autoreload Register" hexmask.long.word 0x08 0.--15. 1. " ARR ,Auto reload value" hgroup.long 0x1C++0x03 hide.long 0x00 "CNT,LPTIM Counter Register" in width 0x0B tree.end tree "IWDG (Independent watchdog)" base ad:0x40003000 width 11. wgroup.long 0x00++0x3 line.long 0x00 "IWDG_KR,Key register" hexmask.long.word 0x00 0.--15. 0x01 " KEY ,Key value" group.long 0x04++0x7 line.long 0x00 "IWDG_PR,Prescaler register" bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256" line.long 0x04 "IWDG_RLR,Reload register" hexmask.long.word 0x04 0.--11. 0x01 " RL ,Watchdog counter reload value" rgroup.long 0x0C++0x3 line.long 0x00 "IWDG_SR,Status register" bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running" bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running" bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running" group.long 0x10++0x3 line.long 0x00 "IWDG_WINR,Window register" hexmask.long.word 0x00 0.--11. 1. " WIN[11:0] ,Watchdog counter window value" width 0xB tree.end tree "WWDG (System window watchdog)" base ad:0x40002C00 width 10. group.long 0x00++0x0B line.long 0x00 "WWDG_CR,Control Register" bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter" line.long 0x04 "WWDG_CFR,Configuration Register" bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt" bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div by 1,Div by 2,Div by 4,Div by 8" textline " " hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value" line.long 0x08 "WWDG_SR,Status Register" bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt" width 0x0B tree.end tree "RTC (Real time clock)" base ad:0x40002800 width 14. if (((per.l(ad:0x40002800+0x8)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)!=0x200000)) group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)==0x200000)) group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x40)&&((per.l(ad:0x40002800)&0x300000)==0x100000)) group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " AM ,AM/PM notation" "AM,PM" else group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC time register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " AM ,AM/PM notation" "AM,PM" endif if (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x0)) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04)&0x30)!=0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000)) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC date register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" textline " " bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif group.long 0x08++0xF line.long 0x00 "RTC_CR,RTC control register" bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarm B,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" textline " " bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" bitfld.long 0x00 6. " FMT ,Hour format" "24 hour/day,AM/PM" textline " " bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Not bypassed,Bypassed" bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge" bitfld.long 0x00 0.--2. " WUCKSEL[2:0] , Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,CK_SPRE,CK_SPRE,CK_SPRE+2^16,CK_SPRE+2^16" line.long 0x04 "RTC_ISR,RTC initialization and status register" rbitfld.long 0x04 16. " RECALPF ,Recalibration pending Flag" "Not detected,Detected" bitfld.long 0x04 14. " TAMP2F ,RTC_TAMP2 detection flag" "Not detected,Detected" bitfld.long 0x04 13. " TAMP1F ,RTC_TAMP1 detection flag" "Not detected,Detected" bitfld.long 0x04 12. " TSOVF ,Time-stamp overflow flag" "Not overflowed,Overflowed" textline " " bitfld.long 0x04 11. " TSF ,Time-stamp flag" "Not occurred,Occurred" bitfld.long 0x04 10. " WUTF ,Wakeup timer flag (counter reached 0)" "Not reached,Reached" bitfld.long 0x04 9. " ALRBF ,Alarm B flag enable" "Disabled,Enabled" bitfld.long 0x04 8. " ALRAF ,Alarm A flag enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " INIT ,Initialization mode" "Free running,Enabled" rbitfld.long 0x04 6. " INITF ,Initialization flag" "Not allowed,Allowed" bitfld.long 0x04 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized" rbitfld.long 0x04 4. " INITS ,Initialization status flag" "Not initialized,Initialized" textline " " rbitfld.long 0x04 3. " SHPF ,Shift operation pending" "Not pending,Pending" rbitfld.long 0x04 2. " WUTWF ,Wakeup timer configuration update" "Not allowed,Allowed" rbitfld.long 0x04 1. " ALRBWF ,Alarm B write flag" "Not allowed,Allowed" rbitfld.long 0x04 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed" line.long 0x08 "RTC_PRER,RTC prescaler register" hexmask.long.byte 0x08 16.--22. 0x01 " PREDIV_A ,Asynchronous prescaler factor" hexmask.long.word 0x08 0.--14. 0x01 " PREDIV_S ,Synchronous prescaler factor" line.long 0x0C "RTC_WUTR,RTC wakeup timer register" hexmask.long.word 0x0C 0.--15. 0x01 " WUT[15:0] ,Wakeup auto-reload value bits" width 14. if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00)) rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif ((per.l(ad:0x40002800+0x0C)&0x81)!=0x00) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMAR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)) group.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00)) rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif ((per.l(ad:0x40002800+0x0C)&0x82)!=0x00) group.long 0x1C++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x3 line.long 0x00 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" textline " " bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif wgroup.long 0x24++0x3 line.long 0x00 "RTC_WPR,RTC write protection register" hexmask.long.byte 0x00 0.--7. 0x01 " KEY ,Write protection key" rgroup.long 0x28++0x3 line.long 0x00 "RTC_SSR,RTC sub second register" hexmask.long.byte 0x00 0.--15. 0x01 " SS ,Sub second value" wgroup.long 0x2C++0x3 line.long 0x00 "RTC_SHIFTR,RTC shift control register" bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Added to the clock/calendar" hexmask.long.word 0x00 0.--14. 0x01 " SUBFS ,Subtract a fraction of a second" if ((per.l((ad:0x40002800)+0x0C)&0x800)==0x0) hgroup.long 0x30++0x7 hide.long 0x00 "RTC_TSTR,RTC time stamp time register" hide.long 0x04 "RTC_TSDR,RTC time stamp date register" elif (((per.l((ad:0x40002800)+0xC)&0x800)==0x800)&&((per.l(ad:0x40002800+0x8)&0x40)==0x0)) rgroup.long 0x30++0x7 line.long 0x00 "RTC_TSTR,RTC time stamp time register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " 24h ,AM/PM notation" "24h,PM" line.long 0x04 "RTC_TSDR,RTC time stamp date register" bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else rgroup.long 0x30++0x7 line.long 0x00 "RTC_TSTR,RTC time stamp time register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. "AM ,AM/PM notation" "AM,PM" line.long 0x04 "RTC_TSDR,RTC time stamp date register" bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif if ((per.l((ad:0x40002800)+0xC)&0x800)==0x800) rgroup.long 0x38++0x3 line.long 0x00 "RTC_TSSSR,RTC timestamp sub second register" hexmask.long 0x00 0.--15. 0x01 " SS ,Sub second value" else hgroup.long 0x38++0x3 hide.long 0x00 "RTC_TSSSR,RTC timestamp sub second register" endif group.long 0x3C++0x3 line.long 0x00 "RTC_CALR,RTC calibration register" bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No RTCCLK,One RTCCLK" bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "Not selected,Selected" bitfld.long 0x00 13. " CALW16 ,Use a 16-second calibration cycle period" "Not selected,Selected" hexmask.long.word 0x00 0.--8. 0x01 " CALM ,Calibration minus" if ((per.l((ad:0x40002800)+0x40)&0x1800)!=0x00) group.long 0x40++0x3 line.long 0x00 "RTC_TAMPCR,RTC RTC tamper configuration register" bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked" bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "Erased,Not erased" bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked" textline " " bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "Not erased,Erased" bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "Enabled,Disabled" bitfld.long 0x00 13.--14. " TAMPPRCH ,RTC_TAMPx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles" textline " " bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "On edge,After 2 samples,After 4 samples,After 8 samples" bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256" bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved" bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP1 input" "Low,High" textline " " bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 input detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High" bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled" else group.long 0x40++0x3 line.long 0x00 "RTC_TAMPCR,RTC RTC tamper configuration register" bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked" bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "Erased,Not erased" bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked" textline " " bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "Not erased,Erased" bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "Enabled,Disabled" bitfld.long 0x00 13.--14. " TAMPPRCH ,RTC_TAMPx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles" textline " " bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "On edge,After 2 samples,After 4 samples,After 8 samples" bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256" bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved" bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP1 input" "Rising edge,Falling edge" textline " " bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 input detection enable" "Disabled,Enabled" bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High" bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled" endif if ((per.l(ad:0x40002800+0x0C)&0x81)!=0x00) group.long 0x44++0x03 line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared" hexmask.long.word 0x00 0.--14. 0x01 " SS ,Sub seconds value" else rgroup.long 0x44++0x03 line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared" hexmask.long.word 0x00 0.--14. 0x01 " SS ,Sub seconds value" endif if ((per.l(ad:0x40002800+0x0C)&0x82)!=0x00) group.long 0x48++0x03 line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared" hexmask.long.word 0x00 0.--14. 0x01 " SS ,Sub seconds value" else rgroup.long 0x48++0x03 line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared" hexmask.long.word 0x00 0.--14. 0x01 " SS ,Sub seconds value" endif group.long 0x4C++0x03 line.long 0x00 "RTC_OR,RTC option register" bitfld.long 0x00 1. " RTC_OUT_RMP ,RTC_OUT remap" "0,1" bitfld.long 0x00 0. " RTC_ALARM_TYPE ,RTC_ALARM on PC13 output type" "Open-drain,Push-pull" group.long 0x50++0x13 line.long 0x0 "BKP0R,RTC backup register 0" line.long 0x4 "BKP1R,RTC backup register 1" line.long 0x8 "BKP2R,RTC backup register 2" line.long 0xC "BKP3R,RTC backup register 3" line.long 0x10 "BKP4R,RTC backup register 4" width 0xB tree.end tree.open "I2C (Inter-integrated circuit interface)" tree "I2C 1" base ad:0x40005400 width 16. if ((per.l(ad:0x40005400+0x00)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable (Device mode/Host mode)" "Disabled/Not supported,Enabled/Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable " "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled" bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" textline " " else group.long 0x00++0x03 line.long 0x00 "I2C1_CR1,Control register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable (Device mode/Host mode)" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable " "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled" bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "I2C1_CR2,Control register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC" textline " " bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 0x01 " NBYTES[7:0] ,Number of bytes" bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits" bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" bitfld.long 0x00 8.--9. " SADD[9:8] ,Slave address bit 9:8" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x01 " SADD[7:1] ,Slave address bit 7:1 " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0" "0,1" textline " " if ((per.l(ad:0x40005400+0x08)&0x8000)==0x00) group.long 0x08++0x03 line.long 0x00 "I2C1_OAR1,Own address 1 register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit" bitfld.long 0x00 9. " OA1 ,Interface address" "0,1" bitfld.long 0x00 8. ",Interface address" "0,1" bitfld.long 0x00 7. ",Interface address" "0,1" bitfld.long 0x00 6. ",Interface address" "0,1" bitfld.long 0x00 5. ",Interface address" "0,1" bitfld.long 0x00 4. ",Interface address" "0,1" bitfld.long 0x00 3. ",Interface address" "0,1" bitfld.long 0x00 2. ",Interface address" "0,1" bitfld.long 0x00 1. ",Interface address" "0,1" bitfld.long 0x00 0. ",Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C1_OAR1,Own address 1 register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit" rbitfld.long 0x00 9. " OA1 ,Interface address" "0,1" rbitfld.long 0x00 8. ",Interface address" "0,1" rbitfld.long 0x00 7. ",Interface address" "0,1" rbitfld.long 0x00 6. ",Interface address" "0,1" rbitfld.long 0x00 5. ",Interface address" "0,1" rbitfld.long 0x00 4. ",Interface address" "0,1" rbitfld.long 0x00 3. ",Interface address" "0,1" rbitfld.long 0x00 2. ",Interface address" "0,1" rbitfld.long 0x00 1. ",Interface address" "0,1" rbitfld.long 0x00 0. ",Interface address" "0,1" endif if ((per.l(ad:0x40005400+0x0C)&0x8000)==0x00) group.long 0x0C++0x03 line.long 0x00 "I2C1_OAR2,Own address 2 register" bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison" bitfld.long 0x00 7. " OA2 ,Interface address" "0,1" bitfld.long 0x00 6. ",Interface address" "0,1" bitfld.long 0x00 5. ",Interface address" "0,1" bitfld.long 0x00 4. ",Interface address" "0,1" bitfld.long 0x00 3. ",Interface address" "0,1" bitfld.long 0x00 2. ",Interface address" "0,1" bitfld.long 0x00 1. ",Interface address" "0,1" else group.long 0x0C++0x03 line.long 0x00 "I2C1_OAR2,Own address 2 register" bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison" rbitfld.long 0x00 7. " OA2 ,Interface address" "0,1" rbitfld.long 0x00 6. ",Interface address" "0,1" rbitfld.long 0x00 5. ",Interface address" "0,1" rbitfld.long 0x00 4. ",Interface address" "0,1" rbitfld.long 0x00 3. ",Interface address" "0,1" rbitfld.long 0x00 2. ",Interface address" "0,1" rbitfld.long 0x00 1. ",Interface address" "0,1" endif textline " " group.long 0x10++0x03 line.long 0x00 "I2C1_TIMINGR,Timing register" bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 0x1 " SCLH[7:0] ,SCL high period" hexmask.long.byte 0x00 0.--7. 0x1 " SCLL[7:0] ,SCL low period" group.long 0x14++0x03 line.long 0x00 "I2C1_TIMEOUTR,Timeout register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disalbed,Enabled" hexmask.long.word 0x00 16.--27. 0x1 " TIMEOUTB[11:0] ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout" hexmask.long.word 0x00 0.--11. 0x1 " TIMEOUTA[11:0] ,Bus Timeout A" group.long 0x18++0x03 line.long 0x00 "I2C1_ISR,Interrupt and Status register" hexmask.long.byte 0x00 17.--23. 0x01 " ADDCODE[6:0] ,Address match code" rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read" rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy" textline " " rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected" rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred" rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error" textline " " bitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred" bitfld.long 0x00 8. " BERR ,Bus error" "No error,Error" bitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed" textline " " bitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected" bitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received" bitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched" textline " " rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty" bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C1_ICR,Interrupt clear register" bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear" bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear" bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear" textline " " bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear" bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear" bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear" rgroup.long 0x20++0x03 line.long 0x00 "I2C1_PECR,PEC register" hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register" rgroup.long 0x24++0x03 line.long 0x00 "I2C1_RXDR,Receive data register" hexmask.long.byte 0x00 0.--7. 0x01 " RXDATA[7:0] ,Data byte received from the I2C bus" if ((per.l(ad:0x40005400+0x18)&0x01)==0x00) group.long 0x28++0x03 line.long 0x00 "I2C1_TXDR,Transmit data register" hexmask.long.byte 0x00 0.--7. 0x01 " TXDATA[7:0] ,Data byte to be transmitted to the I2C bus" else rgroup.long 0x28++0x03 line.long 0x00 "I2C1_TXDR,Transmit data register" hexmask.long.byte 0x00 0.--7. 0x01 " TXDATA[7:0] ,Data byte to be transmitted to the I2C bus" endif width 11. tree.end sif ((!cpuis("STM32L051K*"))&&(!cpuis("STM32L052K*"))&&(!cpuis("STM32L011*"))&&(!cpuis("STM32L021*"))&&(!cpuis("STM32L011*"))&&(!cpuis("STM32L031*"))&&(!cpuis("STM32L011*"))&&(!cpuis("STM32L041*"))) sif ((!cpuis("STM32L07?K*"))&&(!cpuis("STM32L08?K*"))) tree "I2C 2" base ad:0x40005800 width 16. if ((per.l(ad:0x40005800+0x00)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control register 1" bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable " "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled" bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" textline " " else group.long 0x00++0x03 line.long 0x00 "I2C2_CR1,Control register 1" bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable " "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled" bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "I2C2_CR2,Control register 2" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 0x01 " NBYTES[7:0] ,Number of bytes" bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits" bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" bitfld.long 0x00 8.--9. " SADD[9:8] ,Slave address bit 9:8" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x01 " SADD[7:1] ,Slave address bit 7:1 " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0" "0,1" textline " " if ((per.l(ad:0x40005800+0x08)&0x8000)==0x00) group.long 0x08++0x03 line.long 0x00 "I2C2_OAR1,Own address 1 register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit" bitfld.long 0x00 9. " OA1 ,Interface address" "0,1" bitfld.long 0x00 8. ",Interface address" "0,1" bitfld.long 0x00 7. ",Interface address" "0,1" bitfld.long 0x00 6. ",Interface address" "0,1" bitfld.long 0x00 5. ",Interface address" "0,1" bitfld.long 0x00 4. ",Interface address" "0,1" bitfld.long 0x00 3. ",Interface address" "0,1" bitfld.long 0x00 2. ",Interface address" "0,1" bitfld.long 0x00 1. ",Interface address" "0,1" bitfld.long 0x00 0. ",Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C2_OAR1,Own address 1 register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit" rbitfld.long 0x00 9. " OA1 ,Interface address" "0,1" rbitfld.long 0x00 8. ",Interface address" "0,1" rbitfld.long 0x00 7. ",Interface address" "0,1" rbitfld.long 0x00 6. ",Interface address" "0,1" rbitfld.long 0x00 5. ",Interface address" "0,1" rbitfld.long 0x00 4. ",Interface address" "0,1" rbitfld.long 0x00 3. ",Interface address" "0,1" rbitfld.long 0x00 2. ",Interface address" "0,1" rbitfld.long 0x00 1. ",Interface address" "0,1" rbitfld.long 0x00 0. ",Interface address" "0,1" endif if ((per.l(ad:0x40005800+0x0C)&0x8000)==0x00) group.long 0x0C++0x03 line.long 0x00 "I2C2_OAR2,Own address 2 register" bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison" bitfld.long 0x00 7. " OA2 ,Interface address" "0,1" bitfld.long 0x00 6. ",Interface address" "0,1" bitfld.long 0x00 5. ",Interface address" "0,1" bitfld.long 0x00 4. ",Interface address" "0,1" bitfld.long 0x00 3. ",Interface address" "0,1" bitfld.long 0x00 2. ",Interface address" "0,1" bitfld.long 0x00 1. ",Interface address" "0,1" else group.long 0x0C++0x03 line.long 0x00 "I2C2_OAR2,Own address 2 register" bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison" rbitfld.long 0x00 7. " OA2 ,Interface address" "0,1" rbitfld.long 0x00 6. ",Interface address" "0,1" rbitfld.long 0x00 5. ",Interface address" "0,1" rbitfld.long 0x00 4. ",Interface address" "0,1" rbitfld.long 0x00 3. ",Interface address" "0,1" rbitfld.long 0x00 2. ",Interface address" "0,1" rbitfld.long 0x00 1. ",Interface address" "0,1" endif textline " " group.long 0x10++0x03 line.long 0x00 "I2C2_TIMINGR,Timing register" bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 0x1 " SCLH[7:0] ,SCL high period" hexmask.long.byte 0x00 0.--7. 0x1 " SCLL[7:0] ,SCL low period" group.long 0x18++0x03 line.long 0x00 "I2C2_ISR,Interrupt and Status register" hexmask.long.byte 0x00 17.--23. 0x01 " ADDCODE[6:0] ,Address match code" rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read" rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy" textline " " bitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred" bitfld.long 0x00 8. " BERR ,Bus error" "No error,Error" bitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed" textline " " bitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected" bitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received" bitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched" textline " " rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty" bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C2_ICR,Interrupt clear register" bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear" bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear" bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "I2C2_RXDR,Receive data register" hexmask.long.byte 0x00 0.--7. 0x01 " RXDATA[7:0] ,Data byte received from the I2C bus" if ((per.l(ad:0x40005800+0x18)&0x01)==0x00) group.long 0x28++0x03 line.long 0x00 "I2C2_TXDR,Transmit data register" hexmask.long.byte 0x00 0.--7. 0x01 " TXDATA[7:0] ,Data byte to be transmitted to the I2C bus" else rgroup.long 0x28++0x03 line.long 0x00 "I2C2_TXDR,Transmit data register" hexmask.long.byte 0x00 0.--7. 0x01 " TXDATA[7:0] ,Data byte to be transmitted to the I2C bus" endif width 11. tree.end endif tree "I2C 3" base ad:0x40007800 width 16. if ((per.l(ad:0x40007800+0x00)&0x100000)==0x00) group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control register 1" bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable " "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled" bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" textline " " else group.long 0x00++0x03 line.long 0x00 "I2C3_CR1,Control register 1" bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable " "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled" bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif group.long 0x04++0x03 line.long 0x00 "I2C3_CR2,Control register 2" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 0x01 " NBYTES[7:0] ,Number of bytes" bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop" bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits" bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" bitfld.long 0x00 8.--9. " SADD[9:8] ,Slave address bit 9:8" "0,1,2,3" hexmask.long.byte 0x00 1.--7. 0x01 " SADD[7:1] ,Slave address bit 7:1 " bitfld.long 0x00 0. " SADD0 ,Slave address bit 0" "0,1" textline " " if ((per.l(ad:0x40007800+0x08)&0x8000)==0x00) group.long 0x08++0x03 line.long 0x00 "I2C3_OAR1,Own address 1 register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit" bitfld.long 0x00 9. " OA1 ,Interface address" "0,1" bitfld.long 0x00 8. ",Interface address" "0,1" bitfld.long 0x00 7. ",Interface address" "0,1" bitfld.long 0x00 6. ",Interface address" "0,1" bitfld.long 0x00 5. ",Interface address" "0,1" bitfld.long 0x00 4. ",Interface address" "0,1" bitfld.long 0x00 3. ",Interface address" "0,1" bitfld.long 0x00 2. ",Interface address" "0,1" bitfld.long 0x00 1. ",Interface address" "0,1" bitfld.long 0x00 0. ",Interface address" "0,1" else group.long 0x08++0x03 line.long 0x00 "I2C3_OAR1,Own address 1 register" bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit" rbitfld.long 0x00 9. " OA1 ,Interface address" "0,1" rbitfld.long 0x00 8. ",Interface address" "0,1" rbitfld.long 0x00 7. ",Interface address" "0,1" rbitfld.long 0x00 6. ",Interface address" "0,1" rbitfld.long 0x00 5. ",Interface address" "0,1" rbitfld.long 0x00 4. ",Interface address" "0,1" rbitfld.long 0x00 3. ",Interface address" "0,1" rbitfld.long 0x00 2. ",Interface address" "0,1" rbitfld.long 0x00 1. ",Interface address" "0,1" rbitfld.long 0x00 0. ",Interface address" "0,1" endif if ((per.l(ad:0x40007800+0x0C)&0x8000)==0x00) group.long 0x0C++0x03 line.long 0x00 "I2C3_OAR2,Own address 2 register" bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison" bitfld.long 0x00 7. " OA2 ,Interface address" "0,1" bitfld.long 0x00 6. ",Interface address" "0,1" bitfld.long 0x00 5. ",Interface address" "0,1" bitfld.long 0x00 4. ",Interface address" "0,1" bitfld.long 0x00 3. ",Interface address" "0,1" bitfld.long 0x00 2. ",Interface address" "0,1" bitfld.long 0x00 1. ",Interface address" "0,1" else group.long 0x0C++0x03 line.long 0x00 "I2C3_OAR2,Own address 2 register" bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison" rbitfld.long 0x00 7. " OA2 ,Interface address" "0,1" rbitfld.long 0x00 6. ",Interface address" "0,1" rbitfld.long 0x00 5. ",Interface address" "0,1" rbitfld.long 0x00 4. ",Interface address" "0,1" rbitfld.long 0x00 3. ",Interface address" "0,1" rbitfld.long 0x00 2. ",Interface address" "0,1" rbitfld.long 0x00 1. ",Interface address" "0,1" endif textline " " group.long 0x10++0x03 line.long 0x00 "I2C3_TIMINGR,Timing register" bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 0x1 " SCLH[7:0] ,SCL high period" hexmask.long.byte 0x00 0.--7. 0x1 " SCLL[7:0] ,SCL low period" group.long 0x18++0x03 line.long 0x00 "I2C3_ISR,Interrupt and Status register" hexmask.long.byte 0x00 17.--23. 0x01 " ADDCODE[6:0] ,Address match code" rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read" rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy" textline " " bitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred" bitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred" bitfld.long 0x00 8. " BERR ,Bus error" "No error,Error" bitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed" textline " " bitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected" bitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received" bitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched" textline " " rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty" bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty" wgroup.long 0x1C++0x03 line.long 0x00 "I2C3_ICR,Interrupt clear register" bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear" bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear" bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "I2C3_RXDR,Receive data register" hexmask.long.byte 0x00 0.--7. 0x01 " RXDATA[7:0] ,Data byte received from the I2C bus" if ((per.l(ad:0x40007800+0x18)&0x01)==0x00) group.long 0x28++0x03 line.long 0x00 "I2C3_TXDR,Transmit data register" hexmask.long.byte 0x00 0.--7. 0x01 " TXDATA[7:0] ,Data byte to be transmitted to the I2C bus" else rgroup.long 0x28++0x03 line.long 0x00 "I2C3_TXDR,Transmit data register" hexmask.long.byte 0x00 0.--7. 0x01 " TXDATA[7:0] ,Data byte to be transmitted to the I2C bus" endif width 11. tree.end endif tree.end sif ((cpuis("STM32L011*"))||(cpuis("STM32L021*"))||(cpuis("STM32L031*"))||(cpuis("STM32L041*"))) tree "USART (Universal synchronous asynchronous receiver transmitter)" base ad:0x40013800 width 11. if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" rbitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40013800+0x00)&0x05)==0x01) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" else group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" rbitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" rbitfld.long 0x00 30. ",Address of the USART node 6" "0,1" rbitfld.long 0x00 29. ",Address of the USART node 5" "0,1" rbitfld.long 0x00 28. ",Address of the USART node 4" "0,1" rbitfld.long 0x00 27. ",Address of the USART node 3" "0,1" rbitfld.long 0x00 26. ",Address of the USART node 2" "0,1" rbitfld.long 0x00 25. ",Address of the USART node 1" "0,1" rbitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" endif if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" bitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "On address match,,On Start bit detection,On RXNE" bitfld.long 0x00 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" textline " " bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " bitfld.long 0x00 2. " IRLP ,IrDA Power mode" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" rbitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "On address match,,On Start bit detection,On RXNE" bitfld.long 0x00 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" textline " " rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " rbitfld.long 0x00 2. " IRLP ,IrDA Power mode" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" endif if (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8000) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8001) rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x00) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value" hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value" hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART_RTOR,Receiver timeout register" hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length" hexmask.long.tbyte 0x00 0.--23. 0x01 " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART_RQR,Request register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Request" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Request" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Request" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Request" textline " " bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request" rgroup.long 0x1C++0x03 line.long 0x00 "USART_ISR,Interrupt & status register" bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged" bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected" bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected" bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,Reached" bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout" bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset" textline " " bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected" bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "USART_ICR,Interrupt flag clear register" bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear" bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" textline " " bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" textline " " bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "RDR,Receive data register" hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue" group.long 0x28++0x03 line.long 0x00 "USART_TDR,Transmit data register" hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value" width 11. tree.end else tree.open "USART (Universal synchronous asynchronous receiver transmitter)" tree "USART 1" base ad:0x40013800 width 11. if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" rbitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40013800+0x00)&0x05)==0x01) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" else group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" rbitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" rbitfld.long 0x00 30. ",Address of the USART node 6" "0,1" rbitfld.long 0x00 29. ",Address of the USART node 5" "0,1" rbitfld.long 0x00 28. ",Address of the USART node 4" "0,1" rbitfld.long 0x00 27. ",Address of the USART node 3" "0,1" rbitfld.long 0x00 26. ",Address of the USART node 2" "0,1" rbitfld.long 0x00 25. ",Address of the USART node 1" "0,1" rbitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" endif if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" bitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "On address match,,On Start bit detection,On RXNE" bitfld.long 0x00 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" textline " " bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " bitfld.long 0x00 2. " IRLP ,IrDA Power mode" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" rbitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "On address match,,On Start bit detection,On RXNE" bitfld.long 0x00 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" textline " " rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " rbitfld.long 0x00 2. " IRLP ,IrDA Power mode" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" endif if (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8000) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8001) rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x00) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.l(ad:0x40013800+0x00)&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value" hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value" hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART_RTOR,Receiver timeout register" hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length" hexmask.long.tbyte 0x00 0.--23. 0x01 " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART_RQR,Request register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Request" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Request" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Request" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Request" textline " " bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request" rgroup.long 0x1C++0x03 line.long 0x00 "USART_ISR,Interrupt & status register" bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged" bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected" bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected" bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,Reached" bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout" bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset" textline " " bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected" bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "USART_ICR,Interrupt flag clear register" bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear" bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" textline " " bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" textline " " bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "RDR,Receive data register" hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue" group.long 0x28++0x03 line.long 0x00 "USART_TDR,Transmit data register" hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value" width 11. tree.end tree "USART 2" base ad:0x40004400 width 11. if ((per.l(ad:0x40004400+0x00)&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" rbitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if ((per.l(ad:0x40004400+0x00)&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40004400+0x00)&0x05)==0x01) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" else group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" rbitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" rbitfld.long 0x00 30. ",Address of the USART node 6" "0,1" rbitfld.long 0x00 29. ",Address of the USART node 5" "0,1" rbitfld.long 0x00 28. ",Address of the USART node 4" "0,1" rbitfld.long 0x00 27. ",Address of the USART node 3" "0,1" rbitfld.long 0x00 26. ",Address of the USART node 2" "0,1" rbitfld.long 0x00 25. ",Address of the USART node 1" "0,1" rbitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled" rbitfld.long 0x00 21.--22. " ABRMOD ,Baud rate detection method" "Start bit measurement,Beetwen falling edges,0x7F frame detection,0x55 frame detection" bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled" rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" textline " " rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" textline " " rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit" textline " " rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" endif if ((per.l(ad:0x40004400+0x00)&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" bitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "On address match,,On Start bit detection,On RXNE" bitfld.long 0x00 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" textline " " bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " bitfld.long 0x00 2. " IRLP ,IrDA Power mode" "Normal,Low-power" bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" rbitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "On address match,,On Start bit detection,On RXNE" bitfld.long 0x00 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" textline " " rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" textline " " rbitfld.long 0x00 2. " IRLP ,IrDA Power mode" "Normal,Low-power" rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" endif if (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8000) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8001) rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x00) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.l(ad:0x40004400+0x00)&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value" hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value" else rgroup.long 0x10++0x03 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value" hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value" endif group.long 0x14++0x03 line.long 0x00 "USART_RTOR,Receiver timeout register" hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length" hexmask.long.tbyte 0x00 0.--23. 0x01 " RTO ,Receiver timeout value" wgroup.long 0x18++0x03 line.long 0x00 "USART_RQR,Request register" bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "No effect,Request" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Request" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Request" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Request" textline " " bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "No effect,Request" rgroup.long 0x1C++0x03 line.long 0x00 "USART_ISR,Interrupt & status register" bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged" bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected" bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected" bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy" bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set" textline " " bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error" bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,Reached" bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout" bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset" textline " " bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected" bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "USART_ICR,Interrupt flag clear register" bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear" bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear" textline " " bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear" bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" textline " " bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "RDR,Receive data register" hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue" group.long 0x28++0x03 line.long 0x00 "USART_TDR,Transmit data register" hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value" width 11. tree.end sif (cpuis("STM32L07*"))||(cpuis("STM32L08*")) tree "USART 4" base ad:0x40004C00 width 11. if ((per.l(ad:0x40004C00)&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" rbitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if ((per.l(ad:0x40004C00)&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40004C00)&0x05)==0x01) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" else group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" rbitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" rbitfld.long 0x00 30. ",Address of the USART node 6" "0,1" rbitfld.long 0x00 29. ",Address of the USART node 5" "0,1" rbitfld.long 0x00 28. ",Address of the USART node 4" "0,1" rbitfld.long 0x00 27. ",Address of the USART node 3" "0,1" rbitfld.long 0x00 26. ",Address of the USART node 2" "0,1" rbitfld.long 0x00 25. ",Address of the USART node 1" "0,1" rbitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" endif if ((per.l(ad:0x40004C00)&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" endif if (((per.l((ad:0x40004C00+0x0)))&0x8001)==0x8000) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40004C00+0x0)))&0x8001)==0x8001) rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40004C00+0x0)))&0x8001)==0x00) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif wgroup.long 0x18++0x03 line.long 0x00 "USART_RQR,Request register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Request" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Request" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Request" rgroup.long 0x1C++0x03 line.long 0x00 "USART_ISR,Interrupt & status register" bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged" bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected" bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy" textline " " bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset" bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "USART_ICR,Interrupt flag clear register" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" textline " " bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "RDR,Receive data register" hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue" group.long 0x28++0x03 line.long 0x00 "USART_TDR,Transmit data register" hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value" width 11. tree.end sif ((!cpuis("STM32l071K*"))&&(!cpuis("STM32l072K*"))&&(!cpuis("STM32l081K*"))&&(!cpuis("STM32l082K*"))) tree "USART 5" base ad:0x40005000 width 11. if ((per.l(ad:0x40005000)&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" rbitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled" endif if ((per.l(ad:0x40005000)&0x01)==0x00) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40005000)&0x05)==0x01) group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" bitfld.long 0x00 30. ",Address of the USART node 6" "0,1" bitfld.long 0x00 29. ",Address of the USART node 5" "0,1" bitfld.long 0x00 28. ",Address of the USART node 4" "0,1" bitfld.long 0x00 27. ",Address of the USART node 3" "0,1" bitfld.long 0x00 26. ",Address of the USART node 2" "0,1" bitfld.long 0x00 25. ",Address of the USART node 1" "0,1" bitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" else group.long 0x04++0x03 line.long 0x00 "USART_CR2,Control register 2" rbitfld.long 0x00 31. " ADD[7:0] ,Address of the USART node 7" "0,1" rbitfld.long 0x00 30. ",Address of the USART node 6" "0,1" rbitfld.long 0x00 29. ",Address of the USART node 5" "0,1" rbitfld.long 0x00 28. ",Address of the USART node 4" "0,1" rbitfld.long 0x00 27. ",Address of the USART node 3" "0,1" rbitfld.long 0x00 26. ",Address of the USART node 2" "0,1" rbitfld.long 0x00 25. ",Address of the USART node 1" "0,1" rbitfld.long 0x00 24. ",Address of the USART node 0" "0,1" textline " " rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled" rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High" textline " " rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second" rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" endif if ((per.l(ad:0x40005000)&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" textline " " bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "USART_CR3,Control register 3" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low" rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" textline " " rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample" textline " " bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" endif if (((per.l((ad:0x40005000+0x0)))&0x8001)==0x8000) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40005000+0x0)))&0x8001)==0x8001) rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7" elif (((per.l((ad:0x40005000+0x0)))&0x8001)==0x00) group.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]" bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif wgroup.long 0x18++0x03 line.long 0x00 "USART_RQR,Request register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "No effect,Request" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "No effect,Request" bitfld.long 0x00 1. " SBKRQ ,Send break request" "No effect,Request" rgroup.long 0x1C++0x03 line.long 0x00 "USART_ISR,Interrupt & status register" bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged" bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected" bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy" textline " " bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes" bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "USART_ICR,Interrupt flag clear register" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" textline " " bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" textline " " bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "RDR,Receive data register" hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue" group.long 0x28++0x03 line.long 0x00 "USART_TDR,Transmit data register" hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value" width 11. tree.end endif endif tree.end endif sif (!cpuis("STM32L051K*"))&&(!cpuis("STM32L052K*")) tree "LPUART (Low-power universal asynchronous receiver transmitter)" base ad:0x40004800 width 5. if ((per.l(ad:0x40004800+0x00)&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" textline " " bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,LPUART enable in Stop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,LPUART enable" "Disabled,Enabled" elif ((per.l(ad:0x40004800+0x00)&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CR1,Control register 1" rbitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop," rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled" rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark" rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled" rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd" textline " " bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 1. " UESM ,LPUART enable in Stop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UE ,LPUART enable" "Disabled,Enabled" endif if ((per.l(ad:0x40004800+0x00)&0x05)==0x00) group.long 0x04++0x03 line.long 0x00 "CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the LPUART node 7" "0,1" bitfld.long 0x00 30. ",Address of the LPUART node 6" "0,1" bitfld.long 0x00 29. ",Address of the LPUART node 5" "0,1" bitfld.long 0x00 28. ",Address of the LPUART node 4" "0,1" bitfld.long 0x00 27. ",Address of the LPUART node 3" "0,1" bitfld.long 0x00 26. ",Address of the LPUART node 2" "0,1" bitfld.long 0x00 25. ",Address of the LPUART node 1" "0,1" bitfld.long 0x00 24. ",Address of the LPUART node 0" "0,1" textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40004800+0x00)&0x05)==0x05) rgroup.long 0x04++0x03 line.long 0x00 "CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the LPUART node 7" "0,1" bitfld.long 0x00 30. ",Address of the LPUART node 6" "0,1" bitfld.long 0x00 29. ",Address of the LPUART node 5" "0,1" bitfld.long 0x00 28. ",Address of the LPUART node 4" "0,1" bitfld.long 0x00 27. ",Address of the LPUART node 3" "0,1" bitfld.long 0x00 26. ",Address of the LPUART node 2" "0,1" bitfld.long 0x00 25. ",Address of the LPUART node 1" "0,1" bitfld.long 0x00 24. ",Address of the LPUART node 0" "0,1" textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" elif ((per.l(ad:0x40004800+0x00)&0x05)==0x04) group.long 0x04++0x03 line.long 0x00 "CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the LPUART node 7" "0,1" bitfld.long 0x00 30. ",Address of the LPUART node 6" "0,1" bitfld.long 0x00 29. ",Address of the LPUART node 5" "0,1" bitfld.long 0x00 28. ",Address of the LPUART node 4" "0,1" bitfld.long 0x00 27. ",Address of the LPUART node 3" "0,1" bitfld.long 0x00 26. ",Address of the LPUART node 2" "0,1" bitfld.long 0x00 25. ",Address of the LPUART node 1" "0,1" bitfld.long 0x00 24. ",Address of the LPUART node 0" "0,1" textline " " bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" else group.long 0x04++0x03 line.long 0x00 "CR2,Control register 2" bitfld.long 0x00 31. " ADD[7:0] ,Address of the LPUART node 7" "0,1" bitfld.long 0x00 30. ",Address of the LPUART node 6" "0,1" bitfld.long 0x00 29. ",Address of the LPUART node 5" "0,1" bitfld.long 0x00 28. ",Address of the LPUART node 4" "0,1" bitfld.long 0x00 27. ",Address of the LPUART node 3" "0,1" bitfld.long 0x00 26. ",Address of the LPUART node 2" "0,1" bitfld.long 0x00 25. ",Address of the LPUART node 1" "0,1" bitfld.long 0x00 24. ",Address of the LPUART node 0" "0,1" textline " " rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled" rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic" rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted" rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted" textline " " rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped" rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit" rbitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit" endif if ((per.l(ad:0x40004800+0x00)&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CR3,Control register 3" bitfld.long 0x00 23. " UCESM ,LPUART Clock Enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" bitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "Address match,,On Start bit,On RXNE" bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Positive,Negative" textline " " bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "CR3,Control register 3" bitfld.long 0x00 23. " UCESM ,LPUART Clock Enable in Stop mode" "Disabled,Enabled" bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated" rbitfld.long 0x00 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "Address match,,On Start bit,On RXNE" rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "Positive,Negative" textline " " rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled" rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes" rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes" bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled" rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled" bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected" bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled" endif if ((per.l(ad:0x40004800+0x00)&0x01)==0x00) group.long 0x0C++0x03 line.long 0x00 "BRR,Baud rate register" hexmask.long.tbyte 0x00 0.--19. 0x01 " BRR ,Baudrate" else rgroup.long 0x0C++0x03 line.long 0x00 "BRR,Baud rate register" hexmask.long.tbyte 0x00 0.--19. 0x01 " BRR ,Baudrate" endif wgroup.long 0x18++0x03 line.long 0x00 "RQR,Request register" bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested" bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested" bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested" rgroup.long 0x1C++0x03 line.long 0x00 "ISR,Interrupt & status register" bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged" bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged" bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected" bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break" bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected" bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy" bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset" textline " " bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred" bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed" bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes" textline " " bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected" bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error" bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" bitfld.long 0x00 1. " FE ,Framing error" "No error,Error" textline " " bitfld.long 0x00 0. " PE ,Parity error" "No error,Error" wgroup.long 0x20++0x03 line.long 0x00 "ICR,Interrupt flag clear register" bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear" bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear" bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear" bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear" textline " " bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear" bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear" bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear" bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear" textline " " bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear" rgroup.long 0x24++0x03 line.long 0x00 "RDR,Receive data register" hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue" group.long 0x28++0x03 line.long 0x00 "TDR,Transmit data register" hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value" width 11. tree.end endif sif ((cpuis("STM32L011*"))||(cpuis("STM32L021*"))||(cpuis("STM32L041*"))||(cpuis("STM32L071K*"))||(cpuis("STM32L072K*"))||(cpuis("STM32L081K*"))||(cpuis("STM32L082K*"))) tree "SPI (Serial peripheral interface)" base ad:0x40013000 width 12. if ((((per.w((ad:0x40013000+0x04)))&0x10)==0x10)) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" elif (((per.w(ad:0x40013000+0x04))&0x10)==0x00) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hexmask.word 0x00 0.--15. 0x01 " DR[15:0] ,Data register" width 12. tree.end else tree.open "SPI/I2S (Serial peripheral interface/Inter-IC sound)" sif ((!cpuis("STM32L051K*"))&&(!cpuis("STM32L052T*"))&&(!cpuis("STM32L052R6"))&&(!cpuis("STM32L031*"))) tree "SPI 1" base ad:0x40013000 width 12. if ((((per.w((ad:0x40013000+0x04)))&0x10)==0x10)) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" elif (((per.w(ad:0x40013000+0x04))&0x10)==0x00) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hexmask.word 0x00 0.--15. 0x01 " DR[15:0] ,Data register" width 12. tree.end elif (cpuis("STM32L031*")) tree "SPI 1" base ad:0x40013000 width 12. if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10) group.word 0x00++0x1 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data frame format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only mode" "Disabled,Enabled" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" textline " " bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x00) group.word 0x00++0x1 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Data phase,CRC phase" textline " " bitfld.word 0x00 11. " DFF ,Data frame format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only mode" "Disabled,Enabled" bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data" elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800) hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" endif if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w((ad:0x40013000+0x04)))&0x10)==0x10)) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x00) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" rgroup.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" textline " " bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hexmask.word 0x00 0.--15. 0x01 " DR[15:0] ,Data register" group.word 0x10++0x1 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hexmask.word 0x00 0.--15. 0x01 " CRCPOLY[15:0] ,CRC polynomial register" if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000) rgroup.word 0x14++0x1 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word 0x00 0.--15. 1. " RXCRC[15:0] ,Rx CRC register" rgroup.word 0x18++0x1 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word 0x00 0.--15. 1. " TxCRC[15:0] ,Tx CRC register" else hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if (((per.w(ad:0x40013000+0x1C))&0x800)==0x800) group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit," bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit" group.word 0x20++0x1 line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register" bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1" hexmask.word.byte 0x00 0.--7. 0x01 " I2SDIV ,I2S linear prescaler" else group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" hgroup.word 0x20++0x1 hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register" endif width 12. tree.end endif sif (!cpuis("STM32L052K*")) tree "SPI/I2S 2" base ad:0x40003800 width 12. if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10) group.word 0x00++0x1 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data frame format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only mode" "Disabled,Enabled" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" textline " " bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x00) group.word 0x00++0x1 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Data phase,CRC phase" textline " " bitfld.word 0x00 11. " DFF ,Data frame format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only mode" "Disabled,Enabled" bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data" elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800) hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" endif if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w((ad:0x40003800+0x04)))&0x10)==0x10)) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x00) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode" textline " " bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" group.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched" rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800) group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled" rgroup.word 0x08++0x1 line.word 0x00 "SPI_SR,SPI status register" textline " " bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty" bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred" bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty" endif group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hexmask.word 0x00 0.--15. 0x01 " DR[15:0] ,Data register" group.word 0x10++0x1 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hexmask.word 0x00 0.--15. 0x01 " CRCPOLY[15:0] ,CRC polynomial register" if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000) rgroup.word 0x14++0x1 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word 0x00 0.--15. 1. " RXCRC[15:0] ,Rx CRC register" rgroup.word 0x18++0x1 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word 0x00 0.--15. 1. " TxCRC[15:0] ,Tx CRC register" else hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if (((per.w(ad:0x40003800+0x1C))&0x800)==0x800) group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit," bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit" group.word 0x20++0x1 line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register" bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1" hexmask.word.byte 0x00 0.--7. 0x01 " I2SDIV ,I2S linear prescaler" else group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" hgroup.word 0x20++0x1 hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register" endif width 12. tree.end endif tree.end endif sif ((cpuis("STM32L0?2*"))||(cpuis("STM32L0?3*"))) tree "USB (Universal Serial Bus)" base ad:0x40005C00 width 12. group.long 0x40++0x7 line.long 0x00 "USB_CNTR,USB control register" bitfld.long 0x00 15. " CTRM ,Correct Transfer Interrupt Mask" "Disabled,Enabled" bitfld.long 0x00 14. " PMAOVRM ,Packet Memory Area Over/Underrun Interrupt Mask" "Disabled,Enabled" bitfld.long 0x00 13. " ERRM ,Error Interrupt Mask" "Disabled,Enabled" bitfld.long 0x00 12. " WKUPM ,Wake-up Interrupt Mask" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SUSPM ,Suspend mode Interrupt Mask" "Disabled,Enabled" bitfld.long 0x00 10. " RESETM ,USB Reset Interrupt Mask" "Disabled,Enabled" bitfld.long 0x00 9. " SOFM ,Start Of Frame Interrupt Mask" "Disabled,Enabled" bitfld.long 0x00 8. " ESOFM ,Expected Start Of Frame Interrupt Mask" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " L1REQM ,LPM L1 state request interrupt mask" "Disabled,Enabled" bitfld.long 0x00 5. " L1RESUME ,LPM L1 Resume request" "Disabled,Enabled" bitfld.long 0x00 4. " RESUME ,Resume request" "No effect,Requested" bitfld.long 0x00 3. " FSUSP ,Force suspend" "No effect,Forced" textline " " bitfld.long 0x00 2. " LP_MODE ,Low-power mode" "No Low-power,Entered" bitfld.long 0x00 1. " PDWN ,Power down" "Not powered down,Powered down" bitfld.long 0x00 0. " FRES ,Force USB Reset" "Cleared,Reset" line.long 0x04 "USB_ISTR,USB interrupt status register" rbitfld.long 0x04 15. " CTR ,Correct Transfer" "No effect,Correct" bitfld.long 0x04 14. " PMAOVR ,Packet Memory Area Over/Underrun" "No Over/Underrun,Over/Underrun" bitfld.long 0x04 13. " ERR ,Error" "No error,Error" bitfld.long 0x04 12. " WKUP ,Wakeup" "No wakeup,Wakeup" textline " " bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Not requested,Requested" bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset" bitfld.long 0x04 9. " SOF ,Start Of Frame" "No effect,Packet arrived" bitfld.long 0x04 8. " ESOF ,Expected Start Of Frame" "No effect,Packet expected" textline " " bitfld.long 0x04 7. " L1REQ ,LPM L1 state request" "Not requested,Requested" rbitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT/2 pending transactions" rbitfld.long 0x04 0.--3. " EP_ID ,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x48++0x03 line.long 0x00 "USB_FNR,USB frame number register" bitfld.long 0x00 15. " RXDP ,Receive Data + Line Status" "No data,Data" bitfld.long 0x00 14. " RXDM ,Receive Data - Line Status" "No data,Data" bitfld.long 0x00 13. " LCK ,Locked" "Unlocked,Locked" bitfld.long 0x00 11.--12. " LSOF ,Lost SOF" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--10. 0x1 " FN ,Frame Number" group.long 0x4C++0xB line.long 0x00 "USB_DADDR,USB device address" bitfld.long 0x00 7. " EF ,Enable Function" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 0x01 " ADD ,Device Address" line.long 0x04 "USB_BTABLE,Buffer table address" hexmask.long.word 0x04 3.--15. 0x8 " BTABLE ,Buffer Table" line.long 0x08 "USB_LPMCSR,LPM control and status register" rbitfld.long 0x08 4.--7. " BESL ,BESL value received with last ACKed LPM Token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 3. " REMWAKE ,bRemoteWake value" "0,1" bitfld.long 0x08 1. " LPMACK ,LPM Token acknowledge enable" "NYET,ACK" bitfld.long 0x08 0. " LPMEN ,LPM support enable" "Disabled,Enabled" group.word 0x58++0x01 line.word 0x00 "USB_BCDR,Battery Charging Detector" bitfld.word 0x00 15. " DPPU ,DP pull-up control" "Disabled,Enabled" rbitfld.word 0x00 7. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port/Proprietary charger" rbitfld.word 0x00 6. " SDET ,Secondary detection (SD) status" "CDP,DCP" rbitfld.word 0x00 5. " PDET ,Primary detection (PD) status" "No BCD support,BCD support" textline " " rbitfld.word 0x00 4. " DCDET ,Data contact detection" "Not detected,Detected" bitfld.word 0x00 3. " SDEN ,Secondary detection (SD) mode" "Disabled,Enabled" bitfld.word 0x00 2. " PDEN ,Primary detection (PD) mode" "Disabled,Enabled" bitfld.word 0x00 1. " DCDEN ,Data contact detection (DCD) mode" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " BCDEN ,Battery charging detector" "Disabled,Enabled" group.long 0x0++0x03 line.long 0x00 "USB_EP0R,USB endpoint 0 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4++0x03 line.long 0x00 "USB_EP1R,USB endpoint 1 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x03 line.long 0x00 "USB_EP2R,USB endpoint 2 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x03 line.long 0x00 "USB_EP3R,USB endpoint 3 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "USB_EP4R,USB endpoint 4 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x03 line.long 0x00 "USB_EP5R,USB endpoint 5 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x03 line.long 0x00 "USB_EP6R,USB endpoint 6 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "USB_EP7R,USB endpoint 7 register" bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer" bitfld.long 0x00 14. " DTOG_RX ,Data Toggle for reception transfers" "DATA0,DATA1" bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid" rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed" textline " " bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt" bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT" bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed" bitfld.long 0x00 6. " DTOG_TX ,Data Toggle for transmission transfers" "DATA0,DATA1" textline " " bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid" bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0xB tree "USB Buffer descriptor table" base ad:0x40006000 width 15. group.word 0x00++0x01 line.word 0x00 "USB_ADDR0_TX,Transmission buffer address 0" hexmask.word 0x00 1.--15. 0x2 " ADDR0_TX ,Transmission Buffer Address" group.word 0x02++0x01 line.word 0x00 "USB_COUNT0_TX,Transmission byte count 0" hexmask.word 0x00 0.--9. 0x1 " COUNT0_TX ,Transmission Byte Count" group.word 0x04++0x01 line.word 0x00 "USB_ADDR0_RX,Reception buffer address 0" hexmask.word 0x00 1.--15. 0x2 " ADDR0_RX ,Reception Buffer Address" group.word 0x06++0x01 line.word 0x00 "USB_COUNT0_RX,Reception byte count 0" bitfld.word 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x1 " COUNT0_RX ,Reception Byte Count" textline " " group.word 0x8++0x01 line.word 0x00 "USB_ADDR1_TX,Transmission buffer address 1" hexmask.word 0x00 1.--15. 0x2 " ADDR1_TX ,Transmission Buffer Address" group.word (0x8+0x02)++0x01 line.word 0x00 "USB_COUNT1_TX,Transmission byte count 1" hexmask.word 0x00 0.--9. 0x01 " COUNT1_TX_0 ,Transmission Byte Count 0" group.word (0x8+0x04)++0x01 line.word 0x00 "USB_ADDR1_RX,Reception buffer address 1" hexmask.word 0x00 1.--15. 0x2 " ADDR1_RX ,Reception Buffer Address" group.word (0x8+0x06)++0x01 line.word 0x00 "USB_COUNT1_RX,Reception byte count 1" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT1_RX[9:0] ,Reception Byte Count" textline " " group.word 0x10++0x01 line.word 0x00 "USB_ADDR2_TX,Transmission buffer address 2" hexmask.word 0x00 1.--15. 0x2 " ADDR2_TX ,Transmission Buffer Address" group.word (0x10+0x02)++0x01 line.word 0x00 "USB_COUNT2_TX,Transmission byte count 2" hexmask.word 0x00 0.--9. 0x01 " COUNT2_TX_0 ,Transmission Byte Count 0" group.word (0x10+0x04)++0x01 line.word 0x00 "USB_ADDR2_RX,Reception buffer address 2" hexmask.word 0x00 1.--15. 0x2 " ADDR2_RX ,Reception Buffer Address" group.word (0x10+0x06)++0x01 line.word 0x00 "USB_COUNT2_RX,Reception byte count 2" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT2_RX[9:0] ,Reception Byte Count" textline " " group.word 0x18++0x01 line.word 0x00 "USB_ADDR3_TX,Transmission buffer address 3" hexmask.word 0x00 1.--15. 0x2 " ADDR3_TX ,Transmission Buffer Address" group.word (0x18+0x02)++0x01 line.word 0x00 "USB_COUNT3_TX,Transmission byte count 3" hexmask.word 0x00 0.--9. 0x01 " COUNT3_TX_0 ,Transmission Byte Count 0" group.word (0x18+0x04)++0x01 line.word 0x00 "USB_ADDR3_RX,Reception buffer address 3" hexmask.word 0x00 1.--15. 0x2 " ADDR3_RX ,Reception Buffer Address" group.word (0x18+0x06)++0x01 line.word 0x00 "USB_COUNT3_RX,Reception byte count 3" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT3_RX[9:0] ,Reception Byte Count" textline " " group.word 0x20++0x01 line.word 0x00 "USB_ADDR4_TX,Transmission buffer address 4" hexmask.word 0x00 1.--15. 0x2 " ADDR4_TX ,Transmission Buffer Address" group.word (0x20+0x02)++0x01 line.word 0x00 "USB_COUNT4_TX,Transmission byte count 4" hexmask.word 0x00 0.--9. 0x01 " COUNT4_TX_0 ,Transmission Byte Count 0" group.word (0x20+0x04)++0x01 line.word 0x00 "USB_ADDR4_RX,Reception buffer address 4" hexmask.word 0x00 1.--15. 0x2 " ADDR4_RX ,Reception Buffer Address" group.word (0x20+0x06)++0x01 line.word 0x00 "USB_COUNT4_RX,Reception byte count 4" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT4_RX[9:0] ,Reception Byte Count" textline " " group.word 0x28++0x01 line.word 0x00 "USB_ADDR5_TX,Transmission buffer address 5" hexmask.word 0x00 1.--15. 0x2 " ADDR5_TX ,Transmission Buffer Address" group.word (0x28+0x02)++0x01 line.word 0x00 "USB_COUNT5_TX,Transmission byte count 5" hexmask.word 0x00 0.--9. 0x01 " COUNT5_TX_0 ,Transmission Byte Count 0" group.word (0x28+0x04)++0x01 line.word 0x00 "USB_ADDR5_RX,Reception buffer address 5" hexmask.word 0x00 1.--15. 0x2 " ADDR5_RX ,Reception Buffer Address" group.word (0x28+0x06)++0x01 line.word 0x00 "USB_COUNT5_RX,Reception byte count 5" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT5_RX[9:0] ,Reception Byte Count" textline " " group.word 0x30++0x01 line.word 0x00 "USB_ADDR6_TX,Transmission buffer address 6" hexmask.word 0x00 1.--15. 0x2 " ADDR6_TX ,Transmission Buffer Address" group.word (0x30+0x02)++0x01 line.word 0x00 "USB_COUNT6_TX,Transmission byte count 6" hexmask.word 0x00 0.--9. 0x01 " COUNT6_TX_0 ,Transmission Byte Count 0" group.word (0x30+0x04)++0x01 line.word 0x00 "USB_ADDR6_RX,Reception buffer address 6" hexmask.word 0x00 1.--15. 0x2 " ADDR6_RX ,Reception Buffer Address" group.word (0x30+0x06)++0x01 line.word 0x00 "USB_COUNT6_RX,Reception byte count 6" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT6_RX[9:0] ,Reception Byte Count" textline " " group.word 0x38++0x01 line.word 0x00 "USB_ADDR7_TX,Transmission buffer address 7" hexmask.word 0x00 1.--15. 0x2 " ADDR7_TX ,Transmission Buffer Address" group.word (0x38+0x02)++0x01 line.word 0x00 "USB_COUNT7_TX,Transmission byte count 7" hexmask.word 0x00 0.--9. 0x01 " COUNT7_TX_0 ,Transmission Byte Count 0" group.word (0x38+0x04)++0x01 line.word 0x00 "USB_ADDR7_RX,Reception buffer address 7" hexmask.word 0x00 1.--15. 0x2 " ADDR7_RX ,Reception Buffer Address" group.word (0x38+0x06)++0x01 line.word 0x00 "USB_COUNT7_RX,Reception byte count 7" bitfld.word 0x00 15. " BL_SIZE ,Block size 0" "2 byte,32 byte" bitfld.word 0x00 10.--14. " NUM_BLOCK[4:0] ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--9. 0x01 " COUNT7_RX[9:0] ,Reception Byte Count" textline " " width 0xb tree.end tree.end endif tree "DBG (Debug support)" base ad:0x40015800 width 15. rgroup.long 0x00++0x3 line.long 0x00 "DBGMCU_IDCODE,MCU device ID code" hexmask.long.word 0x00 16.--31. 0x1 " REV_ID ,Revision Identifier" hexmask.long.word 0x00 0.--11. 0x1 " DEV_ID ,Device Identifier" group.long 0x04++0xB line.long 0x00 "DBGMCU_CR,Debug MCU configuration Register" bitfld.long 0x00 2. " DBG_STANDBY ,Debug Standby mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On" bitfld.long 0x00 1. " DBG_STOP ,Debug Stop Mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On" bitfld.long 0x00 0. " DBG_SLEEP ,Debug Sleep Mode" "FCLK=On/HCLK=Off,FCLK=On/HCLK=On" line.long 0x04 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register" bitfld.long 0x04 31. " DBG_LPTIMER_STOP ,LPTIM1 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 22. " DBG_I2C2_STOP ,I2C2 SMBUS timeout mode stopped when core is halted" "Started,Stopped" bitfld.long 0x04 21. " DBG_I2C1_STOP ,I2C1 SMBUS timeout mode stopped when core is halted" "Started,Stopped" bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Wachdog stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped" line.long 0x08 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register" bitfld.long 0x08 6. " DBG_TIM22_STOP ,TIM22 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x08 2. " DBG_TIM21_STOP ,TIM21 counter stopped when core is halted" "Started,Stopped" width 0xB tree.end tree "Device electronic signature" base ad:0x1FF80050 width 11. rgroup.long 0x00++0x07 line.long 0x00 "UID[31:0],Unique device ID register" line.long 0x04 "UID[63:32],Unique device ID register" rgroup.long 0x14++0x03 line.long 0x00 "UID[95:64],Unique device ID register" rgroup.word 0x2C++0x1 line.word 0x00 "FLASH_SIZE,Flash size data register" width 0x0B tree.end textline " "