; -------------------------------------------------------------------------------- ; @Title: CoreSight STM On-Chip Peripherals ; @Props: Released ; @Author: KRU ; @Changelog: 2011-03-30 KRU ; @Manufacturer: ARM - ARM Ltd. ; @Doc: DDI0444B_stm_r0p1_trm.pdf; IHI0054A_stm_v1_0_architecture_spec.pdf ; @Core: Generic ; @Chiplist: 66AK2H06, 66AK2H06-DSP0, 66AK2H06-DSP1, 66AK2H06-DSP2, ; 66AK2H06-DSP3, 66AK2H12, 66AK2H12-DSP0, 66AK2H12-DSP1, 66AK2H12-DSP2, ; 66AK2H12-DSP3, 66AK2H12-DSP4, 66AK2H12-DSP5, 66AK2H12-DSP6, 66AK2H12-DSP7, ; 88AP128, 88AP162, 88AP166, 88AP168, 88AP510-V6, 88AP510-V7, 88AP610-V6, ; 88AP610-V7, 88AP610SEC-V6, 88AP610SEC-V7, 88AP955, 88AP955SEAGULL, 88AP978, ; 88AP978M3, 88AP978SEAGULL, 88CP888, 88CP888SEAGULL, 88CP968, 88CP968SEAGULL, ; 88E7251, 88F5082, 88F5082-MPU, 88F5180N, 88F5180N-MPU, 88F5181, 88F5181-MPU, ; 88F5181L, 88F5182, 88F5182-MPU, 88F5281, 88F5281-MPU, 88F6082, 88F6082-MPU, ; 88F6082L, 88F6180, 88F6183, 88F6183L, 88F6190, 88F6192, 88F6280, 88F6281, ; 88F6282, 88F6283, 88F6321-CPU0, 88F6321-CPU1, 88F6322-CPU0, 88F6322-CPU1, ; 88F6323-CPU0, 88F6323-CPU1, 88F6601, 88F6702, 88F6707, 88F6710, 88F6W11, ; 88FR101, 88FR102, 88FR111, 88FR131, 88FR301, 88FR321, 88FR331, 88FR331-X, ; 88FR521, 88FR531, 88FR571, 88M1801, 88M1801M3, 88M1801SEAGULL, 88SV581X-V6, ; 88SV581X-V7, 88SV584X-V6, 88SV584X-V7, A2F060, A2F200, A2F500, AD6522, ; AD6528, AD6532, AD6758, AD6900, ADSPCM402F, ADSPCM403F, ADSPCM407F, ; ADSPCM408F, ADUC7019, ADUC7020, ADUC7021, ADUC7022, ADUC7023, ADUC7024, ; ADUC7025, ADUC7026, ADUC7027, ADUC7028, ADUC7029, ADUC7030, ADUC7032, ; ADUC7033, ADUC7034, ADUC7036, ADUC7039, ADUC7060, ADUC7061, ADUC7121, ; ADUC7122, ADUC7124, ADUC7128, ADUC7129, ADUC7229, ADUCM301, ADUCM330, ; ADUCM331, ADUCM360, ADUCM361, ADUCRF101, AGOLD610-BT, AM1705, AM1707, AM1802, ; AM1806, AM1808, AM1810, AM3352, AM3352-CM3, AM3354, AM3354-CM3, AM3356, ; AM3356-CM3, AM3357, AM3357-CM3, AM3358, AM3358-CM3, AM3359, AM3359-CM3, ; AM3505, AM3517, AM3703, AM3715, AM3872, AM3872IVA1, AM3872IVA2, AM3874, ; AM3874IVA1, AM3874IVA2, AM3892, AM3892IVA1, AM3892IVA2, AM3892IVA3, AM3894, ; AM3894IVA1, AM3894IVA2, AM3894IVA3, AM43XX, AM43XX-CM3, AP9500, APM883208-X1, ; APM883308-X1, ARM1020E, ARM1022E, ARM1026EJ-S, ARM1136J, ARM1136JF, ; ARM1156T2, ARM1156T2F, ARM1176JZ, ARM1176JZF, ARM11MPCORE, ARM710T, ARM720T, ; ARM720TR4, ARM740TD, ARM7DI, ARM7EJS, ARM7TDMI, ARM7TDMIS, ARM915T, ARM920T, ; ARM920T-VFP, ARM922T, ARM925T, ARM926EJ-S, ARM926EJ-VFP, ARM940T, ARM946E-S, ; ARM946E-VFP, ARM966E-S, ARM966E-VFP, ARM968E-S, ARM9E-S, ARM9EJ, ARM9TDMI, ; ARMV8, ARRIAVSOC, AST2300, AST2400, AT91CAP7E, AT91CAP7S250A, AT91CAP7S450A, ; AT91CAP9E, AT91CAP9EC, AT91CAP9S250A, AT91CAP9S500A, AT91CAP9SC250A, ; AT91CAP9SC500A, AT91F40416, AT91F40816, AT91FR40162, AT91FR40162S, ; AT91FR4042, AT91FR4081, AT91M40400, AT91M40800, AT91M40807, AT91M42800A, ; AT91M43300, AT91M55800A, AT91M63200, AT91R40008, AT91R40807, AT91RM3400, ; AT91RM9200, AT91SAM3A4C, AT91SAM3A8C, AT91SAM3N00A, AT91SAM3N00B, ; AT91SAM3N0A, AT91SAM3N0B, AT91SAM3N0C, AT91SAM3N1A, AT91SAM3N1B, AT91SAM3N1C, ; AT91SAM3N2A, AT91SAM3N2B, AT91SAM3N2C, AT91SAM3N4A, AT91SAM3N4B, AT91SAM3N4C, ; AT91SAM3S16C, AT91SAM3S1A, AT91SAM3S1B, AT91SAM3S1C, AT91SAM3S2A, ; AT91SAM3S2B, AT91SAM3S2C, AT91SAM3S4A, AT91SAM3S4B, AT91SAM3S4C, AT91SAM3S8B, ; AT91SAM3S8C, AT91SAM3SD8B, AT91SAM3SD8C, AT91SAM3U1C, AT91SAM3U1E, ; AT91SAM3U2C, AT91SAM3U2E, AT91SAM3U4C, AT91SAM3U4E, AT91SAM3X4C, AT91SAM3X4E, ; AT91SAM3X8C, AT91SAM3X8E, AT91SAM7A1, AT91SAM7A2, AT91SAM7A3, AT91SAM7L128, ; AT91SAM7L64, AT91SAM7S128, AT91SAM7S256, AT91SAM7S32, AT91SAM7S321, ; AT91SAM7S512, AT91SAM7S64, AT91SAM7SE256, AT91SAM7SE32, AT91SAM7SE512, ; AT91SAM7X128, AT91SAM7X256, AT91SAM7X512, AT91SAM7XC128, AT91SAM7XC256, ; AT91SAM7XC512, AT91SAM9260, AT91SAM9261, AT91SAM9263, AT91SAM9G10, ; AT91SAM9G15, AT91SAM9G20, AT91SAM9G25, AT91SAM9G35, AT91SAM9G45, AT91SAM9G46, ; AT91SAM9M10, AT91SAM9M11, AT91SAM9N12, AT91SAM9R64, AT91SAM9RL64, ; AT91SAM9X25, AT91SAM9X35, AT91SAM9XE128, AT91SAM9XE256, AT91SAM9XE512, ATLAS, ; ATLAS-L, ATSAM4E16C, ATSAM4E16E, ATSAM4E8C, ATSAM4E8E, ATSAM4LC2A, ; ATSAM4LC2B, ATSAM4LC2C, ATSAM4LC4A, ATSAM4LC4B, ATSAM4LC4C, ATSAM4LC8A, ; ATSAM4LC8B, ATSAM4LC8C, ATSAM4LS2A, ATSAM4LS2B, ATSAM4LS2C, ATSAM4LS4A, ; ATSAM4LS4B, ATSAM4LS4C, ATSAM4LS8A, ATSAM4LS8B, ATSAM4LS8C, ATSAM4N16B, ; ATSAM4N16C, ATSAM4N8A, ATSAM4N8B, ATSAM4N8C, ATSAM4S16A, ATSAM4S16B, ; ATSAM4S16C, ATSAM4S8A, ATSAM4S8B, ATSAM4S8C, ATSAM4SA16B, ATSAM4SA16C, ; ATSAM4SD16B, ATSAM4SD16C, ATSAM4SD32B, ATSAM4SD32C, ATSAMA5D31, ATSAMA5D33, ; ATSAMA5D34, ATSAMA5D35, ATSAMD20E14, ATSAMD20E15, ATSAMD20E16, ATSAMD20E17, ; ATSAMD20G14, ATSAMD20G15, ATSAMD20G16, ATSAMD20G17, ATSAMD20G18, ATSAMD20J14, ; ATSAMD20J15, ATSAMD20J16, ATSAMD20J17, ATSAMD20J18, ATSAMG51, ATSAMG53, ; AXM5516, BCM4708, BCM47081, BCM63138, C5402, C5404, C5407, C5409, C5410, ; C5416, C5420, C5421, C5441, C5470, C5471, C549, C54X, C5501, C5502, C5503, ; C5506, C5507, C5508, C5509, C5510, C5515, C5532, C5533, C5534, C5535, C55X, ; C55X+, C620X, C6211B, C621X, C6411, C6412, C6413, C6414, C6415, C6416, C6418, ; C6424, C6455, C6482, C6488, C64X, C64X+, C6655, C6657, C6670, C6678, C670X, ; C6711D, C6712D, C6713B, C671X, C672X, C674X, C6A8143, C6A8143DSP, ; C6A8143IVA1, C6A8143IVA2, C6A8147, C6A8147DSP, C6A8147IVA1, C6A8147IVA2, ; C6A8148, C6A8148DSP, C6A8148IVA1, C6A8148IVA2, C6A8167, C6A8167DSP, ; C6A8167IVA1, C6A8167IVA2, C6A8167IVA3, C6A8168, C6A8168DSP, C6A8168IVA1, ; C6A8168IVA2, C6A8168IVA3, CALYPSO, CASTINE, CC2530F128, CC2530F256, ; CC2530F32, CC2530F64, CC2531F128, CC2531F256, CC2533F32, CC2533F64, ; CC2533F96, CC2538F128, CC2538F256, CC2538F512, CE2110, CNS1101, CNS1102, ; CNS1104, CNS1105, CNS1109, CNS1202, CNS1205, CNS2131, CNS2132, CNS2133, ; CNS2181, CNS2182X, CNS3410, CNS3420, CNS3420-CORE0, CNS3420-CORE1, ; CORONA-CM0, CORONA-CM4, CORTEXA12, CORTEXA12MPCORE, CORTEXA15, CORTEXA15A7, ; CORTEXA15MPCORE, CORTEXA5, CORTEXA53, CORTEXA57, CORTEXA57A53, ; CORTEXA5MPCORE, CORTEXA7, CORTEXA7MPCORE, CORTEXA8, CORTEXA9, CORTEXA9MPCORE, ; CORTEXM0, CORTEXM0+, CORTEXM1, CORTEXM1ALTERA, CORTEXM3, CORTEXM4, CORTEXM4F, ; CORTEXR4, CORTEXR4F, CORTEXR5, CORTEXR5F, CORTEXR5MPCORE, CORTEXR7, ; CORTEXR7F, CORTEXR7MPCORE, CS7522, CS7542, CY8C5245, CY8C5246, CY8C5247, ; CY8C5248, CY8C5385, CY8C5386, CY8C5387, CY8C5388, CY8C5485, CY8C5486, ; CY8C5487, CY8C5488, CY8C5585, CY8C5586, CY8C5587, CY8C5588, CYCLONEVSOC, ; CYUSB3014, DA828, DA830, DAVINCI, DB5500, DB5500APECORE0, DB5500APECORE1, ; DB5500MOD, DB8500, DB8500APECORE0, DB8500APECORE1, DB8500MODCORE1, ; DB8500MODCORE2, DB8540, DB8540APECORE0, DB8540APECORE1, DB8540XMIPAPE, ; DB8540XMIPMSSCPUA, DB8540XMIPMSSCPUB, DB9540, DB9540APE-CORE0, ; DB9540APE-CORE1, DB9540MOD-CORE1, DB9540MOD-CORE2, DELTA, DEMONSTRATOR, ; DM320, DM335, DM355, DM357, DM365, DM368, DM3725, DM3725IVA, DM3730, ; DM3730IVA, DM640, DM641, DM642, DM643, DM6431, DM6433, DM6435, DM6437, ; DM6441, DM6443, DM6446, DM6467, DM647, DM648, DM8147, DM8147DSP, DM8147IVA1, ; DM8147IVA2, DM8148, DM8148DSP, DM8148IVA1, DM8148IVA2, DM8165, DM8165DSP, ; DM8165IVA1, DM8165IVA2, DM8165IVA3, DM8166, DM8166DSP, DM8166IVA1, ; DM8166IVA2, DM8166IVA3, DM8167, DM8167DSP, DM8167IVA1, DM8167IVA2, ; DM8167IVA3, DM8168, DM8168DSP, DM8168IVA1, DM8168IVA2, DM8168IVA3, DRA62X, ; DRA62XDSP, DRA62XIVA1, DRA62XIVA2, DRA6XX, DRA6XXDSP, DRA6XXIVA1, DRA6XXIVA2, ; FA526, FA606TE, FA626, FA626TE, FA726TE, HANCOCK3GUMA, HSM, IPQ8064, IXC1100, ; IXP2325, IXP2350, IXP2400, IXP2800, IXP2805, IXP2850, IXP2855, IXP420, ; IXP421, IXP422, IXP423, IXP425, IXP430, IXP431, IXP432, IXP433, IXP435, ; IXP455, IXP460, IXP465, JANUS2, JANUS220, JANUS2CC, JENNYACC-CORE0, ; JENNYACC-CORE1, JENNYAPE, K10N1M0VYY120, K10N32VYY50, K10N512VYY100, ; K10N64VYY50, K10X128VYY100, K10X128VYY50, K10X128VYY72, K10X256VYY100, ; K10X256VYY72, K10X32VYY50, K10X512VYY120, K10X64VYY50, K20N1M0VYY120, ; K20N32VYY50, K20N512VYY100, K20N64VYY50, K20X128VYY100, K20X128VYY50, ; K20X128VYY72, K20X256VYY100, K20X256VYY72, K20X32VYY50, K20X512VYY120, ; K20X64VYY50, K30N512VYY100, K30X128VYY100, K30X128VYY72, K30X256VYY100, ; K30X256VYY72, K30X64VYY50, K40N512VYY100, K40X128VYY100, K40X128VYY72, ; K40X256VYY100, K40X256VYY72, K50N512CYY100, K50X128CYY72, K50X256CYY100, ; K50X256CYY72, K51N256CYY100, K51N512CYY100, K51X128CYY72, K51X256CYY100, ; K51X256CYY72, K52N512CYY100, K53N512CYY100, K53X256CYY100, K60N1M0VYY120, ; K60N1M0VYY150, K60N256VYY100, K60N512VYY100, K60X256VYY100, K60X512VYY120, ; K60X512VYY150, K70FN1M0VYY12, K70FN1M0VYY15, K70FX512VYY12, K70FX512VYY15, ; KINETIS, KIRA100, KRAIT, KS32C50100, LC1711, LEAD3PH2, LEAD3PH2T, LEAD3PH3, ; LEAD3PH3T, LEAD3PH4, LEAD3PH4T, LH75401, LH75410, LH77790, LH79520, LH7A400, ; LH7A404, LM3S101, LM3S102, LM3S1110, LM3S1133, LM3S1138, LM3S1150, LM3S1162, ; LM3S1165, LM3S1332, LM3S1435, LM3S1439, LM3S1512, LM3S1538, LM3S1601, ; LM3S1607, LM3S1608, LM3S1620, LM3S1621, LM3S1625, LM3S1626, LM3S1627, ; LM3S1635, LM3S1637, LM3S1651, LM3S1751, LM3S1776, LM3S1811, LM3S1816, ; LM3S1850, LM3S1911, LM3S1918, LM3S1937, LM3S1958, LM3S1960, LM3S1968, ; LM3S1B21, LM3S1J11, LM3S1J16, LM3S1N11, LM3S1N16, LM3S1P51, LM3S1R21, ; LM3S1R26, LM3S1W16, LM3S1Z16, LM3S2110, LM3S2139, LM3S2276, LM3S2410, ; LM3S2412, LM3S2432, LM3S2533, LM3S2601, LM3S2608, LM3S2616, LM3S2620, ; LM3S2637, LM3S2651, LM3S2671, LM3S2678, LM3S2730, LM3S2739, LM3S2776, ; LM3S2793, LM3S2911, LM3S2918, LM3S2939, LM3S2948, LM3S2950, LM3S2965, ; LM3S2B93, LM3S300, LM3S301, LM3S308, LM3S310, LM3S315, LM3S316, LM3S317, ; LM3S328, LM3S3634, LM3S3651, LM3S3739, LM3S3748, LM3S3749, LM3S3759, ; LM3S3768, LM3S3826, LM3S3J26, LM3S3N26, LM3S3W26, LM3S3Z26, LM3S5632, ; LM3S5651, LM3S5652, LM3S5656, LM3S5662, LM3S5732, LM3S5737, LM3S5739, ; LM3S5747, LM3S5749, LM3S5752, LM3S5757, LM3S5762, LM3S5767, LM3S5768, ; LM3S5769, LM3S5791, LM3S5951, LM3S5956, LM3S5B91, LM3S5C31, LM3S5K31, ; LM3S5K36, LM3S5P31, LM3S5P36, LM3S5P51, LM3S5P56, LM3S5R31, LM3S5R36, ; LM3S5T36, LM3S5Y36, LM3S600, LM3S601, LM3S608, LM3S610, LM3S6100, LM3S611, ; LM3S6110, LM3S612, LM3S613, LM3S615, LM3S617, LM3S618, LM3S628, LM3S6420, ; LM3S6422, LM3S6432, LM3S6537, LM3S6610, LM3S6611, LM3S6618, LM3S6633, ; LM3S6637, LM3S6730, LM3S6753, LM3S6911, LM3S6918, LM3S6938, LM3S6950, ; LM3S6952, LM3S6965, LM3S800, LM3S801, LM3S808, LM3S811, LM3S812, LM3S815, ; LM3S817, LM3S818, LM3S828, LM3S8530, LM3S8538, LM3S8630, LM3S8730, LM3S8733, ; LM3S8738, LM3S8930, LM3S8933, LM3S8938, LM3S8962, LM3S8970, LM3S8971, ; LM3S9781, LM3S9790, LM3S9792, LM3S9997, LM3S9B81, LM3S9B90, LM3S9B92, ; LM3S9B95, LM3S9B96, LM3S9L97, LM4F110B2QR, LM4F110C4QR, LM4F110E5QR, ; LM4F110H5QR, LM4F111B2QR, LM4F111C4QR, LM4F111E5QR, LM4F111H5QR, LM4F112C4QC, ; LM4F112E5QC, LM4F112H5QC, LM4F112H5QD, LM4F120B2QR, LM4F120C4QR, LM4F120E5QR, ; LM4F120H5QR, LM4F121B2QR, LM4F121C4QR, LM4F121E5QR, LM4F121H5QR, LM4F122C4QC, ; LM4F122E5QC, LM4F122H5QC, LM4F122H5QD, LM4F130C4QR, LM4F130E5QR, LM4F130H5QR, ; LM4F131C4QR, LM4F131E5QR, LM4F131H5QR, LM4F132C4QC, LM4F132E5QC, LM4F132H5QC, ; LM4F132H5QD, LM4F230E5QR, LM4F230H5QR, LM4F231E5QR, LM4F231H5QR, LM4F232E5QC, ; LM4F232H5QC, LM4F232H5QD, LPC1101LV, LPC1102, LPC1102LV, LPC1110, ; LPC1111/002, LPC1111/101, LPC1111/102, LPC1111/103, LPC1111/201, LPC1111/202, ; LPC1111/203, LPC1112/101, LPC1112/102, LPC1112/103, LPC1112/201, LPC1112/202, ; LPC1112/203, LPC1112LV, LPC1113/201, LPC1113/202, LPC1113/203, LPC1113/301, ; LPC1113/302, LPC1113/303, LPC1114/102, LPC1114/201, LPC1114/202, LPC1114/203, ; LPC1114/301, LPC1114/302, LPC1114/303, LPC1114/323, LPC1114/333, LPC1114LV, ; LPC1115/303, LPC11A02, LPC11A04, LPC11A11, LPC11A12, LPC11A13, LPC11A14, ; LPC11C12, LPC11C14, LPC11C22, LPC11C24, LPC11D14, LPC11E11, LPC11E12, ; LPC11E13, LPC11E14, LPC11E36, LPC11E37, LPC11E37H, LPC11U12/201, ; LPC11U13/201, LPC11U14/201, LPC11U23/301, LPC11U24/301, LPC11U24/401, ; LPC1224, LPC1225, LPC1226, LPC1227, LPC12D27, LPC1311, LPC1313, LPC1315, ; LPC1316, LPC1317, LPC1342, LPC1343, LPC1345, LPC1346, LPC1347, LPC1751, ; LPC1752, LPC1754, LPC1756, LPC1758, LPC1759, LPC1763, LPC1764, LPC1765, ; LPC1766, LPC1767, LPC1768, LPC1769, LPC1770, LPC1772, LPC1774, LPC1776, ; LPC1777, LPC1778, LPC1780, LPC1781, LPC1785, LPC1786, LPC1787, LPC1788, ; LPC1810, LPC1812, LPC1813, LPC1815, LPC1817, LPC1820, LPC1822, LPC1823, ; LPC1825, LPC1827, LPC1830, LPC1833, LPC1837, LPC1850, LPC1853, LPC1857, ; LPC2101, LPC2102, LPC2103, LPC2104, LPC2105, LPC2106, LPC2109, LPC2112, ; LPC2114, LPC2119, LPC2124, LPC2129, LPC2131, LPC2131/01, LPC2132, LPC2132/01, ; LPC2134, LPC2134/01, LPC2136, LPC2136/01, LPC2138, LPC2138/01, LPC2141, ; LPC2142, LPC2144, LPC2146, LPC2148, LPC2157, LPC2158, LPC2194, LPC2210, ; LPC2212, LPC2214, LPC2220, LPC2290, LPC2292, LPC2294, LPC2361, LPC2362, ; LPC2364, LPC2365, LPC2366, LPC2367, LPC2368, LPC2377, LPC2378, LPC2387, ; LPC2388, LPC2420, LPC2458, LPC2460, LPC2468, LPC2470, LPC2478, LPC2880, ; LPC2888, LPC2915, LPC2917, LPC2917/01, LPC2919, LPC2919/01, LPC2921, LPC2923, ; LPC2925, LPC2926, LPC2927, LPC2929, LPC2930, LPC2939, LPC3130, LPC3131, ; LPC3141, LPC3143, LPC3152, LPC3154, LPC3180, LPC3220, LPC3230, LPC3240, ; LPC3250, LPC4072FBD80, LPC4072FET80, LPC4074FBD144, LPC4074FBD80, ; LPC4076FBD144, LPC4076FET180, LPC4078FBD100, LPC4078FBD144, LPC4078FBD208, ; LPC4078FBD80, LPC4078FET180, LPC4078FET208, LPC4088FBD144, LPC4088FBD208, ; LPC4088FET180, LPC4088FET208, LPC4310FBD144, LPC4310FBD144-M0, LPC4310FET100, ; LPC4310FET100-M0, LPC4320FBD100, LPC4320FBD100-M0, LPC4320FBD144, ; LPC4320FBD144-M0, LPC4320FET100, LPC4320FET100-M0, LPC4330FBD144, ; LPC4330FBD144-M0, LPC4330FET100, LPC4330FET100-M0, LPC4330FET180, ; LPC4330FET180-M0, LPC4330FET256, LPC4330FET256-M0, LPC4333FBD144, ; LPC4333FBD144-M0, LPC4333FET100, LPC4333FET100-M0, LPC4333FET180, ; LPC4333FET180-M0, LPC4333FET256, LPC4333FET256-M0, LPC4337FBD144, ; LPC4337FBD144-M0, LPC4337FET100, LPC4337FET100-M0, LPC4337FET180, ; LPC4337FET180-M0, LPC4337FET256, LPC4337FET256-M0, LPC4350FBD208, ; LPC4350FBD208-M0, LPC4350FET180, LPC4350FET180-M0, LPC4350FET256, ; LPC4350FET256-M0, LPC4353FBD208, LPC4353FBD208-M0, LPC4353FET180, ; LPC4353FET180-M0, LPC4353FET256, LPC4353FET256-M0, LPC4357FBD208, ; LPC4357FBD208-M0, LPC4357FET256, LPC4357FET256-M0, LPC810M021FN8, ; LPC811M001FDH16, LPC812M101FD20, LPC812M101FDH16, LPC812M101FDH20, M0516LAN, ; M0516ZAN, M052LAN, M052ZAN, M054LAN, M054ZAN, M058LAN, M058ZAN, M1366, ; M1366-BT, M1548, M2S005, M2S010, M2S025, M2S050, M2S080, M2S120, MAC7101, ; MAC7104, MAC7105, MAC7106, MAC7111, MAC7112, MAC7114, MAC7115, MAC7116, ; MAC7121, MAC7122, MAC7124, MAC7125, MAC7126, MAC7131, MAC7134, MAC7135, ; MAC7136, MAC7141, MAC7142, MAC7202, MAC7212, MAC7222, MAC7241, MAC7242, ; MAC7252, MAX32600M64A, MAX32600M64B, MAX32600M74A, MAX32600M74B, ; MAX32600M75A, MAX32600M75B, MAX32600M85A, MAX32600M85B, MAX32600P85A, ; MAX32600P85B, MAX32601K64A, MAX32601K64B, MAX32601K74A, MAX32601K74B, ; MAX32601K75A, MAX32601K75B, MAX32601K85A, MAX32601K85B, MB86H60, MB86H61, ; MB86R01, MB86R02, MB86R03, MB86R11, MB86R12, MB9AF102N, MB9AF102R, MB9AF104N, ; MB9AF104R, MB9AF105NA, MB9AF105RA, MB9AF111K, MB9AF111L, MB9AF111M, ; MB9AF111N, MB9AF112K, MB9AF112L, MB9AF112M, MB9AF112N, MB9AF114L, MB9AF114M, ; MB9AF114N, MB9AF115M, MB9AF115N, MB9AF116M, MB9AF116N, MB9AF131L, MB9AF131M, ; MB9AF131N, MB9AF132K, MB9AF132L, MB9AF132M, MB9AF132N, MB9AF141L, MB9AF141M, ; MB9AF141N, MB9AF142L, MB9AF142M, MB9AF142N, MB9AF144L, MB9AF144M, MB9AF144N, ; MB9AF311K, MB9AF311L, MB9AF311M, MB9AF311N, MB9AF312K, MB9AF312L, MB9AF312M, ; MB9AF312N, MB9AF314L, MB9AF314M, MB9AF314N, MB9AF315M, MB9AF315N, MB9AF316M, ; MB9AF316N, MB9AF341L, MB9AF341M, MB9AF341N, MB9AF342L, MB9AF342M, MB9AF342N, ; MB9AF344L, MB9AF344M, MB9AF344N, MB9AFA31L, MB9AFA31M, MB9AFA31N, MB9AFA32L, ; MB9AFA32M, MB9AFA32N, MB9AFA41L, MB9AFA41M, MB9AFA41N, MB9AFA42L, MB9AFA42M, ; MB9AFA42N, MB9AFA44L, MB9AFA44M, MB9AFA44N, MB9AFB41L, MB9AFB41M, MB9AFB41N, ; MB9AFB42L, MB9AFB42M, MB9AFB42N, MB9AFB44L, MB9AFB44M, MB9AFB44N, MB9BF104N, ; MB9BF104R, MB9BF105N, MB9BF105R, MB9BF106N, MB9BF106R, MB9BF112N, MB9BF112R, ; MB9BF114N, MB9BF114R, MB9BF115N, MB9BF115R, MB9BF116N, MB9BF116R, MB9BF116S, ; MB9BF116T, MB9BF117S, MB9BF117T, MB9BF118S, MB9BF118T, MB9BF164K, MB9BF164L, ; MB9BF165K, MB9BF165L, MB9BF166K, MB9BF166L, MB9BF166M, MB9BF166N, MB9BF166R, ; MB9BF167M, MB9BF167N, MB9BF167R, MB9BF168M, MB9BF168N, MB9BF168R, MB9BF216S, ; MB9BF216T, MB9BF217S, MB9BF217T, MB9BF218S, MB9BF218T, MB9BF304N, MB9BF304R, ; MB9BF305N, MB9BF305R, MB9BF306N, MB9BF306R, MB9BF312N, MB9BF312R, MB9BF314N, ; MB9BF314R, MB9BF315N, MB9BF315R, MB9BF316N, MB9BF316R, MB9BF316S, MB9BF316T, ; MB9BF317S, MB9BF317T, MB9BF318S, MB9BF318T, MB9BF364K, MB9BF364L, MB9BF365K, ; MB9BF365L, MB9BF366K, MB9BF366L, MB9BF366M, MB9BF366N, MB9BF366R, MB9BF367M, ; MB9BF367N, MB9BF367R, MB9BF368M, MB9BF368N, MB9BF368R, MB9BF404N, MB9BF404R, ; MB9BF405N, MB9BF405R, MB9BF406N, MB9BF406R, MB9BF412N, MB9BF412R, MB9BF414N, ; MB9BF414R, MB9BF415N, MB9BF415R, MB9BF416N, MB9BF416R, MB9BF416S, MB9BF416T, ; MB9BF417S, MB9BF417T, MB9BF418S, MB9BF418T, MB9BF464K, MB9BF464L, MB9BF465K, ; MB9BF465L, MB9BF466K, MB9BF466L, MB9BF466M, MB9BF466N, MB9BF466R, MB9BF467M, ; MB9BF467N, MB9BF467R, MB9BF468M, MB9BF468N, MB9BF468R, MB9BF504N, MB9BF504R, ; MB9BF505N, MB9BF505R, MB9BF506N, MB9BF506R, MB9BF512N, MB9BF512R, MB9BF514N, ; MB9BF514R, MB9BF515N, MB9BF515R, MB9BF516N, MB9BF516R, MB9BF516S, MB9BF516T, ; MB9BF517S, MB9BF517T, MB9BF518S, MB9BF518T, MB9BF564K, MB9BF564L, MB9BF565K, ; MB9BF565L, MB9BF566K, MB9BF566L, MB9BF566M, MB9BF566N, MB9BF566R, MB9BF567M, ; MB9BF567N, MB9BF567R, MB9BF568M, MB9BF568N, MB9BF568R, MB9BF616S, MB9BF616T, ; MB9BF617S, MB9BF617T, MB9BF618S, MB9BF618T, MB9DF125, MB9DF126, MB9EF126, ; MK10DN128VEX5, MK10DN128VFM5, MK10DN128VFT5, MK10DN128VLF5, MK10DN128VLH5, ; MK10DN128VMP5, MK10DN32VEX5, MK10DN32VFT5, MK10DN32VLF5, MK10DN32VLH5, ; MK10DN32VMP5, MK10DN512VLK10, MK10DN512VLQ10, MK10DN512VMB10, MK10DN512VMC10, ; MK10DN512VMD10, MK10DN64VEX5, MK10DN64VFM5, MK10DN64VFT5, MK10DN64VLF5, ; MK10DN64VMP5, MK10DX128VEX5, MK10DX128VEX7, MK10DX128VFM5, MK10DX128VFT5, ; MK10DX128VLF5, MK10DX128VLH7, MK10DX128VLK7, MK10DX128VLL7, MK10DX128VLQ10, ; MK10DX128VMC7, MK10DX128VMP5, MK10DX256VEX7, MK10DX256VLH7, MK10DX256VLK7, ; MK10DX256VLL7, MK10DX256VLQ10, MK10DX256VMC7, MK10DX32VEX5, MK10DX32VFM5, ; MK10DX32VFT5, MK10DX32VLF5, MK10DX32VMP5, MK10DX64VEX5, MK10DX64VEX7, ; MK10DX64VFM5, MK10DX64VFT5, MK10DX64VLF5, MK10DX64VLH7, MK10DX64VLK7, ; MK10DX64VMC7, MK10DX64VMP5, MK10FN1M0VMD12, MK10FX512VLQ12, MK11DN512VLK5, ; MK11DN512VMC5, MK11DX128VLK5, MK11DX128VMC5, MK11DX256VLK5, MK11DX256VMC5, ; MK12DN512VLH5, MK12DN512VLK5, MK12DN512VMC5, MK12DX128VLF5, MK12DX128VLH5, ; MK12DX128VLK5, MK12DX128VMC5, MK12DX256VLF5, MK12DX256VLH5, MK12DX256VLK5, ; MK12DX256VMC5, MK14LN32VFM4, MK14LN32VFT4, MK14LN32VLF4, MK14LN32VLH4, ; MK14LN32VLK4, MK14LN64VFM4, MK14LN64VFT4, MK14LN64VLF4, MK14LN64VLH4, ; MK14LN64VLK4, MK15LN128VFM4, MK15LN128VFT4, MK15LN128VLF4, MK15LN128VLH4, ; MK15LN128VLK4, MK15LN32VFM4, MK15LN32VFT4, MK15LN32VLF4, MK15LN32VLH4, ; MK15LN32VLK4, MK15LN64VFM4, MK15LN64VFT4, MK15LN64VLF4, MK15LN64VLH4, ; MK15LN64VLK4, MK20DN128VEX5, MK20DN128VFM5, MK20DN128VFT5, MK20DN128VLF5, ; MK20DN128VLH5, MK20DN128VMP5, MK20DN32VEX5, MK20DN32VFM5, MK20DN32VFT5, ; MK20DN32VLF5, MK20DN32VMP5, MK20DN512VLK10, MK20DN512VLL10, MK20DN512VLQ10, ; MK20DN512VMB10, MK20DN512VMC10, MK20DN512ZAB10, MK20DN512ZCAB10, ; MK20DN64VEX5, MK20DN64VFM5, MK20DN64VFT5, MK20DN64VLF5, MK20DN64VMP5, ; MK20DX128VEX5, MK20DX128VEX7, MK20DX128VFM5, MK20DX128VFT5, MK20DX128VLF5, ; MK20DX128VLH7, MK20DX128VLK7, MK20DX128VLQ10, MK20DX128VMC7, MK20DX128VML7, ; MK20DX128VMP5, MK20DX256VEX7, MK20DX256VLH7, MK20DX256VLK10, MK20DX256VLK7, ; MK20DX256VLL10, MK20DX256VLQ10, MK20DX256VMB10, MK20DX256VMC10, ; MK20DX256VMC7, MK20DX256VML7, MK20DX32VEX5, MK20DX32VFM5, MK20DX32VFT5, ; MK20DX32VLF5, MK20DX32VMP5, MK20DX64VEX5, MK20DX64VEX7, MK20DX64VFM5, ; MK20DX64VFT5, MK20DX64VLF5, MK20DX64VLH7, MK20DX64VLK7, MK20DX64VMC7, ; MK20DX64VMP5, MK20FN1M0VLQ12, MK20FX512VLQ12, MK21DN512VLK5, MK21DN512VMC5, ; MK21DX128VLK5, MK21DX128VMC5, MK21DX256VLK5, MK21DX256VMC5, MK21FN1M0VLQ12, ; MK21FN1M0VMC10, MK21FN1M0VMC12, MK21FN1M0VMD10, MK21FN1M0VMD12, ; MK21FX512VLQ12, MK21FX512VMC10, MK21FX512VMC12, MK21FX512VMD10, ; MK21FX512VMD12, MK22DN512VLH5, MK22DN512VLK5, MK22DN512VMC5, MK22DX128VLF5, ; MK22DX128VLH5, MK22DX128VLK5, MK22DX128VMC5, MK22DX256VLF5, MK22DX256VLH5, ; MK22DX256VLK5, MK22DX256VMC5, MK22FN1M0VLH10, MK22FN1M0VLH12, MK22FN1M0VLK10, ; MK22FN1M0VLK12, MK22FN1M0VLL10, MK22FN1M0VLL12, MK22FN1M0VLQ10, ; MK22FN1M0VLQ12, MK22FN1M0VMC10, MK22FN1M0VMC12, MK22FN1M0VMD12, ; MK22FX512VLH12, MK22FX512VLK12, MK22FX512VLL12, MK22FX512VMC12, ; MK22FX512VMD12, MK30DN512VLK10, MK30DN512VLL10, MK30DN512VLQ10, ; MK30DN512VMB10, MK30DN512VMC10, MK30DX128VEX7, MK30DX128VLH7, MK30DX128VLK7, ; MK30DX128VLL7, MK30DX128VLQ10, MK30DX128VMC7, MK30DX256VEX7, MK30DX256VLH7, ; MK30DX256VLK7, MK30DX256VLQ10, MK30DX256VMC7, MK30DX256VML7, MK30DX64VEX7, ; MK30DX64VLH7, MK30DX64VMC7, MK40DN512VLK10, MK40DN512VLL10, MK40DN512VLQ10, ; MK40DN512VMB10, MK40DN512VMC10, MK40DX128VEX7, MK40DX128VLH7, MK40DX128VLK7, ; MK40DX128VLQ10, MK40DX128VMC7, MK40DX128VML7, MK40DX256VEX7, MK40DX256VLH7, ; MK40DX256VLK7, MK40DX256VLL7, MK40DX256VLQ10, MK40DX256VMC7, MK40DX64VEX7, ; MK40DX64VLH7, MK40DX64VLK7, MK40DX64VMC7, MK50DN512CLL10, MK50DN512CLQ10, ; MK50DN512CMC10, MK50DX128CEX7, MK50DX128CLH7, MK50DX128CLK7, MK50DX128CLL7, ; MK50DX128CMC7, MK50DX256CLK10, MK50DX256CLK7, MK50DX256CLL10, MK50DX256CMC7, ; MK50DX256CMD10, MK50DX256CML7, MK51DN256CLQ10, MK51DN512CLL10, ; MK51DN512CLQ10, MK51DN512CMC10, MK51DX128CEX7, MK51DX128CLH7, MK51DX128CMC7, ; MK51DX256CLK10, MK51DX256CLK7, MK51DX256CLL10, MK51DX256CMC7, MK51DX256CML7, ; MK52DN512CLQ10, MK53DN512CLQ10, MK53DX256CLQ10, MK60DN256VLL10, ; MK60DN256VLQ10, MK60DN256VMC10, MK60DN512VLL10, MK60DN512VLQ10, ; MK60DN512VMC10, MK60DN512ZAB10, MK60DN512ZCAB10, MK60DX256VLL10, ; MK60DX256VLQ10, MK60DX256VMC10, MK60FN1M0VLQ12, MK60FN1M0VLQ15, ; MK60FX512VLQ12, MK60FX512VLQ15, MK61FN1M0CAA12, MK61FN1M0VMD12, ; MK61FN1M0VMD15, MK61FN1M0VMJ12, MK61FN1M0VMJ15, MK61FX512VMD12, ; MK61FX512VMD15, MK61FX512VMJ12, MK61FX512VMJ15, MKE02Z16VLC2, MKE02Z16VLC4, ; MKE02Z16VLD2, MKE02Z32VLC2, MKE02Z32VLC4, MKE02Z32VLD2, MKE02Z32VLD4, ; MKE02Z32VLH2, MKE02Z32VLH4, MKE02Z32VQH2, MKE02Z32VQH4, MKE02Z64VLC2, ; MKE02Z64VLD2, MKE02Z64VLD4, MKE02Z64VLH2, MKE02Z64VLH4, MKE02Z64VQH2, ; MKE02Z64VQH4, MKE04Z128VLD4, MKE04Z128VLH4, MKE04Z128VLK4, MKE04Z128VQH4, ; MKE04Z64VLD4, MKE04Z64VLH4, MKE04Z64VLK4, MKE04Z64VQH4, MKE06Z128VLD4, ; MKE06Z128VLH4, MKE06Z128VLK4, MKE06Z128VQH4, MKE06Z64VLD4, MKE06Z64VLH4, ; MKE06Z64VLK4, MKE06Z64VQH4, MKL02Z16VFG4, MKL02Z16VFK4, MKL02Z16VFM4, ; MKL02Z32CAF4, MKL02Z32VFG4, MKL02Z32VFK4, MKL02Z32VFM4, MKL02Z8VFG4, ; MKL04Z16VFK4, MKL04Z16VFM4, MKL04Z16VLC4, MKL04Z16VLF4, MKL04Z32VFK4, ; MKL04Z32VFM4, MKL04Z32VLC4, MKL04Z32VLF4, MKL04Z8VFK4, MKL04Z8VFM4, ; MKL04Z8VLC4, MKL05Z16VFK4, MKL05Z16VFM4, MKL05Z16VLC4, MKL05Z16VLF4, ; MKL05Z32VFK4, MKL05Z32VFM4, MKL05Z32VLC4, MKL05Z32VLF4, MKL05Z8VFK4, ; MKL05Z8VFM4, MKL05Z8VLC4, MKL14Z32VFM4, MKL14Z32VFT4, MKL14Z32VLH4, ; MKL14Z32VLK4, MKL14Z64VFM4, MKL14Z64VFT4, MKL14Z64VLH4, MKL14Z64VLK4, ; MKL15Z128VFM4, MKL15Z128VFT4, MKL15Z128VLH4, MKL15Z128VLK4, MKL15Z32VFM4, ; MKL15Z32VFT4, MKL15Z32VLH4, MKL15Z32VLK4, MKL15Z64VFM4, MKL15Z64VFT4, ; MKL15Z64VLH4, MKL15Z64VLK4, MKL16Z128VFM4, MKL16Z128VFT4, MKL16Z128VLH4, ; MKL16Z256VLH4, MKL16Z256VLK4, MKL16Z256VMP4, MKL16Z32VFM4, MKL16Z32VFT4, ; MKL16Z32VLH4, MKL16Z64VFM4, MKL16Z64VFT4, MKL16Z64VLH4, MKL24Z32VFM4, ; MKL24Z32VFT4, MKL24Z32VLH4, MKL24Z32VLK4, MKL24Z64VFM4, MKL24Z64VFT4, ; MKL24Z64VLH4, MKL24Z64VLK4, MKL25Z128VFM4, MKL25Z128VFT4, MKL25Z128VLH4, ; MKL25Z128VLK4, MKL25Z32VFM4, MKL25Z32VFT4, MKL25Z32VLH4, MKL25Z32VLK4, ; MKL25Z64VFM4, MKL25Z64VFT4, MKL25Z64VLH4, MKL25Z64VLK4, MKL26Z128VFM4, ; MKL26Z128VFT4, MKL26Z128VLH4, MKL26Z128VLL4, MKL26Z128VMC4, MKL26Z256VLH4, ; MKL26Z256VLK4, MKL26Z256VLL4, MKL26Z256VMC4, MKL26Z256VMP4, MKL26Z32VFM4, ; MKL26Z32VFT4, MKL26Z32VLH4, MKL26Z64VFM4, MKL26Z64VFT4, MKL26Z64VLH4, ; MKL34Z64VLH4, MKL34Z64VLL4, MKL36Z128VLH4, MKL36Z128VLL4, MKL36Z128VMC4, ; MKL36Z256VLH4, MKL36Z256VLL4, MKL36Z256VMC4, MKL36Z256VMP4, MKL36Z64VLH4, ; MKL36Z64VLL4, MKL46Z128VLH4, MKL46Z128VLL4, MKL46Z128VMC4, MKL46Z256VLH4, ; MKL46Z256VLL4, MKL46Z256VMC4, MKL46Z256VMP4, MKM14Z128CHH5, MKM33Z128CLH5, ; MKM34Z128CLL5, MKV10Z16VFM7, MKV10Z16VLC7, MKV10Z16VLF7, MKV10Z32VFM7, ; MKV10Z32VLC7, MKV10Z32VLF7, MKW01Z128CHN, MKW21D256VHA5, MKW22D512VHA5, ; MKW24D512VHA5, ML6962XX, MV76100, MV78100, MV78130V6, MV78130V7, MV78160V6, ; MV78160V7, MV78200-CPU0, MV78200-CPU1, MV78230V6, MV78230V7, MV78260V6, ; MV78260V7, MV78460V6, MV78460V7, MV8720, MXC91131, MXC91221, MXC91231, ; MXC91311, MXC91312, MXC91313, MXC91321, MXC91331, MXC91341, MXC92323, ; NETX100, NETX50, NETX500, NETX51, NS7520, NS9210, NS9215, NS9360, NS9750, ; NS9775, NUC100LC1BN, NUC100LD1BN, NUC100LD2BN, NUC100LD3AN, NUC100LE3AN, ; NUC100RC1BN, NUC100RD1BN, NUC100RD2BN, NUC100RD3AN, NUC100RE3AN, NUC100VD2AN, ; NUC100VD3AN, NUC100VE3AN, NUC120LC1BN, NUC120LD1BN, NUC120LD2BN, NUC120LD3AN, ; NUC120LE3AN, NUC120RC1BN, NUC120RD1BN, NUC120RD2BN, NUC120RD3AN, NUC120RE3AN, ; NUC120VD2AN, NUC120VD3AN, NUC120VE3AN, NUC122LC1AN, NUC122LD2AN, NUC122RC1AN, ; NUC122RD2AN, NUC122ZC1AN, NUC122ZD2AN, NUC130LC1BN, NUC130LC1CN, NUC130LD2BN, ; NUC130LD2CN, NUC130LD3AN, NUC130LE3AN, NUC130LE3CN, NUC130RC1BN, NUC130RC1CN, ; NUC130RD2BN, NUC130RD2CN, NUC130RD3AN, NUC130RE3AN, NUC130RE3CN, NUC130VD2AN, ; NUC130VD3AN, NUC130VE3AN, NUC130VE3CN, NUC140LC1BN, NUC140LC1CN, NUC140LD2BN, ; NUC140LD2CN, NUC140LD3AN, NUC140LE3AN, NUC140LE3CN, NUC140RC1BN, NUC140RC1CN, ; NUC140RD2BN, NUC140RD2CN, NUC140RD3AN, NUC140RE3AN, NUC140RE3CN, NUC140VD2AN, ; NUC140VD3AN, NUC140VE3AN, NUC140VE3CN, OMAP1510, OMAP1510DSP, OMAP1610, ; OMAP1610DSP, OMAP1611, OMAP1611DSP, OMAP1612, OMAP1612DSP, OMAP1710, ; OMAP1710DSP, OMAP2420, OMAP2420IVA, OMAP2420UMA, OMAP2430, OMAP2431, OMAP331, ; OMAP3410, OMAP3420, OMAP3430, OMAP3430SEQ, OMAP3440, OMAP3440SEQ, OMAP3503, ; OMAP3515, OMAP3525, OMAP3530, OMAP3610, OMAP3620, OMAP3630, OMAP3630SEQ, ; OMAP3640, OMAP3640SEQ, OMAP4430, OMAP4430APP1, OMAP4430APP2, OMAP4430DUCATI1, ; OMAP4430DUCATI2, OMAP4430IVA1, OMAP4430IVA2, OMAP4440, OMAP4440APP1, ; OMAP4440APP2, OMAP4440DUCATI1, OMAP4440DUCATI2, OMAP4440IVA1, OMAP4440IVA2, ; OMAP4470, OMAP4470APP1, OMAP4470APP2, OMAP4470DUCATI1, OMAP4470DUCATI2, ; OMAP4470IVA1, OMAP4470IVA2, OMAP5910DSP, OMAP5912DSP, OMAPV1030UMA, ; OMAPV1035UMA, OMAPV1230UMA, OMAPV2230UMA, OMAPV2320UMA, OMAPV2350UMA, ORION, ; PXA162, PXA166, PXA168, RCARH2-CA15, RCARH2-CA7, RCARM2, RM42L432, ; RM46L430-PGE, RM46L430-ZWT, RM46L440-PGE, RM46L440-ZWT, RM46L450-PGE, ; RM46L450-ZWT, RM46L830-PGE, RM46L830-ZWT, RM46L840-PGE, RM46L840-ZWT, ; RM46L850-PGE, RM46L850-ZWT, RM46L852-PGE, RM46L852-ZWT, RM48L530-PGE, ; RM48L530-ZWT, RM48L540-PGE, RM48L540-ZWT, RM48L550-PGE, RM48L550-ZWT, ; RM48L730-PGE, RM48L730-ZWT, RM48L740-PGE, RM48L740-ZWT, RM48L750-PGE, ; RM48L750-ZWT, RM48L930-PGE, RM48L930-ZWT, RM48L940-PGE, RM48L940-ZWT, ; RM48L950-PGE, RM48L950-ZWT, RM48L952-PGE, RM48L952-ZWT, RZA1H, S3C2410X, ; S3C2412X, S3C2413X, S3C2416, S3C2440A, S3C2442B, S3C2443X, S3C2450, S3C44BOX, ; S3C4510B, S3C6400X, S3C6410, S3C6410X, S3F401F, S3F4A0KJ, S3F4A0KR, S3F4A1HJ, ; S3F4A1HR, S3F4A2FJ, S3F4A2FR, S3FM02G, S3FMA1G, S3FMA1U, S3FN21D, S3FN22C, ; S3FN23B, S3FN249, S3FN41F, S3FN429, S3FN60D, S5PV210, S5PV310, SA1110, ; SAUSALITO, SBM7000, SC000, SC100, SC110, SC200, SC210, SC300, SCORPION, ; SE470R1VB8AD, SITARA, SPEAR1300, SPEAR1300-CORE0, SPEAR1300-CORE1, SPEAR1310, ; SPEAR1310REVC, SPEAR1340, SPEAR300, SPEAR310, SPEAR320, SPEAR320S, SPEAR600, ; SPEAR600-CORE0, SPEAR600-CORE1, STA2062, STA2063, STA2064, STA2064CPS, ; STA2065, STA2065CPS, STA2164, STA2164CPS, STA2165, STA2165CPS, STA8088, ; STARPRO2503, STARPRO2603, STELLARIS, STELLARISSTELLARIS, STM32F050C4, ; STM32F050C6, STM32F050K4, STM32F050K6, STM32F051C4, STM32F051C6, STM32F051C8, ; STM32F051K4, STM32F051K6, STM32F051K8, STM32F051R4, STM32F051R6, STM32F051R8, ; STM32F100C4, STM32F100C6, STM32F100C8, STM32F100CB, STM32F100R4, STM32F100R6, ; STM32F100R8, STM32F100RB, STM32F100RC, STM32F100RD, STM32F100RE, STM32F100V8, ; STM32F100VB, STM32F100VC, STM32F100VD, STM32F100VE, STM32F100ZC, STM32F100ZD, ; STM32F100ZE, STM32F101, STM32F101C4, STM32F101C6, STM32F101C8, STM32F101CB, ; STM32F101R4, STM32F101R6, STM32F101R8, STM32F101RB, STM32F101RC, STM32F101RD, ; STM32F101RE, STM32F101RF, STM32F101RG, STM32F101T4, STM32F101T6, STM32F101T8, ; STM32F101TB, STM32F101V8, STM32F101VB, STM32F101VC, STM32F101VD, STM32F101VE, ; STM32F101VF, STM32F101VG, STM32F101ZC, STM32F101ZD, STM32F101ZE, STM32F101ZF, ; STM32F101ZG, STM32F102C4, STM32F102C6, STM32F102C8, STM32F102CB, STM32F102R4, ; STM32F102R6, STM32F102R8, STM32F102RB, STM32F103, STM32F103C4, STM32F103C6, ; STM32F103C8, STM32F103CB, STM32F103R4, STM32F103R6, STM32F103R8, STM32F103RB, ; STM32F103RC, STM32F103RD, STM32F103RE, STM32F103RF, STM32F103RG, STM32F103T4, ; STM32F103T6, STM32F103T8, STM32F103TB, STM32F103V8, STM32F103VB, STM32F103VC, ; STM32F103VD, STM32F103VE, STM32F103VF, STM32F103VG, STM32F103ZC, STM32F103ZD, ; STM32F103ZE, STM32F103ZF, STM32F103ZG, STM32F105R8, STM32F105RB, STM32F105RC, ; STM32F105V8, STM32F105VB, STM32F105VC, STM32F107RB, STM32F107RC, STM32F107VB, ; STM32F107VC, STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG, ; STM32F205VB, STM32F205VC, STM32F205VE, STM32F205VF, STM32F205VG, STM32F205ZC, ; STM32F205ZE, STM32F205ZF, STM32F205ZG, STM32F207IC, STM32F207IE, STM32F207IF, ; STM32F207IG, STM32F207VC, STM32F207VE, STM32F207VG, STM32F207ZC, STM32F207ZE, ; STM32F207ZF, STM32F207ZG, STM32F215RE, STM32F215RG, STM32F215VE, STM32F215VG, ; STM32F215ZE, STM32F215ZG, STM32F217IE, STM32F217IG, STM32F217VE, STM32F217VG, ; STM32F217ZE, STM32F217ZG, STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, ; STM32F302VB, STM32F302VC, STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, ; STM32F303VB, STM32F303VC, STM32F313CC, STM32F313RC, STM32F313VC, STM32F372C8, ; STM32F372CB, STM32F372CC, STM32F372R8, STM32F372RB, STM32F372RC, STM32F372V8, ; STM32F372VB, STM32F372VC, STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, ; STM32F373RB, STM32F373RC, STM32F373V8, STM32F373VB, STM32F373VC, STM32F383CC, ; STM32F383RC, STM32F383VC, STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, ; STM32F401VB, STM32F401VC, STM32F405OE, STM32F405OG, STM32F405RG, STM32F405VG, ; STM32F405ZG, STM32F407IE, STM32F407IG, STM32F407VE, STM32F407VG, STM32F407ZE, ; STM32F407ZG, STM32F415OG, STM32F415RG, STM32F415VG, STM32F415ZG, STM32F417IE, ; STM32F417IG, STM32F417VE, STM32F417VG, STM32F417ZE, STM32F417ZG, STM32F427IG, ; STM32F427II, STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F429BG, ; STM32F429BI, STM32F429IG, STM32F429II, STM32F429NG, STM32F429NI, STM32F429VG, ; STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F437IG, STM32F437II, STM32F437VG, ; STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F439BG, STM32F439BI, STM32F439IG, ; STM32F439II, STM32F439NG, STM32F439NI, STM32F439VG, STM32F439VI, STM32F439ZG, ; STM32F439ZI, STM32L151C6, STM32L151C8, STM32L151CB, STM32L151QC, STM32L151QD, ; STM32L151R6, STM32L151R8, STM32L151RB, STM32L151RC, STM32L151RD, STM32L151V8, ; STM32L151VB, STM32L151VC, STM32L151VD, STM32L151ZC, STM32L151ZD, STM32L152C6, ; STM32L152C8, STM32L152CB, STM32L152QC, STM32L152QD, STM32L152R6, STM32L152R8, ; STM32L152RB, STM32L152RC, STM32L152RD, STM32L152V8, STM32L152VB, STM32L152VC, ; STM32L152VD, STM32L152ZC, STM32L152ZD, STM32L162QD, STM32L162RD, STM32L162VD, ; STM32L162ZD, STM32W108C8, STM32W108CB, STM32W108CC, STM32W108CZ, STM32W108HB, ; STN8810, STN8815, STN8820, STR710, STR711, STR712, STR715, STR730, STR731, ; STR735, STR736, STR750FV, STR751FR, STR752FR, STR755FR, STR755FV, STR910, ; STR910FAM32, STR910FAW32, STR910FAZ32, STR911, STR911FAM42, STR911FAM44, ; STR911FAM46, STR911FAM47, STR911FAW42, STR911FAW44, STR911FAW46, STR911FAW47, ; STR912, STR912FAW42, STR912FAW44, STR912FAW46, STR912FAW47, STR912FAZ42, ; STR912FAZ44, STR912FAZ46, STR912FAZ47, TC270TP, TC270TP-ASTEP, TC275TF, ; TC275TF-ASTEP, TC275TP, TC275TP-ASTEP, TC277TF, TC277TF-ASTEP, TC277TP, ; TC277TP-ASTEP, TC290TP, TC297TF, TC297TP, TC298TF, TC298TP, TC299TF, TC299TP, ; TC2D5T, TC2D5TE, TC2D7T, TC2D7TE, TCI6636K2H, TCI6638K2K, TCS2305, ; TCS2305DRP, TCS2305DSP, TEGRA3, TEGRA3PM, TEGRA4, TM4C1230C3PM, TM4C1230D5PM, ; TM4C1230E6PM, TM4C1230H6PM, TM4C1231C3PM, TM4C1231D5PM, TM4C1231D5PZ, ; TM4C1231E6PM, TM4C1231E6PZ, TM4C1231H6PGE, TM4C1231H6PM, TM4C1231H6PZ, ; TM4C1232C3PM, TM4C1232D5PM, TM4C1232E6PM, TM4C1232H6PM, TM4C1233C3PM, ; TM4C1233D5PM, TM4C1233D5PZ, TM4C1233E6PM, TM4C1233E6PZ, TM4C1233H6PGE, ; TM4C1233H6PM, TM4C1233H6PZ, TM4C1236D5PM, TM4C1236E6PM, TM4C1236H6PM, ; TM4C1237D5PM, TM4C1237D5PZ, TM4C1237E6PM, TM4C1237E6PZ, TM4C1237H6PGE, ; TM4C1237H6PM, TM4C1237H6PZ, TM4C123AE6PM, TM4C123AH6PM, TM4C123BE6PM, ; TM4C123BE6PZ, TM4C123BH6PGE, TM4C123BH6PM, TM4C123BH6PZ, TM4C123BH6ZRB, ; TM4C123FE6PM, TM4C123FH6PM, TM4C123GE6PM, TM4C123GE6PZ, TM4C123GH6PGE, ; TM4C123GH6PM, TM4C123GH6PZ, TM4C123GH6ZRB, TMPA900, TMPA901, TMPA910, ; TMPA911, TMPA912, TMPA913, TMPM320C1DFG, TMPM330FDWFG, TMPM330FWFG, ; TMPM330FYFG, TMPM332FWUG, TMPM333FDFG, TMPM333FWFG, TMPM333FYFG, ; TMPM341FDXBG, TMPM341FYXBG, TMPM342FYXBG, TMPM343F10XBG, TMPM343FDXBG, ; TMPM343FEXBG, TMPM360F20, TMPM361F10FG, TMPM361FDFG, TMPM361FYFG, ; TMPM362F10FG, TMPM363F10FG, TMPM364F10FG, TMPM365FYXBG, TMPM366FDFG, ; TMPM366FDXBG, TMPM366FWFG, TMPM366FWXBG, TMPM366FYFG, TMPM366FYXBG, ; TMPM367FDFG, TMPM367FDXBG, TMPM367FWFG, TMPM367FWXBG, TMPM367FYFG, ; TMPM367FYXBG, TMPM368FDFG, TMPM368FDXBG, TMPM369FDFG, TMPM369FDXBG, ; TMPM369FYFG, TMPM369FYXBG, TMPM36BF10FG, TMPM36BFYFG, TMPM370FYDFG, ; TMPM370FYFG, TMPM372FWFG, TMPM372FWUG, TMPM373FWDUG, TMPM374FWUG, ; TMPM375FSDMG, TMPM376FDDFG, TMPM376FDFG, TMPM380FWDFG, TMPM380FYDFG, ; TMPM380FYFG, TMPM382FSFG, TMPM382FWFG, TMPM384FDFG, TMPM390FWFG, ; TMPM395FWAXBG, TMS320C6201, TMS320C6202, TMS320C6203, TMS320C6204, ; TMS320C6205, TMS320C6701, TMS320C6722, TMS320C6726, TMS320C6727, TMS320C6748, ; TMS470AVF688A, TMS470AVF688B, TMS470AVF689A, TMS470AVF689B, TMS470MF031, ; TMS470MF042, TMS470MF066, TMS470MSF541, TMS470MSF542, TMS470PLF111, ; TMS470PLF212, TMS470PLF221, TMS470PLF312, TMS470PLF512, TMS470PLF521, ; TMS470PLF52A, TMS470PLFA21, TMS470PSF621, TMS470PSF761, TMS470PSF761A, ; TMS470PSF764, TMS470PTB5, TMS470PTB5BA, TMS470PVF241, TMS470PVF242, ; TMS470PVF243, TMS470PVF244, TMS470PVF245, TMS470PVF246, TMS470PVF247, ; TMS470PVF248, TMS470PVF341, TMS470PVF344, TMS470PVF345, TMS470PVF346, ; TMS470PVF347, TMS470PVF348, TMS470R1A128, TMS470R1A256, TMS470R1A288, ; TMS470R1A384, TMS470R1A64, TMS470R1B1M, TMS470R1B512, TMS470R1B768, ; TMS470R1F119, TMS470R1F11A, TMS470R1F314, TMS470R1F316, TMS470R1F318, ; TMS470R1F328, TMS470R1F354, TMS470R1F366A, TMS470R1F369, TMS470R1F376A, ; TMS470R1F45B, TMS470R1F55B, TMS470R1SF45B, TMS470R1SF55B, TMS470R1VB8CD, ; TMS470R1VC002, TMS470R1VC012, TMS470R1VC334A, TMS470R1VC336, TMS470R1VC336A, ; TMS470R1VC338, TMS470R1VC3382, TMS470R1VC346, TMS470R1VC346A, TMS470R1VC348, ; TMS470R1VC3482, TMS470R1VC688, TMS470R1VF012, TMS470R1VF104, TMS470R1VF288, ; TMS470R1VF334A, TMS470R1VF336, TMS470R1VF336A, TMS470R1VF338, TMS470R1VF3382, ; TMS470R1VF346A, TMS470R1VF348, TMS470R1VF3482, TMS470R1VF356A, ; TMS470R1VF356B, TMS470R1VF37A, TMS470R1VF438, TMS470R1VF448, TMS470R1VF45A, ; TMS470R1VF45AA, TMS470R1VF45B, TMS470R1VF478, TMS470R1VF478A, TMS470R1VF48B, ; TMS470R1VF48C, TMS470R1VF4B8, TMS470R1VF55B, TMS470R1VF55BA, TMS470R1VF56C, ; TMS470R1VF588, TMS470R1VF58C, TMS470R1VF5CC, TMS470R1VF67A, TMS470R1VF67AA, ; TMS470R1VF688, TMS470R1VF689, TMS470R1VF76B, TMS470R1VF7AC, TMS570LS0332, ; TMS570LS0432, TMS570LS10106-PGE, TMS570LS10106-ZWT, TMS570LS10116-PGE, ; TMS570LS10116-ZWT, TMS570LS10206-PGE, TMS570LS10206-ZWT, TMS570LS10216-PGE, ; TMS570LS10216-ZWT, TMS570LS1114-PGE, TMS570LS1114-ZWT, TMS570LS1115-PGE, ; TMS570LS1115-ZWT, TMS570LS1224-PGE, TMS570LS1224-ZWT, TMS570LS1225-PGE, ; TMS570LS1225-ZWT, TMS570LS1227-PGE, TMS570LS1227-ZWT, TMS570LS20206-PGE, ; TMS570LS20206-ZWT, TMS570LS20216-PGE, TMS570LS20216-ZWT, TMS570LS2124-PGE, ; TMS570LS2124-ZWT, TMS570LS2125-PGE, TMS570LS2125-ZWT, TMS570LS2134-PGE, ; TMS570LS2134-ZWT, TMS570LS2135-PGE, TMS570LS2135-ZWT, TMS570LS3134-PGE, ; TMS570LS3134-ZWT, TMS570LS3135-PGE, TMS570LS3135-ZWT, TMS570LS3137-PGE, ; TMS570LS3137-ZWT, TMS570PSF762, TMS570PSF762M, TMS570PSFC61, TNETC4800, ; TUS9090, VF11xR, VF12XR-CA5, VF31xR, VF32XR-CA5, VF3xx, VF4xx, VF51xR, ; VF52XR-CA5, VF5xx, VF6XX-CA5, VF6XX-CM4, VF7XX-CA5, VF7XX-CM4, WESTPORT, ; WESTPORT-L, WRIGLEY3G, WRIGLEY3GUMA, X-GENE, XGOLD213, XGOLD221, XGOLD221-BT, ; XGOLD223, XGOLD223-BT, XGOLD618, XGOLD618-3G, XGOLD626, XGOLD626-3G, ; XGOLD631, XGOLD631-3G, XGOLD632, XGOLD632-3G, XGOLD636, XGOLD636-3G, ; XGOLD706, XGOLD706-3G, XGOLD716, XGOLD716-3G, XGOLD726, XGOLD726-3G, ; XGOLD726-USPC, XGOLD7262, XGOLD7262-3G, XGOLD7262-USPC, XMC1100-F0008, ; XMC1100-F0016, XMC1100-F0032, XMC1100-F0064, XMC1200-F0200, XMC1201-F0016, ; XMC1201-F0032, XMC1201-F0064, XMC1201-F0200, XMC1202-X0016, XMC1202-X0032, ; XMC1301-F0008, XMC1301-F0016, XMC1301-F0032, XMC1302-X0016, XMC1302-X0032, ; XMC1302-X0064, XMC1302-X0200, XMC4100, XMC4104, XMC4104-X128, XMC4200, ; XMC4400, XMC4400-X256, XMC4402, XMC4500, XMC4500-X768, XMC4502, XMC4504, ; XMC4700, XSCALE, ZSSC1856, ZYNQ-7000, ZYNQ-7000CORE0, ZYNQ-7000CORE1 ; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm.per 13602 2021-08-30 08:21:16Z jboch $ config 16. 8. width 11. sif component.available("STM1") tree.close "STM1" base e:component.base("STM1",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif sif component.available("STM2") tree.close "STM2" base e:component.base("STM2",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif sif component.available("STM3") tree.close "STM3" base e:component.base("STM3",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif sif component.available("STM4") tree.close "STM4" base e:component.base("STM4",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif sif component.available("STM5") tree.close "STM5" base e:component.base("STM5",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif sif component.available("STM6") tree.close "STM6" base e:component.base("STM6",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif sif component.available("STM7") tree.close "STM7" base e:component.base("STM7",-1) width 12. tree "Primary Control and Status Registers" group.long 0xe80++0x3 line.long 0x00 "STMTCSR,Trace Control and Status Register" bitfld.long 0x00 23. " BUSY ,STM is busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--22. 1. " TRACEID ,ATB Trace ID" bitfld.long 0x00 5. " COMPEN ,Compression Enable for Stimulus Ports" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SYNCEN ,STMSYNCR is implemented" "Reserved,Implemented" bitfld.long 0x00 1. " TSEN ,Timestamp requests control" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Global STM enable" "Disabled,Enabled" wgroup.long 0xe84++0x3 line.long 0x00 "STMTSSTIMR,Timestamp Stimulus Register" bitfld.long 0x00 0. " FORCETS ,Force timestamp stimulus" "No effect,Force" group.long 0xe8c++0x3 line.long 0x00 "STMTSFREQR,Timestamp Frequency Register" group.long 0xe90++0x3 line.long 0x00 "STMSYNCR,Synchronization Control Register" bitfld.long 0x00 12. " MODE ,Mode control" "N,2^N" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Counter value for the number of bytes between synchronization packets" group.long 0xe94++0x3 line.long 0x00 "STMAUXCR,Auxiliary Control Register" bitfld.long 0x00 4. " AFREADYHIGH ,Override control for the AFREADY output" "No,Override" bitfld.long 0x00 3. " CLKON ,Override control for architectural clock gate enable" "No,Override" textline " " bitfld.long 0x00 2. " PRIORINVDIS ,Controls arbitration between AXI and HW during flush (priority inversion)" "Inverted,Not inverted" bitfld.long 0x00 1. " ASYNCPE ,ASYNC priority escalate" "No,Escalates" bitfld.long 0x00 0. " FIFOAF ,Auto-flush" "Disabled,Enabled" tree.end width 17. tree "Stimulus Port Control Registers" group.long 0xe00++0x3 line.long 0x00 "STMSPER,Stimulus Port Enable Register" bitfld.long 0x00 31. " SPE31 ,Stimulus port 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPE30 ,Stimulus port 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPE29 ,Stimulus port 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPE28 ,Stimulus port 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPE27 ,Stimulus port 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPE26 ,Stimulus port 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPE25 ,Stimulus port 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPE24 ,Stimulus port 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPE23 ,Stimulus port 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPE22 ,Stimulus port 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPE21 ,Stimulus port 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPE20 ,Stimulus port 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPE19 ,Stimulus port 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPE18 ,Stimulus port 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPE17 ,Stimulus port 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPE16 ,Stimulus port 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPE15 ,Stimulus port 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPE14 ,Stimulus port 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPE13 ,Stimulus port 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPE12 ,Stimulus port 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPE11 ,Stimulus port 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPE10 ,Stimulus port 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPE9 ,Stimulus port 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPE8 ,Stimulus port 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPE7 ,Stimulus port 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPE6 ,Stimulus port 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPE5 ,Stimulus port 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPE4 ,Stimulus port 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPE3 ,Stimulus port 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPE2 ,Stimulus port 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPE1 ,Stimulus port 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPE0 ,Stimulus port 0 enable" "Disabled,Enabled" group.long 0xe20++0x3 line.long 0x00 "STMSPTER,Stimulus Port Trigger Enable Register" bitfld.long 0x00 31. " SPTE31 ,Stimulus port 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " SPTE30 ,Stimulus port 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " SPTE29 ,Stimulus port 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " SPTE28 ,Stimulus port 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " SPTE27 ,Stimulus port 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " SPTE26 ,Stimulus port 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " SPTE25 ,Stimulus port 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " SPTE24 ,Stimulus port 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " SPTE23 ,Stimulus port 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " SPTE22 ,Stimulus port 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPTE21 ,Stimulus port 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " SPTE20 ,Stimulus port 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SPTE19 ,Stimulus port 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " SPTE18 ,Stimulus port 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " SPTE17 ,Stimulus port 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " SPTE16 ,Stimulus port 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SPTE15 ,Stimulus port 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " SPTE14 ,Stimulus port 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " SPTE13 ,Stimulus port 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPTE12 ,Stimulus port 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SPTE11 ,Stimulus port 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " SPTE10 ,Stimulus port 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " SPTE9 ,Stimulus port 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " SPTE8 ,Stimulus port 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SPTE7 ,Stimulus port 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " SPTE6 ,Stimulus port 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " SPTE5 ,Stimulus port 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " SPTE4 ,Stimulus port 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SPTE3 ,Stimulus port 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPTE2 ,Stimulus port 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " SPTE1 ,Stimulus port 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPTE0 ,Stimulus port 0 trigger enable" "Disabled,Enabled" width 17. group.long 0xe60++0xf textline " " line.long 0x00 "STMSPSCR,Stimulus Port Select Configuration Register" hexmask.long.word 0x00 20.--31. 1. " PORTSEL ,Port Selection" bitfld.long 0x00 0.--1. " PORTCTL ,Port selection control" "Disabled,STMSPTER,Reserved,STMSPER/STMSPTER" line.long 0x04 "STMSPMSCR,Stimulus Port Master Select Configuration Register" hexmask.long.tbyte 0x04 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x04 0. " MASTCTL ,Master selection control" "Disabled,Enabled" line.long 0x08 "STMSPOVERRIDER,Stimulus Port Override Register" hexmask.long.tbyte 0x08 15.--31. 1. " PORTSEL ,Port selection" bitfld.long 0x08 2. " OVERTS ,Timestamping override enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " OVERCTL ,Port selection transactions control" "Disabled,Guaranteed,Invariant timing,?..." line.long 0x0c "STMSPMOVERRIDER,Stimulus Port Master Override Register" hexmask.long.tbyte 0x0c 15.--31. 1. " MASTSEL ,Master Selection" bitfld.long 0x0c 0. " MASTCTL ,Master selection control" "Disabled,Enabled" group.long 0xe70++0x3 line.long 0x00 "STMSPTRIGCSR,Stimulus Port Trigger Control and Status Register" bitfld.long 0x00 4. " ATBTRIGEN_DIR ,ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port" "Disabled,Enabled" bitfld.long 0x00 3. " ATBTRIGEN_TE ,ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 1. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " TRIGCTL ,Trigger control" "Multi-shot,Single-shot" tree.end width 13. tree "Hardware Event Control Registers" group.long 0xd00++0x3 line.long 0x00 "STMHEER,Hardware Event Enable Register" bitfld.long 0x00 31. " HEE31 ,Hardware event 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " HEE30 ,Hardware event 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " HEE29 ,Hardware event 29 enable" "Disabled,Enabled" bitfld.long 0x00 28. " HEE28 ,Hardware event 28 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HEE27 ,Hardware event 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " HEE26 ,Hardware event 26 enable" "Disabled,Enabled" bitfld.long 0x00 25. " HEE25 ,Hardware event 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " HEE24 ,Hardware event 24 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HEE23 ,Hardware event 23 enable" "Disabled,Enabled" bitfld.long 0x00 22. " HEE22 ,Hardware event 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " HEE21 ,Hardware event 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " HEE20 ,Hardware event 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HEE19 ,Hardware event 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " HEE18 ,Hardware event 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " HEE17 ,Hardware event 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " HEE16 ,Hardware event 16 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HEE15 ,Hardware event 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HEE14 ,Hardware event 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " HEE13 ,Hardware event 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " HEE12 ,Hardware event 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HEE11 ,Hardware event 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HEE10 ,Hardware event 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HEE9 ,Hardware event 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " HEE8 ,Hardware event 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HEE7 ,Hardware event 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " HEE6 ,Hardware event 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " HEE5 ,Hardware event 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " HEE4 ,Hardware event 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HEE3 ,Hardware event 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " HEE2 ,Hardware event 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " HEE1 ,Hardware event 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " HEE0 ,Hardware event 0 enable" "Disabled,Enabled" group.long 0xd20++0x3 line.long 0x00 "STMHETER,Hardware Event Trigger Enable Register" bitfld.long 0x00 31. " HETE31 ,Hardware event 31 trigger enable" "Disabled,Enabled" bitfld.long 0x00 30. " HETE30 ,Hardware event 30 trigger enable" "Disabled,Enabled" bitfld.long 0x00 29. " HETE29 ,Hardware event 29 trigger enable" "Disabled,Enabled" bitfld.long 0x00 28. " HETE28 ,Hardware event 28 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETE27 ,Hardware event 27 trigger enable" "Disabled,Enabled" bitfld.long 0x00 26. " HETE26 ,Hardware event 26 trigger enable" "Disabled,Enabled" bitfld.long 0x00 25. " HETE25 ,Hardware event 25 trigger enable" "Disabled,Enabled" bitfld.long 0x00 24. " HETE24 ,Hardware event 24 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETE23 ,Hardware event 23 trigger enable" "Disabled,Enabled" bitfld.long 0x00 22. " HETE22 ,Hardware event 22 trigger enable" "Disabled,Enabled" bitfld.long 0x00 21. " HETE21 ,Hardware event 21 trigger enable" "Disabled,Enabled" bitfld.long 0x00 20. " HETE20 ,Hardware event 20 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETE19 ,Hardware event 19 trigger enable" "Disabled,Enabled" bitfld.long 0x00 18. " HETE18 ,Hardware event 18 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " HETE17 ,Hardware event 17 trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " HETE16 ,Hardware event 16 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETE15 ,Hardware event 15 trigger enable" "Disabled,Enabled" bitfld.long 0x00 14. " HETE14 ,Hardware event 14 trigger enable" "Disabled,Enabled" bitfld.long 0x00 13. " HETE13 ,Hardware event 13 trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " HETE12 ,Hardware event 12 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETE11 ,Hardware event 11 trigger enable" "Disabled,Enabled" bitfld.long 0x00 10. " HETE10 ,Hardware event 10 trigger enable" "Disabled,Enabled" bitfld.long 0x00 9. " HETE9 ,Hardware event 9 trigger enable" "Disabled,Enabled" bitfld.long 0x00 8. " HETE8 ,Hardware event 8 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETE7 ,Hardware event 7 trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " HETE6 ,Hardware event 6 trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " HETE5 ,Hardware event 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " HETE4 ,Hardware event 4 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETE3 ,Hardware event 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " HETE2 ,Hardware event 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " HETE1 ,Hardware event 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " HETE0 ,Hardware event 0 trigger enable" "Disabled,Enabled" group.long 0xd60++0x3 textline " " line.long 0x00 "STMHEBSR,Hardware Event Bank Select Register" group.long 0xd64++0x3 textline " " line.long 0x00 "STMHEMCR,Hardware Event Main Control Register" bitfld.long 0x00 7. " ATBTRIGEN ,ATB trigger enable on events being monitored using the STMHETER" "Disabled,Enabled" bitfld.long 0x00 6. " TRIGCLEAR ,Trigger status clear" "No effect,Clear" bitfld.long 0x00 5. " TRIGSTATUS ,Single trigger occurred" "Not occurred,Occurred" bitfld.long 0x00 4. " TRIGCTL ,Trigger Control" "Multi-shot,Single-shot" textline " " bitfld.long 0x00 2. " ERRDETECT ,Enable error detection on the hardware event tracing" "Disabled,Enabled" bitfld.long 0x00 1. " COMPEN ,Enable leading zero suppression of hardware event data values in the trace stream" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable Hardware Event Tracing" "Disabled,Enabled" group.long 0xd68++0x3 textline " " line.long 0x00 "STMHEEXTMUXR,Hardware Event External Multiplex Control Register" hexmask.long.byte 0x0 0.--7. 1. " EXTMUX ,Value for external multiplexing logic" rgroup.long 0xdf4++0xb textline " " line.long 0x00 "STMHEMASTR,Hardware Event Master Number Register" hexmask.long.word 0x00 0.--15. 1. " MASTER ,STPv2 master number for hardware event trace" line.long 0x04 "STMHEFEAT1R,Hardware Event Features 1 Register" hexmask.long.word 0x04 15.--23. 1. " NUMHE ,Number of hardware events supported by the STM" bitfld.long 0x04 4.--5. " HECOMP ,Data compression on hardware event tracing support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 3. " HEMASTR ,STMHEMASTR support" "Read-only,?..." bitfld.long 0x04 2. " HEERR ,Hardware event error detection support" "Reserved,Supported" textline " " bitfld.long 0x04 0. " HETER ,STMHETER support" "Reserved,Supported" line.long 0x08 "STMHEIDR,Hardware Event Features ID Register" hexmask.long.byte 0x08 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x08 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x08 0.--3. " CLASS ,Programmers model" "Reserved,Hardware Event,?..." tree.end width 14. tree "DMA Control Registers" wgroup.long 0xc04++0x7 line.long 0x00 "STMDMASTARTR,DMA Transfer Start Register" bitfld.long 0x00 0. " START ,Start a DMA transfer" "No effect,Start" line.long 0x04 "STMDMASTOPR,DMA Transfer Stop Register" bitfld.long 0x04 0. " STOP ,Stop a DMA transfer" "No effect,Stop" rgroup.long 0xc0c++0x3 line.long 0x00 "STMDMASTATR,DMA Transfer Status Register" bitfld.long 0x00 0. " STATUS ,Status of the DMA peripheral request interface" "Idle,Active" group.long 0xc10++0x3 line.long 0x00 "STMDMACTLR,DMA Control Register" bitfld.long 0x00 2.--3. " SENS ,Sensitivity of the DMA request to the current buffer level" "<25%,<50%,<75% full,<100% full" rgroup.long 0xcfc++0x3 line.long 0x00 "STMDMAIDR,DMA ID Register" hexmask.long.byte 0x00 8.--11. 1. " VENDSPEC ,Vendor specific modifications or mappings" hexmask.long.byte 0x00 4.--7. 1. " CLASSREV ,Revision of the programmers model" bitfld.long 0x00 0.--3. " CLASS ,Programmers model" "Reserved,Reserved,DMA,?..." tree.end width 13. tree "Identification Registers" rgroup.long 0xea0++0xb line.long 0x00 "STMSPFEAT1R,STM Features 1 Register" bitfld.long 0x00 22.--23. " SWOEN ,STMTCSR.SWOEN support" "Reserved,Not supported,?..." bitfld.long 0x00 20.--21. " SYNCEN ,STMTCSR.SYNCEN support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 18.--19. " HWTEN ,STMTCSR.HWTEN support" "Reserved,Not supported,?..." bitfld.long 0x00 16.--17. " TSPRESCALE ,Timestamp prescale support" "Reserved,Not supported,?..." textline " " bitfld.long 0x00 14.--15. " TRIGCTL ,Trigger control support (multi-shot/single-shot/STMTRIGCSR)" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 10.--13. " TRACEBUS ,Trace bus support (CoreSight ATB plus ATB trigger/STMTCSR.TRACEID/STMTRIGCSR.ATBTRIGEN)" "Reserved,Supported,?..." bitfld.long 0x00 8.--9. " SYNC ,STMSYNCR support (with MODE control) " "Reserved,Reserved,Reserved,Supported" bitfld.long 0x00 7. " FORCETS ,STMTSSTIMR support" "Reserved,Supported" textline " " bitfld.long 0x00 6. " TSFREQ ,Timestamp frequency indication configuration" "Reserved,Read-write" bitfld.long 0x00 4.--5. " TS ,Timestamp support" "Reserved,Absolute,?..." bitfld.long 0x00 0.--3. " PROT ,Protocol" "Reserved,STPv2,?..." line.long 0x04 "STMSPFEAT2R,STM Features 2 Register" bitfld.long 0x04 16.--17. " SPTYPE ,Stimulus port type support" "Reserved,Extended,?..." bitfld.long 0x04 12.--15. " DSIZE ,Fundamental data size" "32-bit,?..." bitfld.long 0x04 9.--10. " SPTRTYPE ,Stimulus port transaction type support (invariant timing/guaranteed transactions)" "Reserved,Reserved,Both,?..." bitfld.long 0x04 7.--8. " PRIVMASK ,STMPRIVMASKR support" "Reserved,Not supported,?..." textline " " bitfld.long 0x04 6. " SPOVERRIDE ,STMSPOVERRIDER\STMSPMOVERRIDER support" "Reserved,Supported" bitfld.long 0x04 4.--5. " SPCOMP ,Data compression on stimulus ports support" "Reserved,Reserved,Reserved,Programmable" bitfld.long 0x04 2. " SPER ,STMSPER presence" "Supported,?..." bitfld.long 0x04 0.--1. " SPTER ,STMSPTER support" "Reserved,Reserved,Supported,?..." line.long 0x08 "STMSPFEAT3R,STM Features 3 Register" hexmask.long.byte 0x08 0.--6. 1. " NUMMAST ,Number of stimulus ports masters implemented" tree.end width 15. tree "CoreSight Management Registers" wgroup.long 0xee8++0x7 line.long 0x00 "STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x00 3. " ASYNCOUT_W ,ASYNCOUT output value set (in integration mode)" "0,1" bitfld.long 0x00 2. " TRIGOUTHETE_W ,TRIGOUTHETE output value set (in integration mode)" "0,1" bitfld.long 0x00 1. " TRIGOUTSW_W ,TRIGOUTSW output value set (in integration mode)" "0,1" bitfld.long 0x00 0. " TRIGOUTSPTE_W ,TRIGOUTSPTE output value set (in integration mode)" "0,1" line.long 0x04 "STMITATBDATA0,Integration Mode ATB Data 0 Register" bitfld.long 0x04 4. " ATDATAM31_W ,ATDATAM[31] output value set" "0,1" bitfld.long 0x04 3. " ATDATAM23_W ,ATDATAM[23] output value set" "0,1" bitfld.long 0x04 2. " ATDATAM15_W ,ATDATAM[15] output value set" "0,1" bitfld.long 0x04 1. " ATDATAM7_W ,ATDATAM[7] output value set" "0,1" textline " " bitfld.long 0x04 0. " ATDATAM0_W ,ATDATAM[0] output value set" "0,1" rgroup.long 0xef0++0x3 line.long 0x00 "STMITATBCTR2,Integration Mode ATB Control 2 Register" bitfld.long 0x00 1. " AFVALIDM_R ,Value of the AFVALIDM input" "0,1" bitfld.long 0x00 0. " ATREADYM_R ,Value of the ATREADYM input" "0,1" wgroup.long 0xef4++0x7 line.long 0x00 "STMITATBID,Integration Mode ATB Identification Register" hexmask.long.byte 0x00 0.--6. 1. " ATIDM_W ,ATIDM output value set" line.long 0x04 "STMITATBCTR0,Integration Mode ATB Control 0 Register" bitfld.long 0x04 8.--9. " ATBYTESM_W ,ATBYTESM output value set" "00,01,10,11" bitfld.long 0x04 1. " AFREADYM_W ,AFREADYM output value set" "0,1" bitfld.long 0x04 0. " ATVALIDM_W ,ATVALIDM output value set" "0,1" width 15. group.long 0xf00++0x3 line.long 0x00 "STMITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "Disabled,Enabled" width 15. group.long 0xfa0++0x7 line.long 0x00 "STMCLAIMSET,Claim Tag Set Register" bitfld.long 0x00 3. " CLAIMSET3 ,Claim tag 3 set" "No effect,Set" bitfld.long 0x00 2. " CLAIMSET2 ,Claim tag 2 set" "No effect,Set" bitfld.long 0x00 1. " CLAIMSET1 ,Claim tag 1 set" "No effect,Set" bitfld.long 0x00 0. " CLAIMSET0 ,Claim tag 0 set" "No effect,Set" line.long 0x04 "STMCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x04 3. " CLAIMCLR3 ,Claim tag 3 clear" "No effect,Clear" bitfld.long 0x04 2. " CLAIMCLR2 ,Claim tag 2 clear" "No effect,Clear" bitfld.long 0x04 1. " CLAIMCLR1 ,Claim tag 1 clear" "No effect,Clear" bitfld.long 0x04 0. " CLAIMCLR0 ,Claim tag 0 clear" "No effect,Clear" wgroup.long 0xfb0++0x3 line.long 0x00 "STMLAR,Lock Access Register" rgroup.long 0xfb4++0x7 line.long 0x00 "STMLSR,Lock Status Register" bitfld.long 0x00 2. " TYPE ,32-bit Lock Access Register Implemented" "32-bit,8-bit" bitfld.long 0x00 1. " LOCKED ,Lock Status" "Unlocked,Locked" bitfld.long 0x00 0. " PRESENT ,Lock control mechanism present" "Not present,Present" line.long 0x04 "STMAUTHSTATUS,Authentication Status Register" bitfld.long 0x04 6.--7. " SNID ,Security level for secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 4.--5. " SID ,Security level for secure invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 2.--3. " NSNID ,Security level for non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x04 0.--1. " NSID ,Security level for non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long 0xfc8++0x7 line.long 0x00 "STMDEVID,Device Configuration Register" hexmask.long.tbyte 0x00 0.--16. 1. " NUMSP ,Number of stimulus ports implemented" line.long 0x04 "STMDEVTYPE,Device Type Identifier Register" bitfld.long 0x04 4.--7. " SUB_TYPE ,Sub-classification within the major category" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SW/HW stimulus,?..." bitfld.long 0x04 0.--3. " MAJOR_TYPE ,Major classification grouping for this debug or trace component" "Reserved,Reserved,Reserved,ATB output,?..." rgroup.long 0xfe0++0x13 "Peripheral Identification Registers" line.long 0x00 "STMPIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER[7:0] ,Bits [7:0] of the component part number" line.long 0x04 "STMPIDR1,Peripheral ID1 Register" bitfld.long 0x04 4.--7. " JEP106[3:0] ,Bits [3:0] of the JEDEC identity code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x04 0.--3. " PART_NUMBER[11:8] ,Bits [11:8] of the component part number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMPIDR2,Peripheral ID2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision" "Reserved,r0p1,?..." bitfld.long 0x08 3. " JEDEC ,JEDEC assigned value used" "Not used,Used" bitfld.long 0x08 0.--2. " JEP106[6:4] ,Bits [6:4] of the JEDEC identity code" "000,001,010,011,100,101,110,111" line.long 0x0c "STMPIDR3,Peripheral ID3 Register" hexmask.long.byte 0x0c 4.--7. 1. " REVAND ,Minor errata fixes" hexmask.long.byte 0x0c 0.--3. 1. " CUSTOMER_MODIFIED ,Customer Modified" rgroup.long 0xfd0++0x3 line.long 0x00 "STMPIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " FOURKB_COUNT ,Total contiguous size of the memory window" "4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB" bitfld.long 0x00 0.--3. " JEP106_CONT ,JEDEC continuation code" "Reserved,Reserved,Reserved,Reserved,5th bank,?..." rgroup.long 0xff0++0xf "Component Identification Registers" line.long 0x00 "STMCIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE[31:24] ,Bits [31:24] of the component identification" line.long 0x04 "STMCIDR1,Component ID1 Register" bitfld.long 0x04 4.--7. " CLASS ,Class of the component" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CoreSight,?..." bitfld.long 0x04 0.--3. " PREAMBLE[19:16] ,Bits [19:16] of the component identification" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.long 0x08 "STMCIDR2,Component ID2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE[15:8] ,Bits [15:8] of the component identification" line.long 0x0c "STMCIDR3,Component ID3 Register" hexmask.long.byte 0x0c 0.--7. 1. " PREAMBLE[7:0] ,Bits [7:0] of the component identification" tree.end tree.end endif textline " "