; --------------------------------------------------------------------------------
; @Title: MAX7800x On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2024-01-11 NEJ
; @Manufacturer: MAXIM - Maxim Integrated Products, Inc.
; @Doc: Generated (TRACE32, build: 165838.), based on:
;       max78000.svd (Ver. 1.0), max78002_fixed.svd (Ver. 1.0)
; @Core: Cortex-M4F
; @Chip: MAX78000, MAX78002
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permax7800x.per 17332 2024-01-15 16:15:30Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (10-bit Analog-to-Digital Converter)"
base ad:0x40034000
sif (cpuis("MAX78000"))
group.long 0x0++0x3
line.long 0x0 "CTRL,ADC Control"
bitfld.long 0x0 20. "data_align,ADC Data Alignment Select" "0,1"
bitfld.long 0x0 17.--18. "adc_divsel,Scales the external inputs  all inputs are scaled the same" "0,1,2,3"
newline
hexmask.long.byte 0x0 12.--16. 1. "ch_sel,ADC Channel Select"
bitfld.long 0x0 11. "clk_en,ADC Clock Enable" "0,1"
newline
bitfld.long 0x0 9. "scale,ADC Scale" "0,1"
bitfld.long 0x0 8. "ref_scale,ADC Reference Scale" "0,1"
newline
bitfld.long 0x0 4. "ref_sel,ADC Reference Select" "0,1"
bitfld.long 0x0 3. "refbuf_pwr,ADC Reference Buffer Power Up" "0,1"
newline
bitfld.long 0x0 1. "pwr,ADC Power Up" "0,1"
bitfld.long 0x0 0. "start,Start ADC Conversion" "0,1"
rgroup.long 0x4++0x7
line.long 0x0 "STATUS,ADC Status"
bitfld.long 0x0 3. "overflow,ADC Overflow" "0,1"
bitfld.long 0x0 2. "afe_pwr_up_active,AFE Power Up Delay Active" "0,1"
newline
bitfld.long 0x0 0. "active,ADC Conversion In Progress" "0,1"
line.long 0x4 "DATA,ADC Output Data"
hexmask.long.word 0x4 0.--15. 1. "adc_data,ADC Converted Sample Data Output"
group.long 0xC++0x3
line.long 0x0 "INTR,ADC Interrupt Control Register"
rbitfld.long 0x0 22. "pending,ADC Interrupt Pending Status" "0,1"
eventfld.long 0x0 20. "overflow_if,ADC Overflow Interrupt Flag" "0,1"
newline
eventfld.long 0x0 19. "lo_limit_if,ADC Lo Limit Monitor Interrupt Flag" "0,1"
eventfld.long 0x0 18. "hi_limit_if,ADC Hi Limit Monitor Interrupt Flag" "0,1"
newline
eventfld.long 0x0 17. "ref_ready_if,ADC Reference Ready Interrupt Flag" "0,1"
eventfld.long 0x0 16. "done_if,ADC Done Interrupt Flag" "0,1"
newline
bitfld.long 0x0 4. "overflow_ie,ADC Overflow Interrupt Enable" "0,1"
bitfld.long 0x0 3. "lo_limit_ie,ADC Lo Limit Monitor Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "hi_limit_ie,ADC Hi Limit Monitor Interrupt Enable" "0,1"
bitfld.long 0x0 1. "ref_ready_ie,ADC Reference Ready Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "done_ie,ADC Done Interrupt Enable" "0,1"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "LIMIT[$1],ADC Limit"
bitfld.long 0x0 30. "ch_hi_limit_en,High Limit Monitoring Enable" "0,1"
bitfld.long 0x0 29. "ch_lo_limit_en,Low Limit Monitoring Enable" "0,1"
newline
hexmask.long.byte 0x0 24.--28. 1. "ch_sel,ADC Channel Select"
hexmask.long.word 0x0 12.--21. 1. "ch_hi_limit,High Limit Threshold"
newline
hexmask.long.word 0x0 0.--9. 1. "ch_lo_limit,Low Limit Threshold"
repeat.end
endif
sif (cpuis("MAX78002"))
group.long 0x0++0x33
line.long 0x0 "CTRL0,Control Register 0."
bitfld.long 0x0 4. "RESETB,Reset ADC." "0: reset ADC.,1: activate ADC."
bitfld.long 0x0 3. "CHOP_FORCE,Chop Force Control." "0: Do not force chop mode.,1: Force chop Mode."
newline
bitfld.long 0x0 2. "SKIP_CAL,Skip Calibration Enable." "0: Do not skip calibration.,1: Skip calibration."
bitfld.long 0x0 1. "BIAS_EN,Bias Enable." "0: Disable Bias.,1: Enable Bias."
newline
bitfld.long 0x0 0. "ADC_EN,ADC Enable." "0: Disable ADC.,1: enable ADC."
line.long 0x4 "CTRL1,Control Register 1."
hexmask.long.byte 0x4 16.--20. 1. "NUM_SLOTS,Number of slots enabled for the conversion sequence"
bitfld.long 0x4 8.--10. "AVG,Number of samples to average for each output data code." "0: 1 Sample per output code.,1: 2 Samples per output code.,2: 4 Samples per output code.,3: 8 Samples per output code.,4: 16 Samples per output code.,5: 32 Samples per output code.,?,?"
newline
bitfld.long 0x4 7. "TS_SEL,Temp sensor select." "0: Temp sensor is not one of the slots in the..,1: Temp sensor is one of the slots in the sequence."
bitfld.long 0x4 4.--6. "TRIG_SEL,Hardware trigger source select." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 3. "SAMP_CK_OFF,Sample clock off control." "0: Sample clock always generated.,1: Sample clock generated only when converting."
bitfld.long 0x4 2. "CNV_MODE,Conversion mode control." "0: Do one conversion sequence.,1: Do continuous conversion sequences."
newline
bitfld.long 0x4 1. "TRIG_MODE,Trigger mode control." "0: software trigger mode.,1: hardware trigger mode."
bitfld.long 0x4 0. "START,Start conversion control." "0: Stop conversions.,1: Start conversions."
line.long 0x8 "CLKCTRL,Clock Control Register."
bitfld.long 0x8 4.--6. "CLKDIV,Clock divider control." "0: Divide by 2.,1: Divide by 4.,2: Divide by 8.,3: Divide by 16.,4: Divide by 1.,?,?,?"
bitfld.long 0x8 0.--1. "CLKSEL,Clock source select." "0: Select HCLK.,1: Select CLK_ADC0.,2: Select CLK_ADC1.,3: Select CLK_ADC2."
line.long 0xC "SAMPCLKCTRL,Sample Clock Control Register."
hexmask.long.word 0xC 16.--31. 1. "IDLE_CNT,Number of cycles for SAMPLE_CLK low time."
hexmask.long.byte 0xC 0.--7. 1. "TRACK_CNT,Number of cycles for SAMPLE_CLK high time."
line.long 0x10 "CHSEL0,Channel Select Register 0."
hexmask.long.byte 0x10 24.--28. 1. "slot3_id,channel assignment for slot 3."
hexmask.long.byte 0x10 16.--20. 1. "slot2_id,channel assignment for slot 2."
newline
hexmask.long.byte 0x10 8.--12. 1. "slot1_id,channel assignment for slot 1."
hexmask.long.byte 0x10 0.--4. 1. "slot0_id,channel assignment for slot 0."
line.long 0x14 "CHSEL1,Channel Select Register 1."
hexmask.long.byte 0x14 24.--28. 1. "slot7_id,channel assignment for slot 7."
hexmask.long.byte 0x14 16.--20. 1. "slot6_id,channel assignment for slot 6."
newline
hexmask.long.byte 0x14 8.--12. 1. "slot5_id,channel assignment for slot 5."
hexmask.long.byte 0x14 0.--4. 1. "slot4_id,channel assignment for slot 4."
line.long 0x18 "CHSEL2,Channel Select Register 2."
hexmask.long.byte 0x18 24.--28. 1. "slot11_id,channel assignment for slot 11."
hexmask.long.byte 0x18 16.--20. 1. "slot10_id,channel assignment for slot 10."
newline
hexmask.long.byte 0x18 8.--12. 1. "slot9_id,channel assignment for slot 9."
hexmask.long.byte 0x18 0.--4. 1. "slot8_id,channel assignment for slot 8."
line.long 0x1C "CHSEL3,Channel Select Register 3."
hexmask.long.byte 0x1C 24.--28. 1. "slot15_id,channel assignment for slot 15."
hexmask.long.byte 0x1C 16.--20. 1. "slot14_id,channel assignment for slot 14."
newline
hexmask.long.byte 0x1C 8.--12. 1. "slot13_id,channel assignment for slot 13."
hexmask.long.byte 0x1C 0.--4. 1. "slot12_id,channel assignment for slot 12."
line.long 0x20 "CHSEL4,Channel Select Register 4."
hexmask.long.byte 0x20 24.--28. 1. "slot19_id,channel assignment for slot 19."
hexmask.long.byte 0x20 16.--20. 1. "slot18_id,channel assignment for slot 18."
newline
hexmask.long.byte 0x20 8.--12. 1. "slot17_id,channel assignment for slot 17."
hexmask.long.byte 0x20 0.--4. 1. "slot16_id,channel assignment for slot 16."
line.long 0x24 "CHSEL5,Channel Select Register 5."
hexmask.long.byte 0x24 24.--28. 1. "slot23_id,channel assignment for slot 23."
hexmask.long.byte 0x24 16.--20. 1. "slot22_id,channel assignment for slot 22."
newline
hexmask.long.byte 0x24 8.--12. 1. "slot21_id,channel assignment for slot 21."
hexmask.long.byte 0x24 0.--4. 1. "slot20_id,channel assignment for slot 20."
line.long 0x28 "CHSEL6,Channel Select Register 6."
hexmask.long.byte 0x28 24.--28. 1. "slot27_id,channel assignment for slot 27."
hexmask.long.byte 0x28 16.--20. 1. "slot26_id,channel assignment for slot 26."
newline
hexmask.long.byte 0x28 8.--12. 1. "slot25_id,channel assignment for slot 25."
hexmask.long.byte 0x28 0.--4. 1. "slot24_id,channel assignment for slot 24."
line.long 0x2C "CHSEL7,Channel Select Register 7."
hexmask.long.byte 0x2C 24.--28. 1. "slot31_id,channel assignment for slot 31."
hexmask.long.byte 0x2C 16.--20. 1. "slot30_id,channel assignment for slot 30."
newline
hexmask.long.byte 0x2C 8.--12. 1. "slot29_id,channel assignment for slot 29."
hexmask.long.byte 0x2C 0.--4. 1. "slot28_id,channel assignment for slot 28."
line.long 0x30 "RESTART,Restart Count Control Register"
hexmask.long.word 0x30 0.--15. 1. "CNT,Number of sample periods to skip before restarting a continuous mode sequence"
group.long 0x3C++0x7
line.long 0x0 "DATAFMT,Channel Data Format Register"
hexmask.long 0x0 0.--31. 1. "MODE,Data format control"
line.long 0x4 "FIFODMACTRL,FIFO and DMA control"
hexmask.long.byte 0x4 8.--15. 1. "THRESH,FIFO Threshold. These bits define the FIFO interrupt threshold."
bitfld.long 0x4 2.--3. "DATA_FORMAT,DATA format control." "0: Data and Status in FIFO.,1: Only Data in FIFO.,2: Only Raw Data in FIFO.,?"
newline
bitfld.long 0x4 1. "FLUSH,FIFO Flush." "0: Normal FIFO operation.,1: Flush FIFO."
bitfld.long 0x4 0. "DMA_EN,DMA Enable." "0: Disable DMA.,1: Enable DMA."
rgroup.long 0x44++0x7
line.long 0x0 "DATA,Data Register (FIFO)."
bitfld.long 0x0 31. "CLIPPED,Clipped status for the data." "0,1"
bitfld.long 0x0 24. "INVALID,Invalid status for the data." "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "CHAN,Channel for the data."
hexmask.long.word 0x0 0.--15. 1. "DATA,Conversion data."
line.long 0x4 "STATUS,Status Register"
hexmask.long.byte 0x4 8.--15. 1. "FIFO_LEVEL,Number of entries in FIFO available to read"
bitfld.long 0x4 2. "FULL,FIFO full" "0,1"
newline
bitfld.long 0x4 1. "EMPTY,FIFO Empty" "0,1"
bitfld.long 0x4 0. "READY,Indication that the ADC is in ON power state" "0,1"
group.long 0x4C++0xB
line.long 0x0 "CHSTATUS,Channel Status"
hexmask.long 0x0 0.--31. 1. "CLIPPED,"
line.long 0x4 "INTEN,Interrupt Enable Register."
bitfld.long 0x4 10. "FIFO_OFL," "0,1"
bitfld.long 0x4 9. "FIFO_UFL," "0,1"
newline
bitfld.long 0x4 8. "FIFO_LVL," "0,1"
bitfld.long 0x4 7. "CLIPPED," "0,1"
newline
bitfld.long 0x4 6. "CONV_DONE," "0,1"
bitfld.long 0x4 5. "SEQ_DONE," "0,1"
newline
bitfld.long 0x4 4. "SEQ_STARTED," "0,1"
bitfld.long 0x4 3. "START_DET,Conversion start is detected." "0,1"
newline
bitfld.long 0x4 2. "ABORT,Conversion start is aborted." "0,1"
bitfld.long 0x4 0. "READY,ADC is ready." "0,1"
line.long 0x8 "INTFL,Interrupt Flags Register."
eventfld.long 0x8 10. "FIFO_OFL," "0,1"
eventfld.long 0x8 9. "FIFO_UFL," "0,1"
newline
eventfld.long 0x8 8. "FIFO_LVL," "0,1"
eventfld.long 0x8 7. "CLIPPED," "0,1"
newline
eventfld.long 0x8 6. "CONV_DONE," "0,1"
eventfld.long 0x8 5. "SEQ_DONE," "0,1"
newline
eventfld.long 0x8 4. "SEQ_STARTED," "0,1"
eventfld.long 0x8 3. "START_DET,Conversion start is detected." "0,1"
newline
eventfld.long 0x8 2. "ABORT,Conversion start is aborted." "0,1"
eventfld.long 0x8 0. "READY,ADC is ready." "0,1"
group.long 0x60++0xB
line.long 0x0 "SFRADDROFFSET,SFR Address Offset Register"
hexmask.long.byte 0x0 0.--7. 1. "OFFSET,Address Offset for SAR Digital"
line.long 0x4 "SFRADDR,SFR Address Register"
hexmask.long.byte 0x4 0.--7. 1. "ADDR,Address to SAR Digital"
line.long 0x8 "SFRWRDATA,SFR Write Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,DATA to SAR Digital"
rgroup.long 0x6C++0x7
line.long 0x0 "SFRRDDATA,SFR Read Data Register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA from SAR Digital"
line.long 0x4 "SFRSTATUS,SFR Status Register"
bitfld.long 0x4 0. "NACK,NACK status for SAR Digital SFR communication" "0,1"
endif
tree.end
tree "AES (Advanced Encryption Standard)"
base ad:0x40007400
group.long 0x0++0x13
line.long 0x0 "CTRL,AES Control Register"
bitfld.long 0x0 8.--9. "TYPE,Encryption Type Selection" "0,1,2,3"
bitfld.long 0x0 6.--7. "KEY_SIZE,Encryption Key Size" "0: 128 Bits.,1: 192 Bits.,2: 256 Bits.,?"
bitfld.long 0x0 5. "OUTPUT_FLUSH,Flush the data output FIFO" "0,1"
bitfld.long 0x0 4. "INPUT_FLUSH,Flush the data input FIFO" "0,1"
bitfld.long 0x0 3. "START,Start AES Calculation" "0,1"
bitfld.long 0x0 2. "DMA_TX_EN,DMA Request To Write Data Input FIFO" "0,1"
bitfld.long 0x0 1. "DMA_RX_EN,DMA Request To Read Data Output FIFO" "0,1"
bitfld.long 0x0 0. "EN,AES Enable" "0,1"
line.long 0x4 "STATUS,AES Status Register"
bitfld.long 0x4 4. "OUTPUT_FULL,Data output FIFO full status" "0,1"
bitfld.long 0x4 3. "OUTPUT_EM,Data output FIFO empty status" "0,1"
bitfld.long 0x4 2. "INPUT_FULL,Data input FIFO full status" "0,1"
bitfld.long 0x4 1. "INPUT_EM,Data input FIFO empty status" "0,1"
bitfld.long 0x4 0. "BUSY,AES Busy Status" "0,1"
line.long 0x8 "INTFL,AES Interrupt Flag Register"
bitfld.long 0x8 4. "KEY_ONE,KEY_ONE" "0,1"
bitfld.long 0x8 3. "OV,Data Output FIFO Overrun Interrupt" "0,1"
bitfld.long 0x8 2. "KEY_ZERO,External AES Key Zero Interrupt" "0,1"
bitfld.long 0x8 1. "KEY_CHANGE,External AES Key Changed Interrupt" "0,1"
bitfld.long 0x8 0. "DONE,AES Done Interrupt" "0,1"
line.long 0xC "INTEN,AES Interrupt Enable Register"
bitfld.long 0xC 4. "KEY_ONE,KEY_ONE" "0,1"
bitfld.long 0xC 3. "OV,Data Output FIFO Overrun Interrupt Enable" "0,1"
bitfld.long 0xC 2. "KEY_ZERO,External AES Key Zero Interrupt Enable" "0,1"
bitfld.long 0xC 1. "KEY_CHANGE,External AES Key Changed Interrupt Enable" "0,1"
bitfld.long 0xC 0. "DONE,AES Done Interrupt Enable" "0,1"
line.long 0x10 "FIFO,AES Data Register"
bitfld.long 0x10 0. "DATA,AES FIFO" "0,1"
tree.end
tree "AES_KEYS (Advanced Encryption Standard Keys)"
base ad:0x40007800
group.long 0x0++0x3
line.long 0x0 "KEY0,AES Key 0."
sif (cpuis("MAX78000"))
group.long 0x4++0x1B
line.long 0x0 "KEY1,AES Key 1."
line.long 0x4 "KEY2,AES Key 2."
line.long 0x8 "KEY3,AES Key 3."
line.long 0xC "KEY4,AES Key 4."
line.long 0x10 "KEY5,AES Key 5."
line.long 0x14 "KEY6,AES Key 6."
line.long 0x18 "KEY7,AES Key 7."
endif
sif (cpuis("MAX78002"))
group.long 0x80++0x3
line.long 0x0 "KEY1,AES Key 1."
group.long 0x100++0x3
line.long 0x0 "KEY2,AES Key 2."
group.long 0x180++0x3
line.long 0x0 "KEY3,AES Key 3."
endif
tree.end
tree "CAMERAIF (Camera Interface)"
base ad:0x4000E000
group.long 0x0++0x17
line.long 0x0 "VER,Hardware Version."
hexmask.long.byte 0x0 8.--15. 1. "major,Major Version Number."
hexmask.long.byte 0x0 0.--7. 1. "minor,Minor Version Number."
line.long 0x4 "FIFO_SIZE,FIFO Depth."
hexmask.long.byte 0x4 0.--7. 1. "fifo_size,FIFO size."
line.long 0x8 "CTRL,Control Register."
bitfld.long 0x8 31. "PCIF_SYS,PCIF Control." "0: PCIF disabled.,1: PCIF enabled."
bitfld.long 0x8 30. "THREE_CH_EN,Three-channel mode enable." "0,1"
newline
hexmask.long.byte 0x8 17.--20. 1. "RX_DMA_THRSH,DMA Threshold."
bitfld.long 0x8 16. "RX_DMA,DMA Enable." "0: DMA disabled.,1: DMA enabled."
newline
hexmask.long.byte 0x8 5.--9. 1. "FIFO_THRSH,Data FIFO Threshold."
bitfld.long 0x8 4. "DS_TIMING_EN,DS Timing Enable." "0: Timing from VSYNC and HSYNC.,1: Timing embedded in data using SAV and EAV codes."
newline
bitfld.long 0x8 2.--3. "DATA_WIDTH,Data Width." "0: 8 bit.,1: 10 bit.,2: 12 bit.,?"
bitfld.long 0x8 0.--1. "READ_MODE,Read Mode." "0: Camera Interface Disabled.,1: Single Image Capture.,2: Continuous Image Capture.,?"
line.long 0xC "INT_EN,Interupt Enable Register."
bitfld.long 0xC 3. "FIFO_NOT_EMPTY,FIFO Not Empty." "0,1"
bitfld.long 0xC 2. "FIFO_THRESH,FIFO Threshold Level Met." "0,1"
newline
bitfld.long 0xC 1. "FIFO_FULL,FIFO Full." "0,1"
bitfld.long 0xC 0. "IMG_DONE,Image Done." "0,1"
line.long 0x10 "INT_FL,Interupt Flag Register."
bitfld.long 0x10 3. "FIFO_NOT_EMPTY,FIFO Not Empty." "0,1"
bitfld.long 0x10 2. "FIFO_THRESH,FIFO Threshold Level Met." "0,1"
newline
bitfld.long 0x10 1. "FIFO_FULL,FIFO Full." "0,1"
bitfld.long 0x10 0. "IMG_DONE,Image Done." "0,1"
line.long 0x14 "DS_TIMING_CODES,DS Timing Code Register."
hexmask.long.byte 0x14 8.--15. 1. "EAV,End Active Video Code."
hexmask.long.byte 0x14 0.--7. 1. "SAV,Start Active Video Code."
group.long 0x30++0x3
line.long 0x0 "FIFO_DATA,FIFO DATA Register."
hexmask.long 0x0 0.--31. 1. "DATA,Data from FIFO to be read by DMA."
tree.end
tree "CRC (Cyclic Redundancy Check)"
base ad:0x4000F000
group.long 0x0++0x7
line.long 0x0 "CTRL,CRC Control"
bitfld.long 0x0 16. "BUSY,CRC Busy" "0,1"
bitfld.long 0x0 4. "BYTE_SWAP_OUT,Byte Swap CRC Value Output" "0,1"
bitfld.long 0x0 3. "BYTE_SWAP_IN,Byte Swap CRC Data Input" "0,1"
bitfld.long 0x0 2. "MSB,MSB Select" "0,1"
bitfld.long 0x0 1. "DMA_EN,DMA Request Enable" "0,1"
bitfld.long 0x0 0. "EN,CRC Enable" "0,1"
line.long 0x4 "DATAIN32,CRC Data Input"
hexmask.long 0x4 0.--31. 1. "DATA,CRC Data"
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
group.word ($2+0x4)++0x1
line.word 0x0 "DATAIN16[$1],CRC Data Input"
hexmask.word 0x0 0.--15. 1. "DATA,CRC Data"
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2+0x4)++0x0
line.byte 0x0 "DATAIN8[$1],CRC Data Input"
hexmask.byte 0x0 0.--7. 1. "DATA,CRC Data"
repeat.end
group.long 0x8++0x7
line.long 0x0 "POLY,CRC Polynomial"
hexmask.long 0x0 0.--31. 1. "POLY,CRC Polynomial"
line.long 0x4 "VAL,Current CRC Value"
hexmask.long 0x4 0.--31. 1. "VALUE,Current CRC Value"
tree.end
sif (cpuis("MAX78002"))
tree "CSI2 (Camera Serial Interface)"
base ad:0x40062000
group.long 0x0++0x5F
line.long 0x0 "CFG_NUM_LANES,CFG_NUM_LANES."
hexmask.long.byte 0x0 0.--3. 1. "LANES,Num Lanes for RX controller."
line.long 0x4 "CFG_CLK_LANE_EN,CFG_CLK_LANE_EN."
bitfld.long 0x4 0. "EN,Enable lane clock setting for controller." "0,1"
line.long 0x8 "CFG_DATA_LANE_EN,CFG_DATA_LANE_EN."
hexmask.long.byte 0x8 0.--7. 1. "EN,Enable data lane setting for controller."
line.long 0xC "CFG_FLUSH_COUNT,CFG_FLUSH_COUNT."
hexmask.long.byte 0xC 0.--3. 1. "COUNT,Flush count setting for controller."
line.long 0x10 "CFG_BIT_ERR,CFG_BIT_ERR."
bitfld.long 0x10 9. "VID_ERR_FIFO_WR_OV,Video Error Fifo Overflow." "0,1"
bitfld.long 0x10 8. "VID_ERR_SEND_LVL,Video Error Send Level." "0,1"
bitfld.long 0x10 7. "CRC,CRC error." "0,1"
newline
hexmask.long.byte 0x10 2.--6. 1. "HEADER,Header bit location of single bit ECC error."
bitfld.long 0x10 1. "SBE,Single bit ECC error." "0,1"
bitfld.long 0x10 0. "MBE,Multiple bit ECC error." "0,1"
line.long 0x14 "IRQ_STATUS,IRQ_STATUS."
bitfld.long 0x14 6. "VID_ERR_FIFO_WR_OV,Video Error Fifo Overflow." "0,1"
bitfld.long 0x14 5. "VID_ERR_SEND_LVL,Video Error Send Level." "0,1"
bitfld.long 0x14 4. "ULPS_MARK_ACTIVE,ULPS mark active status change." "0,1"
newline
bitfld.long 0x14 3. "ULPS_ACTIVE,ULPS active status change." "0,1"
bitfld.long 0x14 2. "MBE,Multiple bit ECC error." "0,1"
bitfld.long 0x14 1. "SBE,Single bit ECC error." "0,1"
newline
bitfld.long 0x14 0. "CRC,CRC error." "0,1"
line.long 0x18 "IRQ_ENABLE,IRQ_ENABLE."
bitfld.long 0x18 6. "VID_ERR_FIFO_WR_OV,Video Error Fifo Overflow." "0,1"
bitfld.long 0x18 5. "VID_ERR_SEND_LVL,Video Error Send Level." "0,1"
bitfld.long 0x18 4. "ULPS_MARK_ACTIVE,ULPS mark active status change." "0,1"
newline
bitfld.long 0x18 3. "ULPS_ACTIVE,ULPS active status change." "0,1"
bitfld.long 0x18 2. "MBE,Multiple bit ECC error." "0,1"
bitfld.long 0x18 1. "SBE,Single bit ECC error." "0,1"
newline
bitfld.long 0x18 0. "CRC,CRC error." "0,1"
line.long 0x1C "IRQ_CLR,IRQ_CLR."
bitfld.long 0x1C 6. "VID_ERR_FIFO_WR_OV,Video Error Fifo Overflow." "0,1"
bitfld.long 0x1C 5. "VID_ERR_SEND_LVL,Video Error Send Level." "0,1"
bitfld.long 0x1C 4. "ULPS_MARK_ACTIVE,ULPS mark active status change." "0,1"
newline
bitfld.long 0x1C 3. "ULPS_ACTIVE,ULPS active status change." "0,1"
bitfld.long 0x1C 2. "MBE,Multiple bit ECC error." "0,1"
bitfld.long 0x1C 1. "SBE,Single bit ECC error." "0,1"
newline
bitfld.long 0x1C 0. "CRC,CRC error." "0,1"
line.long 0x20 "ULPS_CLK_STATUS,ULPS_CLK_STATUS."
bitfld.long 0x20 0. "FIFO,FIFO Read/Write register." "0,1"
line.long 0x24 "ULPS_STATUS,ULPS_STATUS."
bitfld.long 0x24 1. "DATA_LANE1,Data Lane 1." "0,1"
bitfld.long 0x24 0. "DATA_LANE0,Data Lane 0." "0,1"
line.long 0x28 "ULPS_CLK_MARK_STATUS,ULPS_CLK_MARK_STATUS."
bitfld.long 0x28 0. "CLK_LANE,Clock Lane." "0,1"
line.long 0x2C "ULPS_MARK_STATUS,ULPS_MARK_STATUS."
bitfld.long 0x2C 1. "DATA_LANE1,Data Lane 1." "0,1"
bitfld.long 0x2C 0. "DATA_LANE0,Data Lane 0." "0,1"
line.long 0x30 "PPI_ERRSOT_HS,PPI_ERRSOT_HS."
line.long 0x34 "PPI_ERRSOTSYNC_HS,PPI_ERRSOTSYNC_HS."
line.long 0x38 "PPI_ERRESC,PPI_ERRESC."
line.long 0x3C "PPI_ERRSYNCESC,PPI_ERRSYNCESC."
line.long 0x40 "PPI_ERRCONTROL,PPI_ERRCONTROL."
line.long 0x44 "CFG_CPHY_EN,CFG_CPHY_EN."
line.long 0x48 "CFG_PPI_16_EN,CFG_PPI_16_EN."
line.long 0x4C "CFG_PACKET_INTERFACE_EN,CFG_PACKET_INTERFACE_EN."
line.long 0x50 "CFG_VCX_EN,CFG_VCX_EN."
line.long 0x54 "CFG_BYTE_DATA_FORMAT,CFG_BYTE_DATA_FORMAT."
line.long 0x58 "CFG_DISABLE_PAYLOAD_0,CFG_DISABLE_PAYLOAD_0."
bitfld.long 0x58 31. "RAW20,RAW20." "0,1"
bitfld.long 0x58 30. "RAW16,RAW16." "0,1"
bitfld.long 0x58 29. "RAW14,RAW14." "0,1"
newline
bitfld.long 0x58 28. "RAW12,RAW12." "0,1"
bitfld.long 0x58 27. "RAW10,RAW10." "0,1"
bitfld.long 0x58 26. "RAW8,RAW8." "0,1"
newline
bitfld.long 0x58 25. "RAW7,RAW7." "0,1"
bitfld.long 0x58 24. "RAW6,RAW6." "0,1"
bitfld.long 0x58 20. "RGB888,RGB888." "0,1"
newline
bitfld.long 0x58 19. "RGB666,RGB666." "0,1"
bitfld.long 0x58 18. "RGB565,RGB565." "0,1"
bitfld.long 0x58 17. "RGB555,RGB555." "0,1"
newline
bitfld.long 0x58 16. "RGB444,RGB444." "0,1"
bitfld.long 0x58 15. "YUV422_10BIT,YUV422_10BIT." "0,1"
bitfld.long 0x58 14. "YUV422_8BIT,YUV422_8BIT." "0,1"
newline
bitfld.long 0x58 13. "YUV420_10BIT_CSP,YUV420_10BIT_CSP." "0,1"
bitfld.long 0x58 12. "YUV420_8BIT_CSP,YUV420_8BIT_CSP." "0,1"
bitfld.long 0x58 10. "YUV420_8BIT_LEG,YUV420_8BIT_LEG." "0,1"
newline
bitfld.long 0x58 9. "YUV420_10BIT,YUV420_10BIT." "0,1"
bitfld.long 0x58 8. "YUV420_8BIT,YUV420_8BIT." "0,1"
bitfld.long 0x58 2. "EMBEDDED,EMBEDDED." "0,1"
newline
bitfld.long 0x58 1. "BLANK,BLANK." "0,1"
bitfld.long 0x58 0. "NULL,NULL." "0,1"
line.long 0x5C "CFG_DISABLE_PAYLOAD_1,CFG_DISABLE_PAYLOAD_1."
bitfld.long 0x5C 7. "USR_DEF_TYPE37,User defined type 0x37." "0,1"
bitfld.long 0x5C 6. "USR_DEF_TYPE36,User defined type 0x36." "0,1"
bitfld.long 0x5C 5. "USR_DEF_TYPE35,User defined type 0x35." "0,1"
newline
bitfld.long 0x5C 4. "USR_DEF_TYPE34,User defined type 0x34." "0,1"
bitfld.long 0x5C 3. "USR_DEF_TYPE33,User defined type 0x33." "0,1"
bitfld.long 0x5C 2. "USR_DEF_TYPE32,User defined type 0x32." "0,1"
newline
bitfld.long 0x5C 1. "USR_DEF_TYPE31,User defined type 0x31." "0,1"
bitfld.long 0x5C 0. "USR_DEF_TYPE30,User defined type 0x30." "0,1"
group.long 0x80++0x1B
line.long 0x0 "CFG_VID_IGNORE_VC,CFG_VID_IGNORE_VC."
line.long 0x4 "CFG_VID_VC,CFG_VID_VC."
line.long 0x8 "CFG_P_FIFO_SEND_LEVEL,CFG_P_FIFO_SEND_LEVEL."
line.long 0xC "CFG_VID_VSYNC,CFG_VID_VSYNC."
line.long 0x10 "CFG_VID_HSYNC_FP,CFG_VID_HSYNC_FP."
line.long 0x14 "CFG_VID_HSYNC,CFG_VID_HSYNC."
line.long 0x18 "CFG_VID_HSYNC_BP,CFG_VID_HSYNC_BP."
group.long 0x400++0x8B
line.long 0x0 "CFG_DATABUS16_SEL,CFG_DATABUS16_SEL."
bitfld.long 0x0 0. "EN,Enable 16-bit data bus." "0,1"
line.long 0x4 "CFG_D0_SWAP_SEL,CFG_D0_SWAP_SEL."
bitfld.long 0x4 0.--2. "SRC,Control Source." "0: PAD_CDRX_L0.,1: PAD_CDRX_L1.,2: PAD_CDRX_L2.,3: PAD_CDRX_L3.,4: PAD_CDRX_L4.,?,?,?"
line.long 0x8 "CFG_D1_SWAP_SEL,CFG_D1_SWAP_SEL."
bitfld.long 0x8 0.--2. "SRC,Control Source." "0: PAD_CDRX_L0.,1: PAD_CDRX_L1.,2: PAD_CDRX_L2.,3: PAD_CDRX_L3.,4: PAD_CDRX_L4.,?,?,?"
line.long 0xC "CFG_D2_SWAP_SEL,CFG_D2_SWAP_SEL."
bitfld.long 0xC 0.--2. "SRC,Control Source." "0: PAD_CDRX_L0.,1: PAD_CDRX_L1.,2: PAD_CDRX_L2.,3: PAD_CDRX_L3.,4: PAD_CDRX_L4.,?,?,?"
line.long 0x10 "CFG_D3_SWAP_SEL,CFG_D3_SWAP_SEL."
bitfld.long 0x10 0.--2. "SRC,Control Source." "0: PAD_CDRX_L0.,1: PAD_CDRX_L1.,2: PAD_CDRX_L2.,3: PAD_CDRX_L3.,4: PAD_CDRX_L4.,?,?,?"
line.long 0x14 "CFG_C0_SWAP_SEL,CFG_C0_SWAP_SEL."
bitfld.long 0x14 0.--2. "SRC,Control Source." "0: PAD_CDRX_L0.,1: PAD_CDRX_L1.,2: PAD_CDRX_L2.,3: PAD_CDRX_L3.,4: PAD_CDRX_L4.,?,?,?"
line.long 0x18 "CFG_DPDN_SWAP,CFG_DPDN_SWAP."
bitfld.long 0x18 4. "SWAP_CLK_LANE,SWAP_CLK_LANE." "0,1"
bitfld.long 0x18 3. "SWAP_DATA_LANE3,SWAP_DATA_LANE3." "0,1"
bitfld.long 0x18 2. "SWAP_DATA_LANE2,SWAP_DATA_LANE2." "0,1"
newline
bitfld.long 0x18 1. "SWAP_DATA_LANE1,SWAP_DATA_LANE1." "0,1"
bitfld.long 0x18 0. "SWAP_DATA_LANE0,SWAP_DATA_LANE0." "0,1"
line.long 0x1C "RG_CFGCLK_1US_CNT,RG_CFGCLK_1US_CNT."
line.long 0x20 "RG_HSRX_CLK_PRE_TIME_GRP0,RG_HSRX_CLK_PRE_TIME_GRP0."
line.long 0x24 "RG_HSRX_DATA_PRE_TIME_GRP0,RG_HSRX_DATA_PRE_TIME_GRP0."
line.long 0x28 "RESET_DESKEW,RESET_DESKEW."
bitfld.long 0x28 3. "DATA_LANE3,DATA_LANE3." "0,1"
bitfld.long 0x28 2. "DATA_LANE2,DATA_LANE2." "0,1"
bitfld.long 0x28 1. "DATA_LANE1,DATA_LANE1." "0,1"
newline
bitfld.long 0x28 0. "DATA_LANE0,DATA_LANE0." "0,1"
line.long 0x2C "PMA_RDY,PMA_RDY."
line.long 0x30 "XCFGI_DW00,XCFGI_DW00."
line.long 0x34 "XCFGI_DW01,XCFGI_DW01."
line.long 0x38 "XCFGI_DW02,XCFGI_DW02."
line.long 0x3C "XCFGI_DW03,XCFGI_DW03."
line.long 0x40 "XCFGI_DW04,XCFGI_DW04."
line.long 0x44 "XCFGI_DW05,XCFGI_DW05."
line.long 0x48 "XCFGI_DW06,XCFGI_DW06."
line.long 0x4C "XCFGI_DW07,XCFGI_DW07."
line.long 0x50 "XCFGI_DW08,XCFGI_DW08."
line.long 0x54 "XCFGI_DW09,XCFGI_DW09."
line.long 0x58 "XCFGI_DW0A,XCFGI_DW0A."
line.long 0x5C "XCFGI_DW0B,XCFGI_DW0B."
line.long 0x60 "XCFGI_DW0C,XCFGI_DW0C."
line.long 0x64 "XCFGI_DW0D,XCFGI_DW0D."
line.long 0x68 "GPIO_MODE,GPIO_MODE."
line.long 0x6C "GPIO_DP_IE,GPIO_DP_IE."
line.long 0x70 "GPIO_DN_IE,GPIO_DN_IE."
line.long 0x74 "GPIO_DP_C,GPIO_DP_C."
line.long 0x78 "GPIO_DN_C,GPIO_DN_C."
line.long 0x7C "VCONTROL,PMA_RDY."
bitfld.long 0x7C 31. "SUSPEND_MODE,SUSPEND_MODE." "0,1"
bitfld.long 0x7C 28. "HS_RX_PRBS9,HS_RX_PRBS9." "0,1"
bitfld.long 0x7C 27. "HS_RX_PARTBERT,HS_RX_PARTBERT." "0,1"
newline
bitfld.long 0x7C 11. "HS_INT_LOOPBACK,HS_INT_LOOPBACK." "0,1"
bitfld.long 0x7C 10. "LP_RX_PARTBERT,LP_RX_PARTBERT." "0,1"
bitfld.long 0x7C 8. "HSRT_1,HSRT_1." "0,1"
newline
bitfld.long 0x7C 7. "HSRT_0,HSRT_0." "0,1"
bitfld.long 0x7C 5. "CAL_SEN_0,CAL_SEN_0." "0,1"
bitfld.long 0x7C 4. "CAL_SEN_1,CAL_SEN_1." "0,1"
newline
bitfld.long 0x7C 3. "LP_RX_DC_0,LP_RX_DC_0." "0,1"
bitfld.long 0x7C 2. "LP_RX_DC_1,LP_RX_DC_1." "0,1"
bitfld.long 0x7C 1. "LP_RX_DC_TEST,LP_RX_DC_TEST." "0,1"
newline
bitfld.long 0x7C 0. "NORMAL_MODE,NORMAL_MODE." "0,1"
line.long 0x80 "MPSOV1,MPSOV1."
line.long 0x84 "MPSOV2,MPSOV2."
line.long 0x88 "MPSOV3,MPSOV3."
group.long 0x490++0x33
line.long 0x0 "RG_CDRX_DSIRX_EN,RG_CDRX_DSIRX_EN."
bitfld.long 0x0 0. "RXMODE,RXMODE." "0: CSI RX Mode.,1: DSI RX Mode."
line.long 0x4 "RG_CDRX_L012_SUBLVDS_EN,RG_CDRX_L012_SUBLVDS_EN."
line.long 0x8 "RG_CDRX_L012_HSRT_CTRL,RG_CDRX_L012_HSRT_CTRL."
line.long 0xC "RG_CDRX_BISTHS_PLL_EN,RG_CDRX_BISTHS_PLL_EN."
line.long 0x10 "RG_CDRX_BISTHS_PLL_PRE_DIV2,RG_CDRX_BISTHS_PLL_PRE_DIV2."
bitfld.long 0x10 0. "RXMODE,RXMODE." "0: CSI RX Mode.,1: DSI RX Mode."
line.long 0x14 "RG_CDRX_BISTHS_PLL_FBK_INT,RG_CDRX_BISTHS_PLL_FBK_INT."
line.long 0x18 "DBG1_MUX_SEL,DBG1_MUX_SEL."
line.long 0x1C "DBG2_MUX_SEL,DBG2_MUX_SEL."
line.long 0x20 "DBG1_MUX_DOUT,DBG1_MUX_DOUT."
line.long 0x24 "DBG2_MUX_DOUT,DBG2_MUX_DOUT."
line.long 0x28 "AON_POWER_READY_N,AON_POWER_READY_N."
line.long 0x2C "DPHY_RST_N,DPHY_RST_N."
line.long 0x30 "RXBYTECLKHS_INV,RXBYTECLKHS_INV."
group.long 0x500++0x47
line.long 0x0 "VFIFO_CFG0,Video FIFO Configuration Register 0."
bitfld.long 0x0 11. "FBWM,Full Band Width mode." "0,1"
bitfld.long 0x0 10. "ERRDE,Error Detection Enable." "0,1"
bitfld.long 0x0 9. "FIFORM,FIFO Read Mode." "0,1"
newline
bitfld.long 0x0 8. "AHBWAIT,AHB Wait Enable." "0,1"
bitfld.long 0x0 6.--7. "DMAMODE,DMA Mode  the condition to trigger DMA request.." "0: No DMA.,1: Immediately send DMA request.,2: Wait for FIFO above threshold.,3: Wait for FIFO is full."
bitfld.long 0x0 0.--1. "VC,CSI Virtual Channel." "0,1,2,3"
line.long 0x4 "VFIFO_CFG1,Video FIFO Configuration Register 1."
bitfld.long 0x4 21. "ACCU_PIXEL_ZERO,ACCU_PIXEL_ZERO." "0,1"
bitfld.long 0x4 20. "ACCU_PIXEL_CNT,ACCU_PIXEL_CNT." "0,1"
bitfld.long 0x4 19. "ACCU_LINE_CNT,ACCU_LINE_CNT." "0,1"
newline
bitfld.long 0x4 18. "ACCU_LINE_CTRL,ACCU_LINE_CTRL." "0,1"
bitfld.long 0x4 17. "ACCU_FRAME_CTRL,ACCU_FRAME_CTRL." "0,1"
bitfld.long 0x4 16. "WAIT_FIRST_FS,WAIT_FIRST_FS." "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "AHBWCYC,Maximal AHB Wait Clock Cycles."
line.long 0x8 "VFIFO_CTRL,Video FIFO Control Register."
hexmask.long.byte 0x8 8.--14. 1. "THD,FIFO Threshold."
bitfld.long 0x8 4. "FLUSH,Write 1 to flush FIFO contents." "0,1"
bitfld.long 0x8 0. "FIFOEN,Video FIFO Enable." "0: Disable.,1: Enable."
line.long 0xC "VFIFO_STS,Video FIFO Status Register."
hexmask.long.byte 0xC 24.--29. 1. "FMT,CSI pixel format of current transaction"
hexmask.long.byte 0xC 16.--22. 1. "FELT,FIFO remaining entity count"
bitfld.long 0xC 11. "LE,CSI Line End" "0,1"
newline
bitfld.long 0xC 10. "LS,CSI Line Start" "0,1"
bitfld.long 0xC 9. "FE,CSI Frame End" "0,1"
bitfld.long 0xC 8. "FS,CSI Frame Start" "0,1"
newline
bitfld.long 0xC 7. "AHBWTO,AHB wait time out" "0,1"
bitfld.long 0xC 6. "FMTERR,CSI Pixel Format Error" "0,1"
bitfld.long 0xC 5. "OUTSYNC,CSI out of sync" "0,1"
newline
bitfld.long 0xC 4. "OVERRUN,FIFO overrun" "0,1"
bitfld.long 0xC 3. "UNDERRUN,FIFO underrun" "0,1"
bitfld.long 0xC 2. "FFULL,FIFO full." "0,1"
newline
bitfld.long 0xC 1. "FTHD,FIFO above threshold." "0,1"
bitfld.long 0xC 0. "FEMPTY,FIFO empty." "0,1"
line.long 0x10 "VFIFO_LINE_NUM,Video FIFO CSI Line Number Per Frame."
hexmask.long.word 0x10 0.--12. 1. "LINE_NUM,Number of lines per frame."
line.long 0x14 "VFIFO_PIXEL_NUM,Video FIFO CSI Pixel Number Per Line."
hexmask.long.word 0x14 0.--13. 1. "PIXEL_NUM,Number of pixels per line."
line.long 0x18 "VFIFO_LINE_CNT,Video FIFO CSI Line Count."
hexmask.long.word 0x18 0.--11. 1. "LINE_CNT,Number of received lines in current frame."
line.long 0x1C "VFIFO_PIXEL_CNT,Video FIFO CSI Pixel Count."
hexmask.long.word 0x1C 0.--12. 1. "PIXEL_CNT,Number of received pixels in current line in a frame."
line.long 0x20 "VFIFO_FRAME_STS,Video FIFO Frame Status Register."
bitfld.long 0x20 3.--5. "ERROR_CODE,Error Codes." "0,1,2,3,4,5,6,7"
bitfld.long 0x20 0.--2. "FRAME_STATE,Frame State." "0,1,2,3,4,5,6,7"
line.long 0x24 "VFIFO_RAW_CTRL,Video FIFO RAW-to-RGB Control Register."
bitfld.long 0x24 12.--14. "RGB_TYP,RGB type." "0: RGB444.,1: RGB555.,2: RGB565.,3: RGB666.,4: RGG888.,?,?,?"
bitfld.long 0x24 8.--9. "RAW_FMT,RAW format." "0: RGRG GBGB,1: GRGR BGBG,2: GBGB RGRG,3: BGBG GRGR"
bitfld.long 0x24 4. "RAW_FF_FO,RAW conversion FIFO flush-out trigger." "0,1"
newline
bitfld.long 0x24 1. "RAW_FF_AFO,RAW conversion FIFO automatic flush-out." "0,1"
bitfld.long 0x24 0. "RAW_CEN,RAW conversion enable." "0,1"
line.long 0x28 "VFIFO_RAW_BUF0_ADDR,Video FIFO RAW-to-RGB Line Buffer0 Address."
hexmask.long 0x28 2.--31. 1. "ADDR,RAM address for RAW conversion buffer 0  word-aligned."
line.long 0x2C "VFIFO_RAW_BUF1_ADDR,Video FIFO RAW-to-RGB Line Buffer1 Address."
hexmask.long 0x2C 2.--31. 1. "ADDR,RAM address for RAW conversion buffer 1  word-aligned."
line.long 0x30 "VFIFO_AHBM_CTRL,Video FIFO AHB Master Control Register."
bitfld.long 0x30 4.--5. "BSTLEN,AHB Burst Length." "0: Video FIFO THD.,1: ONE_WORD.,2: FOUR_WORDS.,3: EIGHT_WORDS."
bitfld.long 0x30 1. "AHBMCLR,AHB Master Status Clear." "0,1"
bitfld.long 0x30 0. "AHBMEN,AHB Master Enable." "0,1"
line.long 0x34 "VFIFO_AHBM_STS,Video FIFO AHB Master Status Register."
bitfld.long 0x34 2. "TRANS_MAX,AHB master maximal transfer count occurrence." "0,1"
bitfld.long 0x34 1. "IDLE_TO,AHB master Idle time-out." "0,1"
bitfld.long 0x34 0. "HRDY_TO,AHB master HREADY time-out." "0,1"
line.long 0x38 "VFIFO_AHBM_START_ADDR,Video FIFO AHB Master Start Address Register."
hexmask.long 0x38 2.--31. 1. "AHBM_START_ADDR,AHB master transfer starting address  word-aligned."
line.long 0x3C "VFIFO_AHBM_ADDR_RANGE,Video FIFO AHB Master Address Range Register."
hexmask.long.word 0x3C 2.--15. 1. "AHBM_ADDR_RANGE,AHB master address range."
line.long 0x40 "VFIFO_AHBM_MAX_TRANS,Video FIFO AHB Master Maximal Transfer Number Register."
hexmask.long 0x40 0.--31. 1. "AHBM_MAX_TRANS,AHB master maximal number of transfer word count."
line.long 0x44 "VFIFO_AHBM_TRANS_CNT,Video FIFO AHB Master Transfer Count Register."
hexmask.long 0x44 0.--31. 1. "AHBM_TRANS_CNT,AHB master number of words been transferred."
group.long 0x600++0x17
line.long 0x0 "RX_EINT_VFF_IE,RX Video FIFO Interrupt Enable Register."
bitfld.long 0x0 26. "AHBM_MAX,AHBM_MAX" "0,1"
bitfld.long 0x0 25. "AHBM_IDTO,AHBM_IDTO" "0,1"
bitfld.long 0x0 24. "AHBM_RDTO,AHBM_RDTO" "0,1"
newline
bitfld.long 0x0 18. "FFUL_MD,Video FIFO full detection mode" "0,1"
bitfld.long 0x0 17. "FTHD_MD,Video FIFO threshold detection mode" "0,1"
bitfld.long 0x0 16. "FNEMP_MD,Video FIFO not empty detection mode" "0,1"
newline
bitfld.long 0x0 13. "RAW_AHBERR,Raw AHB Error Interrupt Enable" "0,1"
bitfld.long 0x0 12. "RAW_OVR,Raw FIFO Overrun Interrupt Enable" "0,1"
bitfld.long 0x0 11. "LE,CSI Line End interrupt enable" "0,1"
newline
bitfld.long 0x0 10. "LS,CSI Line Start interrupt enable" "0,1"
bitfld.long 0x0 9. "FE,CSI Frame End interrupt enable" "0,1"
bitfld.long 0x0 8. "FS,CSI Frame Start interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "AHBWTO,AHB wait time out interrupt enable" "0,1"
bitfld.long 0x0 6. "FMTERR,CSI Pixel Format Error interrupt enable" "0,1"
bitfld.long 0x0 5. "OUTSYNC,CSI out of sync interrupt enable" "0,1"
newline
bitfld.long 0x0 4. "OVERRUN,Video FIFO overrun interrupt enable" "0,1"
bitfld.long 0x0 3. "UNDERRUN,Video FIFO underrun interrupt enable" "0,1"
bitfld.long 0x0 2. "FFULL,Video FIFO full interrupt enable." "0,1"
newline
bitfld.long 0x0 1. "FTHD,Video FIFO above threshold interrupt enable." "0,1"
bitfld.long 0x0 0. "FNEMPTY,Video FIFO not empty interrupt enable." "0,1"
line.long 0x4 "RX_EINT_VFF_IF,RX Video FIFO Interrupt Flag Register."
bitfld.long 0x4 26. "AHBM_MAX,AHBM_MAX" "0,1"
bitfld.long 0x4 25. "AHBM_IDTO,AHBM_IDTO" "0,1"
bitfld.long 0x4 24. "AHBM_RDTO,AHBM_RDTO" "0,1"
newline
bitfld.long 0x4 13. "RAW_AHBERR,Raw AHB Error Interrupt Enable" "0,1"
bitfld.long 0x4 12. "RAW_OVR,Raw FIFO Overrun Interrupt Enable" "0,1"
bitfld.long 0x4 11. "LE,CSI Line End interrupt flag" "0,1"
newline
bitfld.long 0x4 10. "LS,CSI Line Start interrupt flag" "0,1"
bitfld.long 0x4 9. "FE,CSI Frame End interrupt flag" "0,1"
bitfld.long 0x4 8. "FS,CSI Frame Start interrupt flag" "0,1"
newline
bitfld.long 0x4 7. "AHBWTO,AHB wait time out interrupt flag" "0,1"
bitfld.long 0x4 6. "FMTERR,CSI Pixel Format Error interrupt flag" "0,1"
bitfld.long 0x4 5. "OUTSYNC,CSI out of sync interrupt flag" "0,1"
newline
bitfld.long 0x4 4. "OVERRUN,Video FIFO overrun interrupt flag" "0,1"
bitfld.long 0x4 3. "UNDERRUN,Video FIFO underrun interrupt flag" "0,1"
bitfld.long 0x4 2. "FFULL,Video FIFO full interrupt flag." "0,1"
newline
bitfld.long 0x4 1. "FTHD,Video FIFO above threshold interrupt flag." "0,1"
bitfld.long 0x4 0. "FNEMPTY,Video FIFO not empty interrupt flag." "0,1"
line.long 0x8 "RX_EINT_PPI_IE,RX D-PHY Interrupt Enable Register."
bitfld.long 0x8 25. "DL1ECTL,DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt enable" "0,1"
bitfld.long 0x8 24. "DL0ECTL,DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt enable" "0,1"
bitfld.long 0x8 21. "DL1ESESC,DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable" "0,1"
newline
bitfld.long 0x8 20. "DL0ESESC,DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable" "0,1"
bitfld.long 0x8 17. "DL1EESC,DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt enable" "0,1"
bitfld.long 0x8 16. "DL0EESC,DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt enable" "0,1"
newline
bitfld.long 0x8 13. "DL1ESOTS,DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt enable" "0,1"
bitfld.long 0x8 12. "DL0ESOTS,DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt enable" "0,1"
bitfld.long 0x8 9. "DL1ESOT,DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt enable" "0,1"
newline
bitfld.long 0x8 8. "DL0ESOT,DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt enable" "0,1"
bitfld.long 0x8 7. "DL0ECONT1,DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt enable" "0,1"
bitfld.long 0x8 6. "DL0ECONT0,DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt enable" "0,1"
newline
bitfld.long 0x8 4. "CL0STOP,DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt enable." "0,1"
bitfld.long 0x8 1. "DL1STOP,DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt enable." "0,1"
bitfld.long 0x8 0. "DL0STOP,DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt enable." "0,1"
line.long 0xC "RX_EINT_PPI_IF,RX D-PHY Interrupt Flag Register."
bitfld.long 0xC 25. "DL1ECTL,DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt flag" "0,1"
bitfld.long 0xC 24. "DL0ECTL,DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt flag" "0,1"
bitfld.long 0xC 21. "DL1ESESC,DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag" "0,1"
newline
bitfld.long 0xC 20. "DL0ESESC,DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag" "0,1"
bitfld.long 0xC 17. "DL1EESC,DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt flag" "0,1"
bitfld.long 0xC 16. "DL0EESC,DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt flag" "0,1"
newline
bitfld.long 0xC 13. "DL1ESOTS,DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt flag" "0,1"
bitfld.long 0xC 12. "DL0ESOTS,DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt flag" "0,1"
bitfld.long 0xC 9. "DL1ESOT,DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt flag" "0,1"
newline
bitfld.long 0xC 8. "DL0ESOT,DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt flag" "0,1"
bitfld.long 0xC 7. "DL0ECONT1,DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt flag" "0,1"
bitfld.long 0xC 6. "DL0ECONT0,DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt flag" "0,1"
newline
bitfld.long 0xC 4. "CL0STOP,DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt flag." "0,1"
bitfld.long 0xC 1. "DL1STOP,DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt flag." "0,1"
bitfld.long 0xC 0. "DL0STOP,DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt flag." "0,1"
line.long 0x10 "RX_EINT_CTRL_IE,RX Controller Interrupt Enable Register."
bitfld.long 0x10 17. "CL0ULPSM,CSI Data Lane0 ULPSS Mark interrupt enable" "0,1"
bitfld.long 0x10 16. "CL0ULPSA,CSI Clock Lane0 ULPSS Active interrupt enable" "0,1"
bitfld.long 0x10 13. "DL1ULPSM,CSI Data Lane1 ULPSS Mark interrupt enable" "0,1"
newline
bitfld.long 0x10 12. "DL0ULPSM,CSI Data Lane0 ULPSS Mark interrupt enable" "0,1"
bitfld.long 0x10 9. "DL1ULPSA,CSI Data Lane1 ULPSS Active interrupt enable" "0,1"
bitfld.long 0x10 8. "DL0ULPSA,CSI Data Lane0 ULPSS Active interrupt enable" "0,1"
newline
bitfld.long 0x10 4. "PKTFFOV,CSI RX Packet FIFO Overrun interrupt enable" "0,1"
bitfld.long 0x10 3. "EID,CSI RX Packet Header Data ID Error interrupt enable" "0,1"
bitfld.long 0x10 2. "ECRC,CSI RX CRC Error interrupt enable." "0,1"
newline
bitfld.long 0x10 1. "EECC1,CSI RX ECC 1-bit Error interrupt enable." "0,1"
bitfld.long 0x10 0. "EECC2,CSI RX ECC 2-bit Error interrupt enable." "0,1"
line.long 0x14 "RX_EINT_CTRL_IF,RX Controller Interrupt Flag Register."
bitfld.long 0x14 17. "CL0ULPSM,CSI Data Lane0 ULPSS Mark interrupt flag" "0,1"
bitfld.long 0x14 16. "CL0ULPSA,CSI Clock Lane0 ULPSS Active interrupt flag" "0,1"
bitfld.long 0x14 13. "DL1ULPSM,CSI Data Lane1 ULPSS Mark interrupt flag" "0,1"
newline
bitfld.long 0x14 12. "DL0ULPSM,CSI Data Lane0 ULPSS Mark interrupt flag" "0,1"
bitfld.long 0x14 9. "DL1ULPSA,CSI Data Lane1 ULPSS Active interrupt flag" "0,1"
bitfld.long 0x14 8. "DL0ULPSA,CSI Data Lane0 ULPSS Active interrupt flag" "0,1"
newline
bitfld.long 0x14 4. "PKTFFOV,CSI RX Packet FIFO Overrun interrupt flag" "0,1"
bitfld.long 0x14 3. "EID,CSI RX Packet Header Data ID Error interrupt flag" "0,1"
bitfld.long 0x14 2. "ECRC,CSI RX CRC Error interrupt flag." "0,1"
newline
bitfld.long 0x14 1. "EECC1,CSI RX ECC 1-bit Error interrupt flag." "0,1"
bitfld.long 0x14 0. "EECC2,CSI RX ECC 2-bit Error interrupt flag." "0,1"
group.long 0x700++0x7
line.long 0x0 "PPI_STOPSTATE,DPHY PPI Stop State Register."
bitfld.long 0x0 2. "CL0STOP,CSI Clock Lane0 Stop State." "0,1"
bitfld.long 0x0 1. "DL1STOP,CSI Data Lane1 Stop State." "0,1"
bitfld.long 0x0 0. "DL0STOP,CSI Data Lane0 Stop State." "0,1"
line.long 0x4 "PPI_TURNAROUND_CFG,DPHY PPI Turn-Around Configuration Register."
bitfld.long 0x4 2. "DL0FRCRX,CSI Data Lane0 force RX mode." "0,1"
bitfld.long 0x4 1. "DL0TADIS,CSI Data Lane0 turn around disable." "0,1"
bitfld.long 0x4 0. "DL0TAREQ,CSI Data Lane0 turn around request." "0,1"
tree.end
endif
tree "DMA (Direct Memory Access Controller)"
base ad:0x40028000
group.long 0x0++0x3
line.long 0x0 "INTEN,DMA Control Register."
sif (cpuis("MAX78002"))
bitfld.long 0x0 7. "CH7,Channel 7 Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 6. "CH6,Channel 6 Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 5. "CH5,Channel 5 Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 4. "CH4,Channel 4 Interrupt Enable." "0: Disable.,1: Enable."
newline
endif
bitfld.long 0x0 3. "CH3,Channel 3 Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 2. "CH2,Channel 2 Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 1. "CH1,Channel 1 Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 0. "CH0,Channel 0 Interrupt Enable." "0: Disable.,1: Enable."
rgroup.long 0x4++0x3
line.long 0x0 "INTFL,DMA Interrupt Register."
sif (cpuis("MAX78002"))
bitfld.long 0x0 7. "CH7,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 6. "CH6,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 5. "CH5,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 4. "CH4,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
newline
endif
bitfld.long 0x0 3. "CH3,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 2. "CH2,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 1. "CH1,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 0. "CH0,Channel Interrupt. To clear an interrupt  all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
sif (cpuis("MAX78000"))
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40028100 ad:0x40028120 ad:0x40028140 ad:0x40028160)
tree "CH[$1]"
base $2
group.long ($2)++0x1F
line.long 0x0 "CTRL,DMA Channel Control Register."
bitfld.long 0x0 31. "CTZ_IE,Count-to-zero Interrupts Enable. When enabled  the IPEND will be set to 1 whenever a count-to-zero event occurs." "0: Disable.,1: Enable."
bitfld.long 0x0 30. "DIS_IE,Channel Disable Interrupt Enable. When enabled  the IPEND will be set to 1 whenever CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
hexmask.long.byte 0x0 24.--28. 1. "BURST_SIZE,Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."
newline
bitfld.long 0x0 22. "DSTINC,Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals." "0: Disable.,1: Enable."
bitfld.long 0x0 20.--21. "DSTWD,Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)." "0: Byte.,1: Halfword.,2: Word.,?"
bitfld.long 0x0 18. "SRCINC,Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 16.--17. "SRCWD,Source Width. In most cases  this will be the data width of each AHB transactions. However  the width will be reduced in the cases where DMA_CNT indicates a smaller value." "0: Byte.,1: Halfword.,2: Word.,?"
bitfld.long 0x0 14.--15. "TO_CLKDIV,Pre-Scale Select. Selects the Pre-Scale divider for timer clock input." "0: Disable timer.,1: hclk / 256.,2: hclk / 64k.,3: hclk / 16M."
bitfld.long 0x0 11.--13. "TO_PER,Timeout Period Select." "0: Timeout of 3 to 4 prescale clocks.,1: Timeout of 7 to 8 prescale clocks.,2: Timeout of 15 to 16 prescale clocks.,3: Timeout of 31 to 32 prescale clocks.,4: Timeout of 63 to 64 prescale clocks.,5: Timeout of 127 to 128 prescale clocks.,6: Timeout of 255 to 256 prescale clocks.,7: Timeout of 511 to 512 prescale clocks."
newline
bitfld.long 0x0 10. "TO_WAIT,Request Wait Enable. When enabled  delay timer start until DMA request transitions from active to inactive." "0: Disable.,1: Enable."
hexmask.long.byte 0x0 4.--9. 1. "REQUEST,Request Select. Select DMA request line for this channel. If memory-to-memory is selected  the channel operates as if the request is always active."
bitfld.long 0x0 2.--3. "PRI,DMA Priority." "0: Highest Priority.,1: Medium High Priority.,2: Medium Low Priority.,3: Lowest Priority."
newline
bitfld.long 0x0 1. "RLDEN,Reload Enable. Setting this bit to 1 enables DMA_SRC  DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer.." "0: Disable.,1: Enable."
bitfld.long 0x0 0. "EN,Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
line.long 0x4 "STATUS,DMA Channel Status Register."
eventfld.long 0x4 6. "TO_IF,Time-Out Event Interrupt Flag." "0,1"
eventfld.long 0x4 4. "BUS_ERR,Bus Error. Indicates that an AHB abort was received and the channel has been disabled." "0,1"
eventfld.long 0x4 3. "RLD_IF,Reload Event Interrupt Flag." "0,1"
newline
eventfld.long 0x4 2. "CTZ_IF,Count-to-Zero (CTZ) Interrupt Flag" "0,1"
rbitfld.long 0x4 1. "IPEND,Channel Interrupt." "0: No interrupt is pending.,1: An interrupt is pending."
rbitfld.long 0x4 0. "STATUS,Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration  address  and count registers for the channel. Whenever this bit is cleared by hardware  the DMA_CFG.CHEN bit is also cleared (if not.." "0: Disable.,1: Enable."
line.long 0x8 "SRC,Source Device Address. If SRCINC=1. the counter bits are incremented by 1.2. or 4. depending on the data width of each AHB cycle. For peripheral transfers. some or all of the actual address bits are fixed. If SRCINC=0. this register remains constant."
hexmask.long 0x8 0.--31. 1. "ADDR,"
line.long 0xC "DST,Destination Device Address. For peripheral transfers. some or all of the actual address bits are fixed. If DSTINC=1. this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1. 2. or 4. depending on the data width.."
hexmask.long 0xC 0.--31. 1. "ADDR,"
line.long 0x10 "CNT,DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1. 2. or 4 depending on the data width of each AHB cycle. When the counter reaches 0. a.."
hexmask.long.tbyte 0x10 0.--23. 1. "CNT,DMA Counter."
line.long 0x14 "SRCRLD,Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition."
hexmask.long 0x14 0.--30. 1. "ADDR,Source Address Reload Value."
line.long 0x18 "DSTRLD,Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition."
hexmask.long 0x18 0.--30. 1. "ADDR,Destination Address Reload Value."
line.long 0x1C "CNTRLD,DMA Channel Count Reload Register."
bitfld.long 0x1C 31. "EN,Count Reload Enable." "0,1"
hexmask.long.tbyte 0x1C 0.--23. 1. "CNT,Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition."
tree.end
repeat.end
endif
sif (cpuis("MAX78002"))
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40028100 ad:0x40028120 ad:0x40028140 ad:0x40028160 ad:0x40028180 ad:0x400281A0 ad:0x400281C0 ad:0x400281E0)
tree "CH[$1]"
base $2
group.long ($2)++0x1F
line.long 0x0 "CTRL,DMA Channel Control Register."
bitfld.long 0x0 31. "CTZ_IE,Count-to-zero Interrupts Enable. When enabled  the IPEND will be set to 1 whenever a count-to-zero event occurs." "0: Disable.,1: Enable."
bitfld.long 0x0 30. "DIS_IE,Channel Disable Interrupt Enable. When enabled  the IPEND will be set to 1 whenever CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
hexmask.long.byte 0x0 24.--28. 1. "BURST_SIZE,Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."
newline
bitfld.long 0x0 22. "DSTINC,Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals." "0: Disable.,1: Enable."
bitfld.long 0x0 20.--21. "DSTWD,Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)." "0: Byte.,1: Halfword.,2: Word.,?"
bitfld.long 0x0 18. "SRCINC,Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 16.--17. "SRCWD,Source Width. In most cases  this will be the data width of each AHB transactions. However  the width will be reduced in the cases where DMA_CNT indicates a smaller value." "0: Byte.,1: Halfword.,2: Word.,?"
bitfld.long 0x0 14.--15. "TO_CLKDIV,Pre-Scale Select. Selects the Pre-Scale divider for timer clock input." "0: Disable timer.,1: hclk / 256.,2: hclk / 64k.,3: hclk / 16M."
bitfld.long 0x0 11.--13. "TO_PER,Timeout Period Select." "0: Timeout of 3 to 4 prescale clocks.,1: Timeout of 7 to 8 prescale clocks.,2: Timeout of 15 to 16 prescale clocks.,3: Timeout of 31 to 32 prescale clocks.,4: Timeout of 63 to 64 prescale clocks.,5: Timeout of 127 to 128 prescale clocks.,6: Timeout of 255 to 256 prescale clocks.,7: Timeout of 511 to 512 prescale clocks."
newline
bitfld.long 0x0 10. "TO_WAIT,Request Wait Enable. When enabled  delay timer start until DMA request transitions from active to inactive." "0: Disable.,1: Enable."
hexmask.long.byte 0x0 4.--9. 1. "REQUEST,Request Select. Select DMA request line for this channel. If memory-to-memory is selected  the channel operates as if the request is always active."
bitfld.long 0x0 2.--3. "PRI,DMA Priority." "0: Highest Priority.,1: Medium High Priority.,2: Medium Low Priority.,3: Lowest Priority."
newline
bitfld.long 0x0 1. "RLDEN,Reload Enable. Setting this bit to 1 enables DMA_SRC  DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer.." "0: Disable.,1: Enable."
bitfld.long 0x0 0. "EN,Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
line.long 0x4 "STATUS,DMA Channel Status Register."
eventfld.long 0x4 6. "TO_IF,Time-Out Event Interrupt Flag." "0,1"
eventfld.long 0x4 4. "BUS_ERR,Bus Error. Indicates that an AHB abort was received and the channel has been disabled." "0,1"
eventfld.long 0x4 3. "RLD_IF,Reload Event Interrupt Flag." "0,1"
newline
eventfld.long 0x4 2. "CTZ_IF,Count-to-Zero (CTZ) Interrupt Flag" "0,1"
rbitfld.long 0x4 1. "IPEND,Channel Interrupt." "0: No interrupt is pending.,1: An interrupt is pending."
rbitfld.long 0x4 0. "STATUS,Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration  address  and count registers for the channel. Whenever this bit is cleared by hardware  the DMA_CFG.CHEN bit is also cleared (if not.." "0: Disable.,1: Enable."
line.long 0x8 "SRC,Source Device Address. If SRCINC=1. the counter bits are incremented by 1.2. or 4. depending on the data width of each AHB cycle. For peripheral transfers. some or all of the actual address bits are fixed. If SRCINC=0. this register remains constant."
hexmask.long 0x8 0.--31. 1. "ADDR,"
line.long 0xC "DST,Destination Device Address. For peripheral transfers. some or all of the actual address bits are fixed. If DSTINC=1. this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1. 2. or 4. depending on the data width.."
hexmask.long 0xC 0.--31. 1. "ADDR,"
line.long 0x10 "CNT,DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1. 2. or 4 depending on the data width of each AHB cycle. When the counter reaches 0. a.."
hexmask.long.tbyte 0x10 0.--23. 1. "CNT,DMA Counter."
line.long 0x14 "SRCRLD,Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition."
hexmask.long 0x14 0.--30. 1. "ADDR,Source Address Reload Value."
line.long 0x18 "DSTRLD,Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition."
hexmask.long 0x18 0.--30. 1. "ADDR,Destination Address Reload Value."
line.long 0x1C "CNTRLD,DMA Channel Count Reload Register."
bitfld.long 0x1C 31. "EN,Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs." "0: Disable.,1: Enable."
hexmask.long.tbyte 0x1C 0.--23. 1. "CNT,Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition."
tree.end
repeat.end
endif
tree.end
tree "DVS (Dynamic Voltage Scaling)"
base ad:0x40003C00
group.long 0x0++0x1B
line.long 0x0 "CTL,Control Register"
bitfld.long 0x0 25. "ADJ_ABORT,Causes the DVS to enter the idle state immediately on a request to enter a low power mode" "0,1"
bitfld.long 0x0 24. "PD_ACK_ENA,Prevent DVS from ack'ing a request to enter a low power mode until in the idle state" "0,1"
bitfld.long 0x0 23. "FC_LV_IE,Enable Low Voltage Interrupt" "0,1"
bitfld.long 0x0 22. "FB_TO_IE,Enable Voltage Adjustment Timeout Interrupt" "0,1"
bitfld.long 0x0 21. "DVS_HI_RANGE_ANY,Any high range signal from a delay line will cause a voltage adjustment" "0,1"
bitfld.long 0x0 20. "DVS_PS_APB_DIS,Prevent the application code from adjusting Vcore" "0,1"
newline
bitfld.long 0x0 17.--19. "INC_VAL,Step size to increment voltage when in automatic mode" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 13.--16. 1. "REF_SEL,Select TAP used for voltage adjustment"
bitfld.long 0x0 12. "ADJ_IE,Enable Adjustment Error Interrupt" "0,1"
bitfld.long 0x0 11. "RANGE_IE,Enable Range Error Interrupt" "0,1"
bitfld.long 0x0 10. "LIMIT_IE,Enable Limit Error Interrupt" "0,1"
bitfld.long 0x0 9. "PRIME_ENA,Include a delay line priming signal before monitoring" "0,1"
newline
bitfld.long 0x0 8. "DIRECT_REG,Step incrementally to target voltage" "0,1"
bitfld.long 0x0 7. "GO_DIRECT,Operate in automatic mode or move directly" "0,1"
bitfld.long 0x0 6. "MON_ONESHOT,Measure delay once" "0,1"
bitfld.long 0x0 4.--5. "PROP_DLY,Additional delay to monitor lines" "0,1,2,3"
bitfld.long 0x0 3. "CTRL_TAP_ENA,Use the TAP Select for automatic adjustment or monitoring" "0,1"
bitfld.long 0x0 2. "PS_FB_DIS,Power Supply Feedback Disable" "0,1"
newline
bitfld.long 0x0 1. "ADJ_ENA,Enable the power supply adjustment based on measurements" "0,1"
bitfld.long 0x0 0. "MON_ENA,Enable the DVS monitoring circuit" "0,1"
line.long 0x4 "STAT,Status Fields"
bitfld.long 0x4 31. "FC_LV_DET_S,Interrupt flag that mirrors FC_LV_DET_INT" "0,1"
bitfld.long 0x4 30. "FC_LV_DET_INT,Interrupt flag that indicates the power supply voltage requested is below the low threshold" "0,1"
bitfld.long 0x4 29. "FB_TO_ERR_S,Interrupt flag that mirror FB_TO_ERR and is write one clear" "0,1"
bitfld.long 0x4 28. "FB_TO_ERR,Interrupt flag that indicates a timeout while adjusting the voltage" "0,1"
bitfld.long 0x4 27. "REF_SEL_ERR,Indicates the ref select register bit is out of range" "0,1"
bitfld.long 0x4 26. "ADJ_ERR,Interrupt flag that indicates up and down adjustment requested simultaneously" "0,1"
newline
bitfld.long 0x4 25. "RANGE_ERR,Interrupt flag that indicates a tap has an invalid value" "0,1"
bitfld.long 0x4 24. "LIMIT_ERR,Interrupt flag that indicates a voltage count is at/beyond manufacturer limits" "0,1"
bitfld.long 0x4 23. "VALID_TAP,At least one delay line has been enabled" "0,1"
bitfld.long 0x4 22. "HI_LIMIT_DET,Power supply voltage counter is at high limit" "0,1"
bitfld.long 0x4 21. "LO_LIMIT_DET,Power supply voltage counter is at low limit" "0,1"
bitfld.long 0x4 20. "ADJ_DLY_OK,Indicates the adjustment delay count is at 0" "0,1"
newline
bitfld.long 0x4 19. "MON_DLY_OK,Indicates the monitor delay count is at 0" "0,1"
hexmask.long.byte 0x4 12.--18. 1. "PS_VCNTR,Voltage Count value sent to the power supply"
bitfld.long 0x4 11. "PS_IN_RANGE,Indicates if the power supply is in range" "0,1"
bitfld.long 0x4 10. "FAST_TRIP_DET,Provides the current combined status of all selected High Range delay lines" "0,1"
bitfld.long 0x4 9. "SLOW_TRIP_DET,Provides the current combined status of all selected Low Range delay lines" "0,1"
bitfld.long 0x4 8. "CTR_TAP_SEL,Status of selected center tap delay line detect output" "0,1"
newline
bitfld.long 0x4 7. "CTR_TAP_OK,Tap Enabled and the Tap is withing Hi/Low limits" "0,1"
bitfld.long 0x4 6. "ADJ_ACTIVE,Adjustment to a Direct Voltage" "0,1"
bitfld.long 0x4 5. "ADJ_DWN_ENA,DVS Lowering voltage" "0,1"
bitfld.long 0x4 4. "ADJ_UP_ENA,DVS Raising voltage" "0,1"
hexmask.long.byte 0x4 0.--3. 1. "DVS_STATE,State machine state"
line.long 0x8 "DIRECT,Direct control of target voltage"
hexmask.long.byte 0x8 0.--6. 1. "VOLTAGE,Sets the target power supply value"
line.long 0xC "MON,Monitor Delay"
hexmask.long.byte 0xC 24.--31. 1. "PRE,Number of clocks before DVS_MON_DLY is decremented"
hexmask.long.tbyte 0xC 0.--23. 1. "DLY,Number of prescaled clocks between delay line samples"
line.long 0x10 "ADJ_UP,Up Delay Register"
hexmask.long.byte 0x10 16.--23. 1. "PRE,Number of clocks before DVS_ADJ_UP_DLY is decremented"
hexmask.long.word 0x10 0.--15. 1. "DLY,Number of prescaled clocks between updates of the adjustment delay counter"
line.long 0x14 "ADJ_DWN,Down Delay Register"
hexmask.long.byte 0x14 16.--23. 1. "PRE,Number of clocks before DVS_ADJ_DWN_DLY is decremented"
hexmask.long.word 0x14 0.--15. 1. "DLY,Number of prescaled clocks between updates of the adjustment delay counter"
line.long 0x18 "THRES_CMP,Up Delay Register"
hexmask.long.byte 0x18 8.--14. 1. "VCNTR_THRES_MASK,Mask applied to threshold and vcount to determine if the device is in a low voltage range"
hexmask.long.byte 0x18 0.--6. 1. "VCNTR_THRES_CNT,Value used to determine 'low voltage' range"
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1C)++0x3
line.long 0x0 "TAP_SEL[$1],DVS Tap Select Register"
bitfld.long 0x0 31. "DELAY_ACT,Set if the delay is active" "0,1"
bitfld.long 0x0 29.--30. "DET_DLY,Number of HCLK between delay line launch and sampling" "0,1,2,3"
bitfld.long 0x0 24.--26. "COARSE,Selects delay line tap for coarse or fixed delay portion of the line" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--20. 1. "CTR,Selects delay line tap for center point of auto adjustment"
hexmask.long.byte 0x0 8.--12. 1. "HI,Selects delay line tap for high point of auto adjustment"
bitfld.long 0x0 7. "HI_TAP_STAT,Returns last delay line tap value" "0,1"
newline
bitfld.long 0x0 6. "CTR_TAP_STAT,Returns last delay line tap value" "0,1"
bitfld.long 0x0 5. "LO_TAP_STAT,Returns last delay line tap value" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "LO,Select delay line tap for lower bound of auto adjustment"
repeat.end
tree.end
tree "FCR (Function Control Register)"
base ad:0x40000800
group.long 0x0++0x17
line.long 0x0 "FCTRL0,Function Control 0."
bitfld.long 0x0 25. "I2C2DGEN1,I2C2 SCL Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled."
bitfld.long 0x0 24. "I2C2DGEN0,I2C2 SDA Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled."
bitfld.long 0x0 23. "I2C1DGEN1,I2C1 SCL Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled."
newline
bitfld.long 0x0 22. "I2C1DGEN0,I2C1 SDA Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled."
bitfld.long 0x0 21. "I2C0DGEN1,I2C0 SCL Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled."
bitfld.long 0x0 20. "I2C0DGEN0,I2C0 SDA Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled."
newline
sif (cpuis("MAX78002"))
bitfld.long 0x0 16.--17. "USBCLKSEL,USB Core Clock Select." "0,1,2,3"
endif
line.long 0x4 "AUTOCAL0,Automatic Calibration 0."
hexmask.long.word 0x4 23.--31. 1. "HIRC96MACTMROUT,HIRC96M Trim Value."
hexmask.long.word 0x4 8.--19. 1. "MU,MU value."
bitfld.long 0x4 4. "ATOMIC,Atomic mode." "0: Not Running.,1: Running."
newline
bitfld.long 0x4 3. "GAININV,Invert Gain." "0: Not Running.,1: Running."
bitfld.long 0x4 2. "LDTRM,Load Trim." "0,1"
bitfld.long 0x4 1. "ACRUN,Autocalibration Run." "0: Not Running.,1: Running."
newline
bitfld.long 0x4 0. "ACEN,Auto-calibration Enable." "0: Disabled.,1: Enabled."
line.long 0x8 "AUTOCAL1,Automatic Calibration 1."
hexmask.long.word 0x8 0.--8. 1. "INITTRM,Initial Trim Setting."
line.long 0xC "AUTOCAL2,Automatic Calibration 2"
hexmask.long.word 0xC 8.--20. 1. "ACDIV,Auto-callibration Div Setting."
hexmask.long.byte 0xC 0.--7. 1. "DONECNT,Auto-callibration Done Counter Setting."
line.long 0x10 "URVBOOTADDR,RISC-V Boot Address."
line.long 0x14 "URVCTRL,RISC-V Control Register."
bitfld.long 0x14 1. "IFLUSHEN,URV instruction flush enable." "0,1"
bitfld.long 0x14 0. "MEMSEL,RAM2  RAM3 exclusive ownership." "0,1"
sif (cpuis("MAX78002"))
group.long 0x18++0x3
line.long 0x0 "XO32MKS,RISC-V Control Register."
bitfld.long 0x0 12.--13. "CLKSEL,Kick Start XO Clock Select" "0: No kick start clock.,1: Test Clock in P1.2 (TMR3[22]=1).,2: Internal secondary oscilator,3: Internal Primary Oscilator"
bitfld.long 0x0 11. "PULSE,Kick Start XO 2X Pulse" "0,1"
newline
bitfld.long 0x0 8.--10. "DRIVER,Kick Start XO Driver" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "EN,Kick Start XO Enable" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "CLK,Kick Start XO Counter Setting"
group.long 0x20++0x13
line.long 0x0 "TS0,Temp Sensor trim0"
hexmask.long.word 0x0 0.--11. 1. "GAIN,Unsigned gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET."
line.long 0x4 "TS1,Temp Sensor trim1"
hexmask.long.tbyte 0x4 14.--31. 1. "TS_OFFSET_SIGN,Sign extension of TS_OFFSET[13:0]"
hexmask.long.word 0x4 0.--13. 1. "OFFSET,Signed gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET."
line.long 0x8 "ADCREFTRIM0,Temp Sensor trim1"
hexmask.long.byte 0x8 24.--29. 1. "VX2_TUNE,Controls tuning capacitor in fine DAC (offset binary)"
bitfld.long 0x8 16.--17. "VCM,Trimming code for VCM output of reference buffer" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--14. 1. "VREFM,Trimming code for VREFM output of reference buffer"
hexmask.long.byte 0x8 0.--6. 1. "VREFP,Trimming code for VREFP output of reference buffer"
line.long 0xC "ADCREFTRIM1,Temp Sensor trim1"
hexmask.long.byte 0xC 24.--29. 1. "VX2_TUNE,Controls tuning capacitor in fine DAC (offset binary)"
bitfld.long 0xC 16.--17. "VCM,Trimming code for VCM output of reference buffer" "0,1,2,3"
newline
hexmask.long.byte 0xC 8.--14. 1. "VREFM,Trimming code for VREFM output of reference buffer"
hexmask.long.byte 0xC 0.--6. 1. "VREFP,Trimming code for VREFP output of reference buffer"
line.long 0x10 "ADCREFTRIM2,Temp Sensor trim1"
hexmask.long.byte 0x10 24.--29. 1. "VX2_TUNE,Controls tuning capacitor in fine DAC (offset binary)"
bitfld.long 0x10 16.--17. "VCM,Trimming code for VCM output of reference buffer" "0,1,2,3"
newline
hexmask.long.byte 0x10 8.--14. 1. "VREFM,Trimming code for VREFM output of reference buffer"
hexmask.long.byte 0x10 0.--6. 1. "VREFP,Trimming code for VREFP output of reference buffer"
endif
tree.end
tree "FLC (Flash Memory Control)"
base ad:0x40029000
group.long 0x0++0xB
line.long 0x0 "ADDR,Flash Write Address."
hexmask.long 0x0 0.--31. 1. "ADDR,Address for next operation."
line.long 0x4 "CLKDIV,Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller."
line.long 0x8 "CTRL,Flash Control Register."
hexmask.long.byte 0x8 28.--31. 1. "UNLOCK,Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed."
bitfld.long 0x8 25. "LVE,Low Voltage enable." "0,1"
rbitfld.long 0x8 24. "PEND,Flash Pending. When Flash operation is in progress (busy)  Flash reads and writes will fail. When PEND is set  write to all Flash registers  with exception of the Flash interrupt register  are ignored." "0: Idle.,1: Busy."
newline
hexmask.long.byte 0x8 8.--15. 1. "ERASE_CODE,Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete."
sif (cpuis("MAX78002"))
bitfld.long 0x8 4. "WDTH,Data Width. This bits selects write data width." "0: 128-bit.,1: 32-bit."
endif
bitfld.long 0x8 2. "PGE,Page Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 1. "ME,Mass Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 0. "WR,Write. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
group.long 0x24++0x3
line.long 0x0 "INTR,Flash Interrupt Register."
bitfld.long 0x0 9. "AFIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 8. "DONEIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 1. "AF,Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware." "0: No Failure.,1: Failure occurs."
newline
bitfld.long 0x0 0. "DONE,Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion." "0: No interrupt is pending.,1: An interrupt is pending."
sif (cpuis("MAX78000"))
group.long 0x28++0x3
line.long 0x0 "ECCDATA,ECC Data Register."
hexmask.long.word 0x0 16.--24. 1. "ODD,Error Correction Code Even Data."
hexmask.long.word 0x0 0.--8. 1. "EVEN,Error Correction Code Odd Data."
group.long 0x90++0x3
line.long 0x0 "RLR0,RLR0"
hexmask.long 0x0 0.--31. 1. "RLR0,Access control."
group.long 0x98++0x3
line.long 0x0 "RLR1,RLR1"
hexmask.long 0x0 0.--31. 1. "RLR1,Access control."
endif
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x30)++0x3
line.long 0x0 "DATA[$1],Flash Write Data."
hexmask.long 0x0 0.--31. 1. "DATA,Data next operation."
repeat.end
wgroup.long 0x40++0x3
line.long 0x0 "ACTRL,Access Control Register. Writing the ACTRL register with the following values in the order shown. allows read and write access to the system and user Information block:"
hexmask.long 0x0 0.--31. 1. "ACTRL,Access control."
sif (cpuis("MAX78002"))
group.long 0x5A++0x3
line.long 0x0 "WELR2,WELR2"
hexmask.long 0x0 0.--31. 1. "WELR2,Access control."
endif
group.long 0x80++0x3
line.long 0x0 "WELR0,WELR0"
hexmask.long 0x0 0.--31. 1. "WELR0,Access control."
sif (cpuis("MAX78002"))
group.long 0x84++0x3
line.long 0x0 "RLR0,RLR0"
hexmask.long 0x0 0.--31. 1. "RLR0,Access control."
endif
group.long 0x88++0x3
line.long 0x0 "WELR1,WELR1"
hexmask.long 0x0 0.--31. 1. "WELR1,Access control."
sif (cpuis("MAX78002"))
group.long 0x8C++0x3
line.long 0x0 "RLR1,RLR1"
hexmask.long 0x0 0.--31. 1. "RLR1,Access control."
group.long 0x94++0x13
line.long 0x0 "RLR2,RLR2"
hexmask.long 0x0 0.--31. 1. "RLR2,Access control."
line.long 0x4 "WELR3,WELR3"
hexmask.long 0x4 0.--31. 1. "WELR3,Access control."
line.long 0x8 "RLR3,RLR3"
hexmask.long 0x8 0.--31. 1. "RLR3,Access control."
line.long 0xC "WELR4,WELR4"
hexmask.long 0xC 0.--31. 1. "WELR4,Access control."
line.long 0x10 "RLR4,RLR4"
hexmask.long 0x10 0.--31. 1. "RLR4,Access control."
endif
tree.end
tree "GCFR (General Control Function Registers)"
base ad:0x40005800
group.long 0x0++0xF
line.long 0x0 "REG0,Register 0."
bitfld.long 0x0 3. "cnnx16_3_pwr_en,CNNx16_3 Power Domain Enable" "0,1"
bitfld.long 0x0 2. "cnnx16_2_pwr_en,CNNx16_2 Power Domain Enable" "0,1"
bitfld.long 0x0 1. "cnnx16_1_pwr_en,CNNx16_1 Power Domain Enable" "0,1"
bitfld.long 0x0 0. "cnnx16_0_pwr_en,CNNx16_0 Power Domain Enable" "0,1"
line.long 0x4 "REG1,Register 1."
bitfld.long 0x4 3. "cnnx16_3_ram_en,CNNx16_3 RAM Power Enable" "0,1"
bitfld.long 0x4 2. "cnnx16_2_ram_en,CNNx16_2 RAM Power Enable" "0,1"
bitfld.long 0x4 1. "cnnx16_1_ram_en,CNNx16_1 RAM Power Enable" "0,1"
bitfld.long 0x4 0. "cnnx16_0_ram_en,CNNx16_0 RAM Power Enable" "0,1"
line.long 0x8 "REG2,Register 2."
sif (cpuis("MAX78002"))
bitfld.long 0x8 23. "cnnx16_3_ram_data_ret_en,CNNx16_3 RAM Pad Retention Control" "0,1"
bitfld.long 0x8 22. "cnnx16_2_ram_data_ret_en,CNNx16_2 RAM Pad Retention Control" "0,1"
bitfld.long 0x8 21. "cnnx16_1_ram_data_ret_en,CNNx16_1 RAM Pad Retention Control" "0,1"
bitfld.long 0x8 20. "cnnx16_0_ram_data_ret_en,CNNx16_0 RAM Pad Retention Control" "0,1"
bitfld.long 0x8 19. "cnnx16_3_data_ret_en,CNNx16_3 Pad Retention Control" "0,1"
newline
bitfld.long 0x8 18. "cnnx16_2_data_ret_en,CNNx16_2 Pad Retention Control" "0,1"
bitfld.long 0x8 17. "cnnx16_1_data_ret_en,CNNx16_1 Pad Retention Control" "0,1"
bitfld.long 0x8 16. "cnnx16_0_data_ret_en,CNNx16_0 Pad Retention Control" "0,1"
endif
bitfld.long 0x8 3. "cnnx16_3_iso,CNNx16_3 Power Domain Isolation" "0,1"
bitfld.long 0x8 2. "cnnx16_2_iso,CNNx16_2 Power Domain Isolation" "0,1"
newline
bitfld.long 0x8 1. "cnnx16_1_iso,CNNx16_1 Power Domain Isolation" "0,1"
bitfld.long 0x8 0. "cnnx16_0_iso,CNNx16_0 Power Domain Isolation" "0,1"
line.long 0xC "REG3,Register 3."
bitfld.long 0xC 3. "cnnx16_3_rst,CNNx16_3 Power Domain Reset" "0,1"
bitfld.long 0xC 2. "cnnx16_2_rst,CNNx16_2 Power Domain Reset" "0,1"
bitfld.long 0xC 1. "cnnx16_1_rst,CNNx16_1 Power Domain Reset" "0,1"
bitfld.long 0xC 0. "cnnx16_0_rst,CNNx16_0 Power Domain Reset" "0,1"
tree.end
tree "GCR (Global Control Registers)"
base ad:0x40000000
group.long 0x0++0xF
line.long 0x0 "SYSCTRL,System Control."
sif (cpuis("MAX78000"))
bitfld.long 0x0 16.--17. "OVR,Operating Voltage Range." "0,1,2,3"
bitfld.long 0x0 1. "BSTAPEN,Boundary Scan TAP enable. When enabled  the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE." "0,1"
newline
endif
sif (cpuis("MAX78002"))
bitfld.long 0x0 16.--17. "OVR,Operating Voltage Range." "0: 0.9V,1: 1.0V,2: 1.1V,?"
endif
bitfld.long 0x0 15. "CHKRES,ROM Checksum Result. This bit is only valid when CHKRD=1." "0: ROM Checksum Correct.,1: ROM Checksum Fail."
newline
bitfld.long 0x0 14. "SWD_DIS,Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)." "0,1"
bitfld.long 0x0 13. "CCHK,Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set  software clearing this bit is ignored and the bit will remain set until the operation is completed." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x0 12. "ROMDONE,ROM_DONE status. Used to disable SWD interface during system initialization procedure" "0,1"
bitfld.long 0x0 6. "ICC0_FLUSH,Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4." "0: Normal Code Cache Operation,1: Code Caches and CPU instruction buffer are.."
newline
bitfld.long 0x0 4. "FLASH_PAGE_FLIP,Flips the Flash bottom and top halves. (Depending on the total flash size  each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer." "0: Physical layout matches logical layout.,1: Bottom half mapped to logical top half and vice.."
sif (cpuis("MAX78002"))
bitfld.long 0x0 0. "BSTAPEN,Boundary Scan TAP enable. When enabled  the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE." "0,1"
endif
line.long 0x4 "RST0,Reset."
bitfld.long 0x4 31. "SYS,System Reset. Setting this bit to 1 resets the CPU core and all peripherals  including the watchdog timer." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 30. "PERIPH,Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core  the watchdog timer  and all GPIO pins are unaffected by this reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 29. "SOFT,Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 28. "UART2,UART2 Reset. Setting this bit to 1 resets all UART 2 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 26. "ADC,ADC Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 25. "CNN,CNN Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 24. "TRNG,TRNG Reset. This reset is only available during the manufacture testing phase." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
sif (cpuis("MAX78002"))
bitfld.long 0x4 23. "USB,USB Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
endif
newline
bitfld.long 0x4 22. "SMPHR,Semaphore Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 17. "RTC,Real Time Clock Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 16. "I2C0,I2C 0 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 13. "SPI1,SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 12. "UART1,UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 11. "UART0,UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 8. "TMR3,Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 7. "TMR2,Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 6. "TMR1,Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 5. "TMR0,Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 3. "GPIO1,GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 2. "GPIO0,GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x4 1. "WDT0,Watchdog Timer 0 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x4 0. "DMA,DMA Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
line.long 0x8 "CLKCTRL,Clock Control."
rbitfld.long 0x8 29. "INRO_RDY,8 kHz Low Frequency Reference Clock Ready." "0: Is not Ready.,1: Is Ready."
rbitfld.long 0x8 28. "IBRO_RDY,7.3725 MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
newline
rbitfld.long 0x8 27. "IPO_RDY,100 MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
rbitfld.long 0x8 26. "ISO_RDY,60 MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
newline
rbitfld.long 0x8 25. "ERTCO_RDY,32 kHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
sif (cpuis("MAX78002"))
rbitfld.long 0x8 24. "EBO_RDY,External Base Oscillator Ready." "0: Is not Ready.,1: Is Ready."
endif
newline
bitfld.long 0x8 21. "IBRO_VS,7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO." "0: VCore Supply,1: Dedicated 1V regulated supply."
bitfld.long 0x8 20. "IBRO_EN,7.3725 MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled."
newline
bitfld.long 0x8 19. "IPO_EN,100 MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled."
bitfld.long 0x8 18. "ISO_EN,60 MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled."
newline
bitfld.long 0x8 17. "ERTCO_EN,32 kHz Crystal Oscillator Enable." "0: Is Disabled.,1: Is Enabled."
sif (cpuis("MAX78002"))
bitfld.long 0x8 16. "EBO_EN,External Base Oscillator" "0: Is Disabled.,1: Is Enabled."
newline
endif
rbitfld.long 0x8 13. "SYSCLK_RDY,Clock Ready. This read only bit reflects whether the currently selected system clock source is running." "0: Switchover to the new clock source (as selected..,1: System clock running from CLKSEL clock source."
newline
sif (cpuis("MAX78000"))
bitfld.long 0x8 9.--11. "SYSCLK_SEL,Clock Source Select. This 3 bit field selects the source for the system clock." "0: The internal 60 MHz oscillator is used for the..,?,?,3: 8 kHz LIRC is used for the system clock.,4: The internal 100 MHz oscillator is used for the..,5: The internal 7.3725 MHz oscillator is used for..,6: 32 kHz is used for the system clock.,7: External clock on GPIO0.30."
endif
sif (cpuis("MAX78002"))
bitfld.long 0x8 9.--11. "SYSCLK_SEL,Clock Source Select. This 3 bit field selects the source for the system clock." "0: The internal 60 MHz oscillator is used for the..,1: The internal 120 MHz IPLL is used for the system..,2: The external 25 MHz input is used for the system..,3: 8 kHz LIRC is used for the system clock.,4: The internal 100 MHz oscillator is used for the..,5: The internal 7.3725 MHz oscillator is used for..,6: External 32 kHz input is used for the system..,7: External clock input is used for the system clock."
endif
bitfld.long 0x8 6.--8. "SYSCLK_DIV,Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128."
line.long 0xC "PM,Power Management."
sif (cpuis("MAX78002"))
bitfld.long 0xC 20. "EBO_BP,EBO Bypass" "0,1"
endif
bitfld.long 0xC 17. "IBRO_PD,7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP."
newline
bitfld.long 0xC 16. "IPO_PD,100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP."
bitfld.long 0xC 15. "ISO_PD,60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP."
newline
bitfld.long 0xC 9. "AINCOMP_WE,AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable."
bitfld.long 0xC 7. "WUT_WE,WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable."
newline
sif (cpuis("MAX78002"))
bitfld.long 0xC 6. "USB_WE,USB Wake Up Enable. This bit enables USB IRQ as wakeup source" "0: Wake Up Disable.,1: Wake Up Enable."
endif
bitfld.long 0xC 5. "RTC_WE,RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled  the desired RTC alarm must be configured via the RTC control registers." "0: Wake Up Disable.,1: Wake Up Enable."
newline
bitfld.long 0xC 4. "GPIO_WE,GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set." "0: Wake Up Disable.,1: Wake Up Enable."
hexmask.long.byte 0xC 0.--3. 1. "MODE,Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode."
sif (cpuis("MAX78002"))
group.long 0x10++0x3
line.long 0x0 "IPLL_CTRL,IPLL Control"
bitfld.long 0x0 1. "RDY," "0,1"
bitfld.long 0x0 0. "EN," "0,1"
endif
group.long 0x18++0x3
line.long 0x0 "PCLKDIV,Peripheral Clock Divider."
sif (cpuis("MAX78000"))
bitfld.long 0x0 17. "CNNCLKSEL,CNN Clock Select." "0,1"
hexmask.long.byte 0x0 10.--13. 1. "ADCFRQ,ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ)"
newline
endif
sif (cpuis("MAX78002"))
bitfld.long 0x0 17.--18. "CNNCLKSEL,CNN Clock Select." "0,1,2,3"
endif
bitfld.long 0x0 14.--16. "CNNCLKDIV,CNN Clock Divider." "0,1,2,3,4,5,6,7"
newline
sif (cpuis("MAX78002"))
bitfld.long 0x0 7. "SDIOCLKDIV," "0: 48 MHz,1: 24 MHz"
endif
group.long 0x24++0xB
line.long 0x0 "PCLKDIS0,Peripheral Clock Disable."
bitfld.long 0x0 29. "PT,Pluse Train Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 28. "I2C1,I2C 1 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x0 25. "CNN,CNN Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 23. "ADC,ADC Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x0 18. "TMR3,Timer 3 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 17. "TMR2,Timer 2 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x0 16. "TMR1,Timer 1 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 15. "TMR0,Timer 0 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x0 13. "I2C0,I2C 0 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 10. "UART1,UART 1 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x0 9. "UART0,UART 0 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 6. "SPI1,SPI 1 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x0 5. "DMA,DMA Clock Disable." "0: enable it.,1: disable it."
sif (cpuis("MAX78002"))
bitfld.long 0x0 3. "USB,USB Clock Disable." "0: enable it.,1: disable it."
endif
newline
bitfld.long 0x0 1. "GPIO1,GPIO1 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x0 0. "GPIO0,GPIO0 Clock Disable." "0: enable it.,1: disable it."
line.long 0x4 "MEMCTRL,Memory Clock Control Register."
bitfld.long 0x4 16. "SYSRAM0ECC,SYSRAM0 ECC Select." "0,1"
bitfld.long 0x4 0.--2. "FWS,Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2." "0,1,2,3,4,5,6,7"
line.long 0x8 "MEMZ,Memory Zeroize Control."
sif (cpuis("MAX78002"))
bitfld.long 0x8 11. "USBFIFO,USB FIFO Zeroization." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 10. "ICC1,Instruction Cache 1 Zeroization." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 9. "ICC0,Instruction Cache 0 Zeroization." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 8. "RAM0ECC,System RAM Block 0 ECC Zeroization." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 7. "RAM7,System RAM Block 7 Zeroization." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 6. "RAM6,System RAM Block 6 Zeroization." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 5. "RAM5,System RAM Block 5 Zeroization." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 4. "RAM4,System RAM Block 4 Zeroization." "0: No operation/complete.,1: Start operation."
newline
endif
sif (cpuis("MAX78000"))
bitfld.long 0x8 6. "ICC1,Instruction Cachei 1 Zeroization." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 5. "ICC0,Instruction Cachei 0 Zeroization." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 4. "SYSRAM0ECC,System RAM 0 ECC Zeroization." "0: No operation/complete.,1: Start operation."
endif
bitfld.long 0x8 3. "RAM3,System RAM Block 3 Zeroization." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 2. "RAM2,System RAM Block 2 Zeroization." "0: No operation/complete.,1: Start operation."
bitfld.long 0x8 1. "RAM1,System RAM Block 1 Zeroization." "0: No operation/complete.,1: Start operation."
newline
bitfld.long 0x8 0. "RAM0,System RAM Block 0 Zeroization." "0: No operation/complete.,1: Start operation."
group.long 0x40++0xF
line.long 0x0 "SYSST,System Status Register."
bitfld.long 0x0 0. "ICELOCK,ARM ICE Lock Status." "0: ICE is unlocked.,1: ICE is locked."
line.long 0x4 "RST1,Reset 1."
bitfld.long 0x4 31. "CPU1,CPU1 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
sif (cpuis("MAX78002"))
bitfld.long 0x4 27. "CSI2,CSI2 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
newline
bitfld.long 0x4 26. "PCIF,PCIF Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
endif
bitfld.long 0x4 25. "SIMO,SIMO Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
newline
bitfld.long 0x4 24. "DVS,DVS Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
bitfld.long 0x4 20. "I2C2,I2C2 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
newline
bitfld.long 0x4 19. "I2S,I2S Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
bitfld.long 0x4 16. "SMPHR,SMPHR Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
newline
sif (cpuis("MAX78002"))
bitfld.long 0x4 14. "CSI2PHY,CSI2 PHY Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
endif
bitfld.long 0x4 11. "SPI0,SPI 0 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
newline
bitfld.long 0x4 10. "AES,AES Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
bitfld.long 0x4 9. "CRC,CRC Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
newline
bitfld.long 0x4 7. "OWM,OWM Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
sif (cpuis("MAX78002"))
bitfld.long 0x4 6. "SDHC,SDHC Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
endif
newline
bitfld.long 0x4 1. "PT,PT Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
bitfld.long 0x4 0. "I2C1,I2C1 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
line.long 0x8 "PCLKDIS1,Peripheral Clock Disable."
bitfld.long 0x8 31. "CPU1,CPU1 Clock Disable." "0: Enable.,1: Disable."
sif (cpuis("MAX78002"))
bitfld.long 0x8 30. "CSI2,CSI2 Clock Disable." "0: Enable.,1: Disable."
endif
newline
bitfld.long 0x8 27. "WDT0,Watch Dog Timer 0 Clock Disable." "0: Enable.,1: Disable."
bitfld.long 0x8 24. "I2C2,I2C2 Clock Disable." "0: Enable.,1: Disable."
newline
bitfld.long 0x8 23. "I2S,I2S Clock Disable." "0: Enable.,1: Disable."
bitfld.long 0x8 18. "PCIF,Parallel Camera Interface Clock Disable." "0: Enable.,1: Disable."
newline
bitfld.long 0x8 16. "SPI0,SPI 0 Clock Disable." "0: Enable.,1: Disable."
bitfld.long 0x8 15. "AES,AES Clock Disable." "0: Enable.,1: Disable."
newline
bitfld.long 0x8 14. "CRC,CRC Clock Disable." "0: Enable.,1: Disable."
bitfld.long 0x8 13. "OWM,One-Wire Clock Disable." "0: Enable.,1: Disable."
newline
sif (cpuis("MAX78002"))
bitfld.long 0x8 10. "SDHC,SDHC Clock Disable." "0: Enable.,1: Disable."
endif
bitfld.long 0x8 9. "SMPHR,SMPHR Clock Disable." "0: Enable.,1: Disable."
newline
bitfld.long 0x8 2. "TRNG,TRNG Clock Disable." "0: Enable.,1: Disable."
bitfld.long 0x8 1. "UART2,UART2 Clock Disable." "0: Enable.,1: Disable."
line.long 0xC "EVENTEN,Event Enable Register."
bitfld.long 0xC 2. "TX,Enable TXEV pin event. When this bit is set  TXEV event from the CPU is output to GPIO1.9." "0,1"
sif (cpuis("MAX78000"))
bitfld.long 0xC 1. "RX,Enable RXEV pin event. When this bit is set  a logic high of GPIO1.8 will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1"
newline
endif
bitfld.long 0xC 0. "DMA,Enable DMA event. When this bit is set  a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1"
rgroup.long 0x50++0x3
line.long 0x0 "REVISION,Revision Register."
hexmask.long.word 0x0 0.--15. 1. "REVISION,Manufacturer Chip Revision."
group.long 0x54++0x3
line.long 0x0 "SYSIE,System Status Interrupt Enable Register."
bitfld.long 0x0 0. "ICEUNLOCK,ARM ICE Unlock Interrupt Enable." "0: disabled.,1: enabled."
group.long 0x64++0xF
line.long 0x0 "ECCERR,ECC Error Register"
bitfld.long 0x0 0. "RAM,ECC System RAM0 Error Flag. Write 1 to clear." "0,1"
line.long 0x4 "ECCCED,ECC Not Double Error Detect Register"
bitfld.long 0x4 0. "RAM,ECC System RAM0 Error Flag. Write 1 to clear." "0,1"
line.long 0x8 "ECCIE,ECC IRQ Enable Register"
bitfld.long 0x8 0. "RAM,ECC System RAM0 Error Interrup Enable" "0,1"
line.long 0xC "ECCADDR,ECC Error Address Register"
hexmask.long 0xC 0.--31. 1. "ECCERRAD,ECC Error Address."
sif (cpuis("MAX78000"))
group.long 0x80++0x3
line.long 0x0 "GPR,General Purpose Register."
endif
sif (cpuis("MAX78002"))
group.long 0x80++0x3
line.long 0x0 "GPR0,General Purpose Register 0"
endif
tree.end
tree "GPIO (General-Purpose I/O and Alternate Function Pins)"
base ad:0x0
tree "GPIO0"
base ad:0x40008000
group.long 0x0++0x1B
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
wgroup.long 0x1C++0x7
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
rgroup.long 0x24++0x3
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
group.long 0x28++0x17
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
line.long 0x8 "INEN,GPIO Input Enable"
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
rgroup.long 0x40++0x3
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
group.long 0x48++0xF
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0x5C++0x23
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0xA8++0x13
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
line.long 0x10 "PS,GPIO Pull Select Mode."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0xC0++0x3
line.long 0x0 "VSSEL,GPIO Voltage Select."
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
tree.end
tree "GPIO1"
base ad:0x40009000
group.long 0x0++0x1B
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
wgroup.long 0x1C++0x7
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
rgroup.long 0x24++0x3
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
group.long 0x28++0x17
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
line.long 0x8 "INEN,GPIO Input Enable"
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
rgroup.long 0x40++0x3
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
group.long 0x48++0xF
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0x5C++0x23
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0xA8++0x13
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
line.long 0x10 "PS,GPIO Pull Select Mode."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0xC0++0x3
line.long 0x0 "VSSEL,GPIO Voltage Select."
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
tree.end
tree "GPIO2"
base ad:0x40080400
group.long 0x0++0x1B
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
wgroup.long 0x1C++0x7
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
rgroup.long 0x24++0x3
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
group.long 0x28++0x17
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
line.long 0x8 "INEN,GPIO Input Enable"
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
rgroup.long 0x40++0x3
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
group.long 0x48++0xF
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0x5C++0x23
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0xA8++0x13
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
line.long 0x10 "PS,GPIO Pull Select Mode."
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
group.long 0xC0++0x3
line.long 0x0 "VSSEL,GPIO Voltage Select."
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
tree "I2C0"
base ad:0x4001D000
group.long 0x0++0x17
line.long 0x0 "CTRL,Control Register0."
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
newline
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode  or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
newline
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
newline
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
newline
bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
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rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
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rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
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bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
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bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
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bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
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bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
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bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
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bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
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bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
line.long 0x4 "STATUS,Status Register."
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
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bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
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bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
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rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
line.long 0x8 "INTFL0,Interrupt Status Register."
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
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bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
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bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
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bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
line.long 0xC "INTEN0,Interrupt Enable Register."
bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
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bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
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bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
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bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
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bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
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bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
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bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
line.long 0x10 "INTFL1,Interrupt Status Register 1."
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
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bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter  this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver  this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
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bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
rgroup.long 0x18++0x3
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
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hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
group.long 0x1C++0x27
line.long 0x0 "RXCTRL0,Receive Control Register 0."
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
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bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
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bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
line.long 0x4 "RXCTRL1,Receive Control Register 1."
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
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hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction  except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
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bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
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bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
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bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
line.long 0xC "TXCTRL1,Transmit Control Register 1."
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
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bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
line.long 0x10 "FIFO,Data Register."
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
line.long 0x14 "MSTCTRL,Master Control Register."
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
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bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
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bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
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bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
line.long 0x18 "CLKLO,Clock Low Register."
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode  these bits define the SCL low period. In slave mode  these bits define the time SCL will be held low after data is outputted."
line.long 0x1C "CLKHI,Clock high Register."
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode  these bits define the SCL high period."
line.long 0x20 "HSCLK,Clock high Register."
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode  this is the time SCL is held high after data is output on SDA"
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hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode  this is the time SCL is held low after data is output on SDA."
line.long 0x24 "TIMEOUT,Timeout Register"
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
group.long 0x48++0x3
line.long 0x0 "DMA,DMA Register."
bitfld.long 0x0 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
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bitfld.long 0x0 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4C)++0x3
line.long 0x0 "SLAVE_MULTI[$1],Slave Address Register."
bitfld.long 0x0 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
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bitfld.long 0x0 10. "DIS,Slave Disable." "0,1"
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hexmask.long.word 0x0 0.--9. 1. "ADDR,Slave Address."
repeat.end
group.long 0x4C++0xF
line.long 0x0 "SLAVE0,Slave Address Register."
line.long 0x4 "SLAVE1,Slave Address Register."
line.long 0x8 "SLAVE2,Slave Address Register."
line.long 0xC "SLAVE3,Slave Address Register."
tree.end
tree "I2C1"
base ad:0x4001E000
group.long 0x0++0x17
line.long 0x0 "CTRL,Control Register0."
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
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bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode  or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
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bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
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rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
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bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
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rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
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rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
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bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
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bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
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bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
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bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
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bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
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bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
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bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
line.long 0x4 "STATUS,Status Register."
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
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bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
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bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
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rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
line.long 0x8 "INTFL0,Interrupt Status Register."
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
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bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
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bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
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bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
line.long 0xC "INTEN0,Interrupt Enable Register."
bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
newline
bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
newline
hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
newline
bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
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bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
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bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
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bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
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bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
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bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
line.long 0x10 "INTFL1,Interrupt Status Register 1."
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
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bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter  this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver  this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
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bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
rgroup.long 0x18++0x3
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
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hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
group.long 0x1C++0x27
line.long 0x0 "RXCTRL0,Receive Control Register 0."
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
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bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
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bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
line.long 0x4 "RXCTRL1,Receive Control Register 1."
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
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hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction  except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
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bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
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bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
newline
bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
line.long 0xC "TXCTRL1,Transmit Control Register 1."
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
newline
bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
line.long 0x10 "FIFO,Data Register."
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
line.long 0x14 "MSTCTRL,Master Control Register."
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
newline
bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
newline
bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
newline
bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
line.long 0x18 "CLKLO,Clock Low Register."
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode  these bits define the SCL low period. In slave mode  these bits define the time SCL will be held low after data is outputted."
line.long 0x1C "CLKHI,Clock high Register."
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode  these bits define the SCL high period."
line.long 0x20 "HSCLK,Clock high Register."
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode  this is the time SCL is held high after data is output on SDA"
newline
hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode  this is the time SCL is held low after data is output on SDA."
line.long 0x24 "TIMEOUT,Timeout Register"
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
group.long 0x48++0x3
line.long 0x0 "DMA,DMA Register."
bitfld.long 0x0 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4C)++0x3
line.long 0x0 "SLAVE_MULTI[$1],Slave Address Register."
bitfld.long 0x0 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
newline
bitfld.long 0x0 10. "DIS,Slave Disable." "0,1"
newline
hexmask.long.word 0x0 0.--9. 1. "ADDR,Slave Address."
repeat.end
group.long 0x4C++0xF
line.long 0x0 "SLAVE0,Slave Address Register."
line.long 0x4 "SLAVE1,Slave Address Register."
line.long 0x8 "SLAVE2,Slave Address Register."
line.long 0xC "SLAVE3,Slave Address Register."
tree.end
tree "I2C2"
base ad:0x4001F000
group.long 0x0++0x17
line.long 0x0 "CTRL,Control Register0."
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
newline
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode  or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
newline
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
newline
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
newline
bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
newline
rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
newline
rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
newline
bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
newline
bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
newline
bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
newline
bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
newline
bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
newline
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
newline
bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
line.long 0x4 "STATUS,Status Register."
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
newline
bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
newline
bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
newline
rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
newline
rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
newline
rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
line.long 0x8 "INTFL0,Interrupt Status Register."
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
newline
bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
newline
hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
newline
bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
newline
bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
newline
bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
newline
bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
newline
bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
line.long 0xC "INTEN0,Interrupt Enable Register."
bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
newline
bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
newline
hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
newline
bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
newline
bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
newline
bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
newline
bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
newline
bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
newline
bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
newline
bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
line.long 0x10 "INTFL1,Interrupt Status Register 1."
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
newline
bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter  this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver  this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
newline
bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
newline
bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
rgroup.long 0x18++0x3
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
group.long 0x1C++0x27
line.long 0x0 "RXCTRL0,Receive Control Register 0."
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
newline
bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
newline
bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
line.long 0x4 "RXCTRL1,Receive Control Register 1."
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
newline
hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction  except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
newline
bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
newline
bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
newline
bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
newline
bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
line.long 0xC "TXCTRL1,Transmit Control Register 1."
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
newline
bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
line.long 0x10 "FIFO,Data Register."
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
line.long 0x14 "MSTCTRL,Master Control Register."
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
newline
bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
newline
bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
newline
bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
line.long 0x18 "CLKLO,Clock Low Register."
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode  these bits define the SCL low period. In slave mode  these bits define the time SCL will be held low after data is outputted."
line.long 0x1C "CLKHI,Clock high Register."
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode  these bits define the SCL high period."
line.long 0x20 "HSCLK,Clock high Register."
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode  this is the time SCL is held high after data is output on SDA"
newline
hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode  this is the time SCL is held low after data is output on SDA."
line.long 0x24 "TIMEOUT,Timeout Register"
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
group.long 0x48++0x3
line.long 0x0 "DMA,DMA Register."
bitfld.long 0x0 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x4C)++0x3
line.long 0x0 "SLAVE_MULTI[$1],Slave Address Register."
bitfld.long 0x0 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
newline
bitfld.long 0x0 10. "DIS,Slave Disable." "0,1"
newline
hexmask.long.word 0x0 0.--9. 1. "ADDR,Slave Address."
repeat.end
group.long 0x4C++0xF
line.long 0x0 "SLAVE0,Slave Address Register."
line.long 0x4 "SLAVE1,Slave Address Register."
line.long 0x8 "SLAVE2,Slave Address Register."
line.long 0xC "SLAVE3,Slave Address Register."
tree.end
tree.end
tree "I2S (Inter-IC Sound Interface)"
base ad:0x40060000
group.long 0x0++0x3
line.long 0x0 "CTRL0CH0,Global mode channel."
hexmask.long.byte 0x0 24.--31. 1. "RX_THD_VAL,depth of receive FIFO for threshold interrupt generation."
bitfld.long 0x0 20. "FIFO_LSB,Bit Field Control." "0,1"
bitfld.long 0x0 19. "RST,Write 1 to reset channel." "0,1"
bitfld.long 0x0 18. "FLUSH,Flushes the TX/RX FIFO buffer." "0,1"
bitfld.long 0x0 17. "RX_EN,RX channel enable." "0,1"
bitfld.long 0x0 16. "TX_EN,TX channel enable." "0,1"
newline
bitfld.long 0x0 14.--15. "WSIZE,Data size when write to FIFO." "0,1,2,3"
rbitfld.long 0x0 12.--13. "STEREO,Stereo mode of I2S." "0,1,2,3"
bitfld.long 0x0 11. "EXT_SEL,External SCK/WS selection." "0,1"
rbitfld.long 0x0 10. "ALIGN,Align to MSB or LSB." "0,1"
rbitfld.long 0x0 9. "MSB_LOC,MSB location." "0,1"
bitfld.long 0x0 8. "WS_POL,WS polarity select." "0,1"
newline
bitfld.long 0x0 6.--7. "CH_MODE,SCK Select." "0,1,2,3"
bitfld.long 0x0 5. "PDM_INV,Invert PDM." "0,1"
bitfld.long 0x0 4. "USEDDR,DDR." "0,1"
bitfld.long 0x0 3. "PDM_EN,PDM Enable." "0,1"
bitfld.long 0x0 2. "PDM_FILT,PDM Filter." "0,1"
bitfld.long 0x0 1. "LSB_FIRST,LSB Transmit Receive First." "0,1"
group.long 0x10++0x3
line.long 0x0 "CTRL1CH0,Local channel Setup."
hexmask.long.word 0x0 16.--31. 1. "CLKDIV,I2S clock frequency divisor."
bitfld.long 0x0 15. "ADJUST,LSB/MSB Justify." "0,1"
sif (cpuis("MAX78002"))
bitfld.long 0x0 14. "CLKSEL,I2S clock select." "0,1"
endif
hexmask.long.byte 0x0 9.--13. 1. "SMP_SIZE,I2S sample size length."
bitfld.long 0x0 8. "EN,I2S clock enable." "0,1"
hexmask.long.byte 0x0 0.--4. 1. "BITS_WORD,I2S word length."
group.long 0x20++0x3
line.long 0x0 "FILTCH0,Filter."
group.long 0x30++0x3
line.long 0x0 "DMACH0,DMA Control."
hexmask.long.byte 0x0 24.--31. 1. "RX_LVL,Number of data word in the RX FIFO."
hexmask.long.byte 0x0 16.--23. 1. "TX_LVL,Number of data word in the TX FIFO."
bitfld.long 0x0 15. "DMA_RX_EN,RX DMA channel enable." "0,1"
hexmask.long.byte 0x0 8.--14. 1. "DMA_RX_THD_VAL,RX FIFO Level DMA Trigger."
bitfld.long 0x0 7. "DMA_TX_EN,TX DMA channel enable." "0,1"
hexmask.long.byte 0x0 0.--6. 1. "DMA_TX_THD_VAL,TX FIFO Level DMA Trigger."
group.long 0x40++0x3
line.long 0x0 "FIFOCH0,I2S Fifo."
hexmask.long 0x0 0.--31. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
group.long 0x50++0x13
line.long 0x0 "INTFL,ISR Status."
bitfld.long 0x0 3. "TX_HE_CH0,Status for interrupt when TX FIFO is half empty." "0,1"
bitfld.long 0x0 2. "TX_OB_CH0,Status for interrupt when TX FIFO has only one byte remaining." "0,1"
bitfld.long 0x0 1. "RX_THD_CH0,Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1"
bitfld.long 0x0 0. "RX_OV_CH0,Status for RX FIFO Overrun interrupt." "0,1"
line.long 0x4 "INTEN,Interrupt Enable."
bitfld.long 0x4 3. "TX_HE_CH0,Enable for interrupt when TX FIFO is half empty." "0,1"
bitfld.long 0x4 2. "TX_OB_CH0,Enable for interrupt when TX FIFO has only one byte remaining." "0,1"
bitfld.long 0x4 1. "RX_THD_CH0,Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1"
bitfld.long 0x4 0. "RX_OV_CH0,Enable for RX FIFO Overrun interrupt." "0,1"
line.long 0x8 "EXTSETUP,Ext Control."
hexmask.long.byte 0x8 0.--4. 1. "EXT_BITS_WORD,Word Length for ch_mode."
line.long 0xC "WKEN,Wakeup Enable."
line.long 0x10 "WKFL,Wakeup Flags."
tree.end
tree "ICC (Instruction Cache Controller)"
base ad:0x0
tree "ICC0 (Instruction Cache Controller Registers)"
base ad:0x4002A000
rgroup.long 0x0++0x7
line.long 0x0 "INFO,Cache ID Register."
hexmask.long.byte 0x0 10.--15. 1. "ID,Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter."
hexmask.long.byte 0x0 6.--9. 1. "PARTNUM,Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter."
hexmask.long.byte 0x0 0.--5. 1. "RELNUM,Release Number. Identifies the RTL release version."
line.long 0x4 "SZ,Memory Configuration Register."
hexmask.long.word 0x4 16.--31. 1. "MEM,Main Memory Size. Indicates the total size  in units of 128 Kbytes  of code memory accessible to the cache controller."
hexmask.long.word 0x4 0.--15. 1. "CCH,Cache Size. Indicates total size in Kbytes of cache."
group.long 0x100++0x3
line.long 0x0 "CTRL,Cache Control and Status Register."
rbitfld.long 0x0 16. "RDY,Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0  the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill.." "0: Not Ready.,1: Ready."
bitfld.long 0x0 0. "EN,Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated." "0: Cache Bypassed. Instruction data is stored in..,1: Cache Enabled."
group.long 0x700++0x3
line.long 0x0 "INVALIDATE,Invalidate All Registers."
hexmask.long 0x0 0.--31. 1. "INVALID,Invalidate."
tree.end
sif (cpuis("MAX78002"))
tree "ICC1 (Instruction Cache Controller Registers 1)"
base ad:0x4002AC00
rgroup.long 0x0++0x7
line.long 0x0 "INFO,Cache ID Register."
hexmask.long.byte 0x0 10.--15. 1. "ID,Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter."
hexmask.long.byte 0x0 6.--9. 1. "PARTNUM,Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter."
hexmask.long.byte 0x0 0.--5. 1. "RELNUM,Release Number. Identifies the RTL release version."
line.long 0x4 "SZ,Memory Configuration Register."
hexmask.long.word 0x4 16.--31. 1. "MEM,Main Memory Size. Indicates the total size  in units of 128 Kbytes  of code memory accessible to the cache controller."
hexmask.long.word 0x4 0.--15. 1. "CCH,Cache Size. Indicates total size in Kbytes of cache."
group.long 0x100++0x3
line.long 0x0 "CTRL,Cache Control and Status Register."
rbitfld.long 0x0 16. "RDY,Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0  the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill.." "0: Not Ready.,1: Ready."
bitfld.long 0x0 0. "EN,Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated." "0: Cache Bypassed. Instruction data is stored in..,1: Cache Enabled."
group.long 0x700++0x3
line.long 0x0 "INVALIDATE,Invalidate All Registers."
hexmask.long 0x0 0.--31. 1. "INVALID,Invalidate."
tree.end
endif
tree.end
tree "LPCMP (Low Power Comparator)"
base ad:0x40088000
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "CTRL[$1],Comparator Control Register."
bitfld.long 0x0 15. "INT_FL,IRQ Flag" "0,1"
bitfld.long 0x0 14. "OUT,Raw Compartor Input." "0,1"
bitfld.long 0x0 6. "INT_EN,IRQ Enable." "0,1"
bitfld.long 0x0 5. "POL,Polarity Select" "0,1"
bitfld.long 0x0 0. "EN,Comparator Enable." "0,1"
repeat.end
tree.end
tree "LPGCR (Low Power Global Control Registers)"
base ad:0x40080000
group.long 0x8++0x7
line.long 0x0 "RST,Low Power Reset Register."
bitfld.long 0x0 6. "LPCOMP,Low Power Comparator Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x0 4. "UART3,Low Power UART 3 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x0 3. "TMR5,Low Power Timer 5 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x0 2. "TMR4,Low Power Timer 4 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
newline
bitfld.long 0x0 1. "WDT1,Low Power Watchdog Timer 1 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
bitfld.long 0x0 0. "GPIO2,Low Power GPIO 2 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
line.long 0x4 "PCLKDIS,Low Power Peripheral Clock Disable Register."
bitfld.long 0x4 6. "LPCOMP,Low Power Comparator Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x4 4. "UART3,Low Power UART 3 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x4 3. "TMR5,Low Power Timer 5 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x4 2. "TMR4,Low Power Timer 4 Clock Disable." "0: enable it.,1: disable it."
newline
bitfld.long 0x4 1. "WDT1,Low Power Watchdog 1 Clock Disable." "0: enable it.,1: disable it."
bitfld.long 0x4 0. "GPIO2,Low Power GPIO 2 Clock Disable." "0: enable it.,1: disable it."
tree.end
tree "MCR (Miscellaneous Control Registers)"
base ad:0x40006C00
group.long 0x0++0x13
line.long 0x0 "ECCEN,ECC Enable Register"
bitfld.long 0x0 0. "RAM0,ECC System RAM0 Enable." "0: disabled.,1: enabled."
line.long 0x4 "IPO_MTRIM,IPO Manual Register"
bitfld.long 0x4 8. "TRIM_RANGE,Trim Range Select." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "MTRIM,Manual Trim Value."
line.long 0x8 "OUTEN,Output Enable Register"
bitfld.long 0x8 1. "PDOWN_OUT_EN,Power Down Output Enable." "0,1"
bitfld.long 0x8 0. "SQWOUT_EN,Square Wave Output Enable." "0,1"
line.long 0xC "CMP_CTRL,Comparator Control Register."
bitfld.long 0xC 15. "INT_FL,IRQ Flag" "0,1"
bitfld.long 0xC 14. "OUT,Comparator Output State." "0,1"
bitfld.long 0xC 6. "INT_EN,IRQ Enable." "0,1"
bitfld.long 0xC 5. "POL,Polarity Select" "0,1"
bitfld.long 0xC 0. "EN,Comparator Enable." "0,1"
line.long 0x10 "CTRL,Miscellaneous Control Register."
bitfld.long 0x10 9. "SIMO_RSTD,SIMO System Reset Disable." "0,1"
bitfld.long 0x10 8. "SIMO_CLKSCL_EN,SIMO Clock Scaling Enable." "0,1"
sif (cpuis("MAX78002"))
bitfld.long 0x10 4. "IBRO_EN,IBRO Enable." "0,1"
endif
bitfld.long 0x10 3. "ERTCO_EN,ERTCO Enable." "0,1"
bitfld.long 0x10 2. "INRO_EN,INRO Enable." "0,1"
sif (cpuis("MAX78002"))
bitfld.long 0x10 0.--1. "CMPHYST,Comparator HYST." "0,1,2,3"
endif
group.long 0x20++0x3
line.long 0x0 "GPIO3_CTRL,GPIO3 Pin Control Register."
bitfld.long 0x0 7. "P31_IN,GPIO3 Pin 1 Input Status." "0,1"
bitfld.long 0x0 6. "P31_PE,GPIO3 Pin 1 Pull-up Enable." "0,1"
bitfld.long 0x0 5. "P31_OE,GPIO3 Pin 1 Output Enable." "0,1"
bitfld.long 0x0 4. "P31_DO,GPIO3 Pin 1 Data Output." "0,1"
bitfld.long 0x0 3. "P30_IN,GPIO3 Pin 0 Input Status." "0,1"
bitfld.long 0x0 2. "P30_PE,GPIO3 Pin 0 Pull-up Enable." "0,1"
bitfld.long 0x0 1. "P30_OE,GPIO3 Pin 0 Output Enable." "0,1"
newline
bitfld.long 0x0 0. "P30_DO,GPIO3 Pin 0 Data Output." "0,1"
sif (cpuis("MAX78002"))
group.long 0x40++0x7
line.long 0x0 "CWD0,Code Word Data0"
hexmask.long 0x0 0.--31. 1. "data,Code word Data0 the register retains its value while vregi supply present"
line.long 0x4 "CWD1,Code Word Data1"
hexmask.long 0x4 0.--31. 1. "data,Code word Data0 the register retains its value while vregi supply present"
group.long 0x50++0xB
line.long 0x0 "ADCCFG0,ADC Config 0"
bitfld.long 0x0 3. "REF_SEL,Internal Reference Select Option" "0,1"
bitfld.long 0x0 2. "EXT_REF,External Reference Select Option" "0,1"
newline
bitfld.long 0x0 1. "LP_50K_DIS,Disable 50K divider optionin low power modes" "0,1"
bitfld.long 0x0 0. "LP_5K_DIS,Disable 5K divider optionin low power modes" "0,1"
line.long 0x4 "ADCCFG1,ADC Config 1"
hexmask.long.word 0x4 0.--12. 1. "CHX_PU_DYN,ADC PU dynamic control"
line.long 0x8 "ADCCFG2,ADC Config 2"
bitfld.long 0x8 14.--15. "CH7,Divider option for ADC input channel 7" "0: div1,1: 5k ohom,2: 50k ohom,?"
bitfld.long 0x8 12.--13. "CH6,Divider option for ADC input channel 6" "0: div1,1: 5k ohom,2: 50k ohom,?"
newline
bitfld.long 0x8 10.--11. "CH5,Divider option for ADC input channel 5" "0: div1,1: 5k ohom,2: 50k ohom,?"
bitfld.long 0x8 8.--9. "CH4,Divider option for ADC input channel 4" "0: div1,1: 5k ohom,2: 50k ohom,?"
newline
bitfld.long 0x8 6.--7. "CH3,Divider option for ADC input channel 3" "0: div1,1: 5k ohom,2: 50k ohom,?"
bitfld.long 0x8 4.--5. "CH2,Divider option for ADC input channel 2" "0: div1,1: 5k ohom,2: 50k ohom,?"
newline
bitfld.long 0x8 2.--3. "CH1,Divider option for ADC input channel 1" "0: div1,1: 5k ohom,2: 50k ohom,?"
bitfld.long 0x8 0.--1. "CH0,Divider option for ADC input channel 0" "0: div1,1: 5k ohom,2: 50k ohom,?"
group.long 0x60++0x3
line.long 0x0 "LDOCTRL,LDO Control"
bitfld.long 0x0 1. "2P5EN,LDO 2.5V Enable" "0,1"
bitfld.long 0x0 0. "0P9EN,LDO 0.9V Enable" "0,1"
endif
tree.end
tree "OWM (1-Wire Master)"
base ad:0x4003D000
group.long 0x0++0x17
line.long 0x0 "CFG,1-Wire Master Configuration."
bitfld.long 0x0 7. "int_pullup_enable,Enable intenral pullup." "0,1"
bitfld.long 0x0 6. "overdrive,Enables overdrive speed for 1-Wire operations." "0,1"
bitfld.long 0x0 5. "single_bit_mode,Enable Single Bit TX/RX Mode." "0,1"
bitfld.long 0x0 4. "ext_pullup_enable,Enable External Pullup." "0,1"
bitfld.long 0x0 3. "ext_pullup_mode,Provide an extra output control to control an external pullup." "0,1"
bitfld.long 0x0 2. "bit_bang_en,Bit Bang Enable." "0,1"
newline
bitfld.long 0x0 1. "force_pres_det,Force Line During Presence Detect." "0,1"
bitfld.long 0x0 0. "long_line_mode,Long Line Mode." "0,1"
line.long 0x4 "CLK_DIV_1US,1-Wire Master Clock Divisor."
hexmask.long.byte 0x4 0.--7. 1. "divisor,Clock Divisor for 1Mhz."
line.long 0x8 "CTRL_STAT,1-Wire Master Control/Status."
rbitfld.long 0x8 7. "presence_detect,Presence Pulse Detected." "0,1"
rbitfld.long 0x8 4. "od_spec_mode,Overdrive Spec Mode." "0,1"
rbitfld.long 0x8 3. "ow_input,OW Input State." "0,1"
bitfld.long 0x8 2. "bit_bang_oe,Bit Bang Output Enable." "0,1"
bitfld.long 0x8 1. "sra_mode,SRA Mode." "0,1"
bitfld.long 0x8 0. "start_ow_reset,Start OW Reset." "0,1"
line.long 0xC "DATA,1-Wire Master Data Buffer."
hexmask.long.byte 0xC 0.--7. 1. "tx_rx,TX/RX Buffer."
line.long 0x10 "INTFL,1-Wire Master Interrupt Flags."
bitfld.long 0x10 4. "line_low,OW Line Low Detected Interrupt Flag." "0,1"
bitfld.long 0x10 3. "line_short,OW Line Short Detected Interrupt Flag." "0,1"
bitfld.long 0x10 2. "rx_data_ready,RX Data Ready Interrupt Flag" "0,1"
bitfld.long 0x10 1. "tx_data_empty,TX Data Empty Interrupt Flag." "0,1"
bitfld.long 0x10 0. "ow_reset_done,OW Reset Sequence Completed." "0,1"
line.long 0x14 "INTEN,1-Wire Master Interrupt Enables."
eventfld.long 0x14 4. "line_low,OW Line Low Detected Interrupt Enable." "0,1"
eventfld.long 0x14 3. "line_short,OW Line Short Detected Interrupt Enable." "0,1"
eventfld.long 0x14 2. "rx_data_ready,Rx Data Ready Interrupt Enable." "0,1"
eventfld.long 0x14 1. "tx_data_empty,Tx Data Empty Interrupt Enable." "0,1"
eventfld.long 0x14 0. "ow_reset_done,OW Reset Sequence Completed." "0,1"
tree.end
tree "PT (Pulse Train Engine)"
base ad:0x0
tree "PT"
base ad:0x4003C020
group.long 0x0++0xF
line.long 0x0 "RATE_LENGTH,Pulse Train Configuration"
hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length"
hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train."
line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length."
line.long 0x8 "LOOP,Pulse Train Loop Count"
hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles"
hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat."
line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration."
bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1"
hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select"
bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1"
hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select"
tree.end
tree "PT1"
base ad:0x4003C030
group.long 0x0++0xF
line.long 0x0 "RATE_LENGTH,Pulse Train Configuration"
hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length"
hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train."
line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length."
line.long 0x8 "LOOP,Pulse Train Loop Count"
hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles"
hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat."
line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration."
bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1"
hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select"
bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1"
hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select"
tree.end
tree "PT2"
base ad:0x4003C040
group.long 0x0++0xF
line.long 0x0 "RATE_LENGTH,Pulse Train Configuration"
hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length"
hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train."
line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length."
line.long 0x8 "LOOP,Pulse Train Loop Count"
hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles"
hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat."
line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration."
bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1"
hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select"
bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1"
hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select"
tree.end
tree "PT3"
base ad:0x4003C050
group.long 0x0++0xF
line.long 0x0 "RATE_LENGTH,Pulse Train Configuration"
hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length"
hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train."
line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length."
line.long 0x8 "LOOP,Pulse Train Loop Count"
hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles"
hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat."
line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration."
bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1"
hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select"
bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1"
hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select"
tree.end
tree "PTG"
base ad:0x4003C000
group.long 0x0++0xF
line.long 0x0 "ENABLE,Global Enable/Disable Controls for All Pulse Trains"
bitfld.long 0x0 3. "pt3,Enable/Disable control for PT3" "0,1"
bitfld.long 0x0 2. "pt2,Enable/Disable control for PT2" "0,1"
bitfld.long 0x0 1. "pt1,Enable/Disable control for PT1" "0,1"
bitfld.long 0x0 0. "pt0,Enable/Disable control for PT0" "0,1"
line.long 0x4 "RESYNC,Global Resync (All Pulse Trains) Control"
bitfld.long 0x4 3. "pt3,Resync control for PT3" "0,1"
bitfld.long 0x4 2. "pt2,Resync control for PT2" "0,1"
bitfld.long 0x4 1. "pt1,Resync control for PT1" "0,1"
bitfld.long 0x4 0. "pt0,Resync control for PT0" "0,1"
line.long 0x8 "INTFL,Pulse Train Interrupt Flags"
bitfld.long 0x8 3. "pt3,Pulse Train 3 Stopped Interrupt Flag" "0,1"
bitfld.long 0x8 2. "pt2,Pulse Train 2 Stopped Interrupt Flag" "0,1"
bitfld.long 0x8 1. "pt1,Pulse Train 1 Stopped Interrupt Flag" "0,1"
bitfld.long 0x8 0. "pt0,Pulse Train 0 Stopped Interrupt Flag" "0,1"
line.long 0xC "INTEN,Pulse Train Interrupt Enable/Disable"
bitfld.long 0xC 3. "pt3,Pulse Train 3 Stopped Interrupt Enable/Disable" "0,1"
bitfld.long 0xC 2. "pt2,Pulse Train 2 Stopped Interrupt Enable/Disable" "0,1"
bitfld.long 0xC 1. "pt1,Pulse Train 1 Stopped Interrupt Enable/Disable" "0,1"
bitfld.long 0xC 0. "pt0,Pulse Train 0 Stopped Interrupt Enable/Disable" "0,1"
wgroup.long 0x10++0x7
line.long 0x0 "SAFE_EN,Pulse Train Global Safe Enable."
bitfld.long 0x0 3. "PT3," "0,1"
bitfld.long 0x0 2. "PT2," "0,1"
bitfld.long 0x0 1. "PT1," "0,1"
bitfld.long 0x0 0. "PT0," "0,1"
line.long 0x4 "SAFE_DIS,Pulse Train Global Safe Disable."
bitfld.long 0x4 3. "PT3," "0,1"
bitfld.long 0x4 2. "PT2," "0,1"
bitfld.long 0x4 1. "PT1," "0,1"
bitfld.long 0x4 0. "PT0," "0,1"
tree.end
tree.end
tree "PWRSEQ (Power Sequencer)"
base ad:0x40006800
group.long 0x0++0x23
line.long 0x0 "LPCN,Low Power Control Register."
sif (cpuis("MAX78000"))
bitfld.long 0x0 31. "LPWKST_CLR,Low Power Wakeup Status Register Clear" "0,1"
bitfld.long 0x0 11. "BG_DIS,Bandgap OFF. This controls the System Bandgap in DeepSleep mode." "0: Bandgap is always ON.,1: Bandgap is OFF in DeepSleep mode (default)."
newline
bitfld.long 0x0 9. "LPMFAST,Low Power Mode Clock Select." "0,1"
bitfld.long 0x0 8. "LPMCLKSEL,Low Power Mode APB Clock Select." "0,1"
newline
endif
sif (cpuis("MAX78002"))
bitfld.long 0x0 31. "WKRST,Reset wakeup status registers" "0,1"
endif
sif (cpuis("MAX78002"))
bitfld.long 0x0 11. "BGOFF,Bandgap OFF. This controls the System Bandgap in DeepSleep mode." "0: Bandgap is always ON.,1: Bandgap is OFF in DeepSleep mode (default)."
newline
endif
sif (cpuis("MAX78002"))
bitfld.long 0x0 9. "FAST_ENTRY_DIS,Fast Low Power mode entry disable" "0,1"
bitfld.long 0x0 8. "ISOCLK_SELECT,0 = PCLK 1= ISO CLK use for RISV in Low power mode" "0: PCLK,1: ISO CLK use for RISV in Low power mode"
newline
bitfld.long 0x0 7. "RAMRET7,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 3 retention."
bitfld.long 0x0 6. "RAMRET6,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 3 retention."
newline
bitfld.long 0x0 5. "RAMRET5,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 3 retention."
bitfld.long 0x0 4. "RAMRET4,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 3 retention."
newline
endif
bitfld.long 0x0 3. "RAMRET3,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 3 retention."
bitfld.long 0x0 2. "RAMRET2,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 2 retention."
newline
bitfld.long 0x0 1. "RAMRET1,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 1 retention."
bitfld.long 0x0 0. "RAMRET0,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 0 retention."
line.long 0x4 "LPWKST0,Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0."
bitfld.long 0x4 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.." "0,1"
line.long 0x8 "LPWKEN0,Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0."
hexmask.long 0x8 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
line.long 0xC "LPWKST1,Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1."
sif (cpuis("MAX78000"))
bitfld.long 0xC 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.." "0,1"
endif
sif (cpuis("MAX78002"))
hexmask.long.word 0xC 0.--9. 1. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.."
endif
line.long 0x10 "LPWKEN1,Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1."
sif (cpuis("MAX78000"))
hexmask.long 0x10 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
endif
sif (cpuis("MAX78002"))
hexmask.long.word 0x10 0.--9. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
endif
line.long 0x14 "LPWKST2,Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2."
sif (cpuis("MAX78000"))
bitfld.long 0x14 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.." "0,1"
endif
sif (cpuis("MAX78002"))
hexmask.long.byte 0x14 0.--7. 1. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.."
endif
line.long 0x18 "LPWKEN2,Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2."
sif (cpuis("MAX78000"))
hexmask.long 0x18 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
endif
sif (cpuis("MAX78002"))
hexmask.long.byte 0x18 0.--7. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
endif
line.long 0x1C "LPWKST3,Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3."
sif (cpuis("MAX78000"))
bitfld.long 0x1C 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.." "0,1"
endif
sif (cpuis("MAX78002"))
bitfld.long 0x1C 0.--1. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected  using PM.GPIOWKEN register  and the.." "0,1,2,3"
endif
line.long 0x20 "LPWKEN3,Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3."
sif (cpuis("MAX78000"))
hexmask.long 0x20 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
endif
sif (cpuis("MAX78002"))
bitfld.long 0x20 0.--1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register." "0,1,2,3"
endif
group.long 0x30++0x7
line.long 0x0 "LPPWST,Low Power Peripheral Wakeup Status Register."
bitfld.long 0x0 17. "RESET,Reset Detected Wakeup Flag." "0,1"
bitfld.long 0x0 16. "BACKUP,Backup Mode Wakeup Flag." "0,1"
newline
bitfld.long 0x0 4. "AINCOMP0,Analog Input Comparator Wakeup Flag." "0,1"
line.long 0x4 "LPPWEN,Low Power Peripheral Wakeup Enable Register."
bitfld.long 0x4 26. "LPCMP,LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP." "0,1"
bitfld.long 0x4 25. "SPI1,SPI1 Wakeup Enable. This bit allows wakeup from the SPI1." "0,1"
newline
bitfld.long 0x4 24. "I2S,I2S Wakeup Enable. This bit allows wakeup from the I2S." "0,1"
bitfld.long 0x4 23. "I2C2,I2C2 Wakeup Enable. This bit allows wakeup from the I2C2." "0,1"
newline
bitfld.long 0x4 22. "I2C1,I2C1 Wakeup Enable. This bit allows wakeup from the I2C1." "0,1"
bitfld.long 0x4 21. "I2C0,I2C0 Wakeup Enable. This bit allows wakeup from the I2C0." "0,1"
newline
bitfld.long 0x4 20. "UART3,UART3 Wakeup Enable. This bit allows wakeup from the UART3." "0,1"
bitfld.long 0x4 19. "UART2,UART2 Wakeup Enable. This bit allows wakeup from the UART2." "0,1"
newline
bitfld.long 0x4 18. "UART1,UART1 Wakeup Enable. This bit allows wakeup from the UART1." "0,1"
bitfld.long 0x4 17. "UART0,UART0 Wakeup Enable. This bit allows wakeup from the UART0." "0,1"
newline
bitfld.long 0x4 16. "TMR5,TMR5 Wakeup Enable. This bit allows wakeup from the TMR5." "0,1"
bitfld.long 0x4 15. "TMR4,TMR4 Wakeup Enable. This bit allows wakeup from the TMR4." "0,1"
newline
bitfld.long 0x4 14. "TMR3,TMR3 Wakeup Enable. This bit allows wakeup from the TMR3." "0,1"
bitfld.long 0x4 13. "TMR2,TMR2 Wakeup Enable. This bit allows wakeup from the TMR2." "0,1"
newline
bitfld.long 0x4 12. "TMR1,TMR1 Wakeup Enable. This bit allows wakeup from the TMR1." "0,1"
bitfld.long 0x4 11. "TMR0,TMR0 Wakeup Enable. This bit allows wakeup from the TMR0." "0,1"
newline
bitfld.long 0x4 10. "CPU1,CPU1 Wakeup Enable. This bit allows wakeup from the CPU1." "0,1"
bitfld.long 0x4 9. "WDT1,WDT1 Wakeup Enable. This bit allows wakeup from the WDT1." "0,1"
newline
bitfld.long 0x4 8. "WDT0,WDT0 Wakeup Enable. This bit allows wakeup from the WDT0." "0,1"
bitfld.long 0x4 4. "AINCOMP0,AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0." "0,1"
newline
sif (cpuis("MAX78002"))
bitfld.long 0x4 2. "USBVBUS,USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status." "0,1"
bitfld.long 0x4 0.--1. "USBLS,USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate" "0,1,2,3"
endif
group.long 0x48++0x7
line.long 0x0 "GP0,General Purpose Register 0"
line.long 0x4 "GP1,General Purpose Register 1"
tree.end
tree "RTC (Real Time Clock)"
base ad:0x40006000
group.long 0x0++0x1B
line.long 0x0 "SEC,RTC Second Counter. This register contains the 32-bit second counter."
hexmask.long 0x0 0.--31. 1. "SEC,Seconds Counter."
line.long 0x4 "SSEC,RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00."
hexmask.long.word 0x4 0.--11. 1. "SSEC,Sub-Seconds Counter (12-bit)."
line.long 0x8 "TODA,Time-of-day Alarm."
hexmask.long.tbyte 0x8 0.--19. 1. "TOD_ALARM,Time-of-day Alarm."
line.long 0xC "SSECA,RTC sub-second alarm. This register contains the reload value for the sub-second alarm."
hexmask.long 0xC 0.--31. 1. "SSEC_ALARM,This register contains the reload value for the sub-second alarm."
line.long 0x10 "CTRL,RTC Control Register."
bitfld.long 0x10 15. "WR_EN,Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits." "0: Not active,1: Active"
bitfld.long 0x10 14. "RD_EN,Asynchronous Counter Read Enable." "0,1"
bitfld.long 0x10 9.--10. "SQW_SEL,Frequency Output Selection. When SQE=1  these bits specify the output frequency on the SQW pin." "0: 1 Hz (Compensated).,1: 512 Hz (Compensated).,2: 4 KHz.,3: RTC Input Clock / 8."
bitfld.long 0x10 8. "SQW_EN,Square Wave Output Enable." "0: Not active,1: Active"
newline
rbitfld.long 0x10 7. "SSEC_ALARM,Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor." "0: Not active,1: Active"
rbitfld.long 0x10 6. "TOD_ALARM,Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor." "0: Not active,1: Active"
bitfld.long 0x10 5. "RDY_IE,RTC Ready Interrupt Enable." "0: Disable.,1: Enable."
bitfld.long 0x10 4. "RDY,RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register." "0: Register has not updated.,1: Ready."
newline
rbitfld.long 0x10 3. "BUSY,RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware." "0: Idle.,1: Busy."
bitfld.long 0x10 2. "SSEC_ALARM_IE,Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable."
bitfld.long 0x10 1. "TOD_ALARM_IE,Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable."
bitfld.long 0x10 0. "EN,Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable."
line.long 0x14 "TRIM,RTC Trim Register."
hexmask.long.tbyte 0x14 8.--31. 1. "VRTC_TMR,VBAT Timer Value. When RTC is running off of VBAT  this field is incremented every 32 seconds."
hexmask.long.byte 0x14 0.--7. 1. "TRIM,RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value  with a maximum correction of +/- 127ppm."
line.long 0x18 "OSCCTRL,RTC Oscillator Control Register."
bitfld.long 0x18 5. "SQW_32K,RTC 32kHz Square Wave Output" "0,1"
bitfld.long 0x18 4. "BYPASS,RTC Crystal Bypass" "0,1"
tree.end
sif (cpuis("MAX78002"))
tree "SDHC (Secure Digital Host Controller)"
base ad:0x40037000
group.long 0x0++0x3
line.long 0x0 "SDMA,SDMA System Address / Argument 2."
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address / Argument 2 of Auto CMD23."
group.word 0x4++0x3
line.word 0x0 "BLK_SIZE,Block Size."
bitfld.word 0x0 12.--14. "HOST_BUFF,Host SDMA Buffer Boundary." "0,1,2,3,4,5,6,7"
hexmask.word 0x0 0.--11. 1. "TRANS,Transfer Block Size."
line.word 0x2 "BLK_CNT,Block Count."
hexmask.word 0x2 0.--15. 1. "COUNT,Blocks Count For Current Transfer."
group.long 0x8++0x3
line.long 0x0 "ARG_1,Argument 1."
hexmask.long 0x0 0.--31. 1. "CMD,Command Argument 1."
group.word 0xC++0x3
line.word 0x0 "TRANS,Transfer Mode."
bitfld.word 0x0 5. "MULTI,Multi / Single Block Select." "0,1"
bitfld.word 0x0 4. "READ_WRITE,Data Transfer Direction Select." "0,1"
bitfld.word 0x0 2.--3. "AUTO_CMD_EN,Auto CMD Enable." "0,1,2,3"
bitfld.word 0x0 1. "BLK_CNT_EN,Block Count Enable." "0,1"
newline
bitfld.word 0x0 0. "DMA_EN,DMA Enable." "0,1"
line.word 0x2 "CMD,Command."
hexmask.word.byte 0x2 8.--13. 1. "IDX,Command Index."
bitfld.word 0x2 6.--7. "TYPE,Command Type." "0,1,2,3"
bitfld.word 0x2 5. "DATA_PRES_SEL,Data Present Select." "0,1"
bitfld.word 0x2 4. "IDX_CHK_EN,Command Index Check Enable." "0,1"
newline
bitfld.word 0x2 3. "CRC_CHK_EN,Command CRC Check Enable." "0,1"
bitfld.word 0x2 0.--1. "RESP_TYPE,Response Type Select." "0,1,2,3"
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "RESP[$1],Response 0 Register 0-15."
hexmask.long 0x0 0.--31. 1. "CMD_RESP,Command Response."
repeat.end
group.long 0x20++0x3
line.long 0x0 "BUFFER,Buffer Data Port."
hexmask.long 0x0 0.--31. 1. "DATA,Buffer Data."
rgroup.long 0x24++0x3
line.long 0x0 "PRESENT,Present State."
bitfld.long 0x0 24. "CMD_SIGNAL_LEVEL,CMD Line Signal Level." "0,1"
hexmask.long.byte 0x0 20.--23. 1. "DAT_SIGNAL_LEVEL,DAT[3:0] Line Signal Level."
rbitfld.long 0x0 19. "WP,Write Protect Switch Pin Level." "0,1"
rbitfld.long 0x0 18. "CARD_DETECT,Card Detect Pin Level." "0,1"
newline
rbitfld.long 0x0 17. "CARD_STATE,Card State Stable." "0,1"
rbitfld.long 0x0 16. "CARD_INSERTED,Card Inserted." "0,1"
rbitfld.long 0x0 11. "BUFFER_READ,Buffer Read Enable." "0,1"
rbitfld.long 0x0 10. "BUFFER_WRITE,Buffer Write Enable." "0,1"
newline
rbitfld.long 0x0 9. "READ_TRANSFER,Read Transfer Active." "0,1"
rbitfld.long 0x0 8. "WRITE_TRANSFER,Write Transfer Active." "0,1"
rbitfld.long 0x0 3. "RETUNING,Re-Tuning Request." "0,1"
rbitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active." "0,1"
newline
rbitfld.long 0x0 1. "DAT,Command Inhibit (DAT)." "0,1"
rbitfld.long 0x0 0. "CMD,Command Inhibit (CMD)." "0,1"
group.byte 0x28++0x3
line.byte 0x0 "HOST_CN_1,Host Control 1."
bitfld.byte 0x0 7. "CARD_DETECT_SIGNAL,Card Detect Signal Selection." "0,1"
bitfld.byte 0x0 6. "CARD_DETECT_TEST,Card Detect Test Level." "0,1"
bitfld.byte 0x0 5. "EXT_DATA_TRANSFER_WIDTH,Extended Data Transfer Width." "0,1"
bitfld.byte 0x0 3.--4. "DMA_SELECT,DMA Select." "0,1,2,3"
newline
bitfld.byte 0x0 2. "HS_EN,High Speed Enable." "0,1"
bitfld.byte 0x0 1. "DATA_TRANSFER_WIDTH,Data Transfer Width." "0,1"
bitfld.byte 0x0 0. "LED_CN,LED Control." "0,1"
line.byte 0x1 "PWR,Power Control."
bitfld.byte 0x1 1.--3. "BUS_VOLT_SEL,SD Bus Voltage Select." "0,1,2,3,4,5,6,7"
bitfld.byte 0x1 0. "BUS_POWER,SD Bus Power." "0,1"
line.byte 0x2 "BLK_GAP,Block Gap Control."
bitfld.byte 0x2 3. "INTR,Interrupt At Block Gap." "0,1"
bitfld.byte 0x2 2. "READ_WAIT,Read Wait Control." "0,1"
bitfld.byte 0x2 1. "CONT,Continue Request." "0,1"
bitfld.byte 0x2 0. "STOP,Stop At Block Gap Request." "0,1"
line.byte 0x3 "WAKEUP,Wakeup Control."
bitfld.byte 0x3 2. "CARD_REM,Wakeup Event Enable On SD Card Removal." "0,1"
bitfld.byte 0x3 1. "CARD_INS,Wakeup Event Enable On SD Card Insertion." "0,1"
bitfld.byte 0x3 0. "CARD_INT,Wakeup Event Enable On Card Interrupt." "0,1"
group.word 0x2C++0x1
line.word 0x0 "CLK_CN,Clock Control."
hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FREQ_SEL,SDCLK Frequency Select."
bitfld.word 0x0 6.--7. "UPPER_SDCLK_FREQ_SEL,Upper Bits of SDCLK Frequency Select." "0,1,2,3"
rbitfld.word 0x0 5. "CLK_GEN_SEL,Clock Generator Select." "0,1"
bitfld.word 0x0 2. "SD_CLK_EN,SD Clock Enable." "0,1"
newline
rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable." "0,1"
bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable." "0,1"
group.byte 0x2E++0x1
line.byte 0x0 "TO,Timeout Control."
bitfld.byte 0x0 0.--2. "DATA_COUNT_VALUE,Data Timeout Counter Value." "0,1,2,3,4,5,6,7"
line.byte 0x1 "SW_RESET,Software Reset."
bitfld.byte 0x1 2. "RESET_DAT,Software Reset For DAT Line." "0,1"
bitfld.byte 0x1 1. "RESET_CMD,Software Reset For CMD Line." "0,1"
bitfld.byte 0x1 0. "RESET_ALL,Software Reset For All." "0,1"
group.word 0x30++0xF
line.word 0x0 "INT_STAT,Normal Interrupt Status."
bitfld.word 0x0 15. "ERR_INTR,Error Interrupt." "0,1"
bitfld.word 0x0 12. "RETUNING,Re-Tuning Event." "0,1"
bitfld.word 0x0 8. "CARD_INTR,Card Interrupt." "0,1"
bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal." "0,1"
newline
bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion." "0,1"
bitfld.word 0x0 5. "BUFF_RD_READY,Buffer Read Ready." "0,1"
bitfld.word 0x0 4. "BUFF_WR_READY,Buffer Write Ready." "0,1"
bitfld.word 0x0 3. "DMA,DMA Interrupt." "0,1"
newline
bitfld.word 0x0 2. "BLK_GAP_EVENT,Block Gap Event." "0,1"
bitfld.word 0x0 1. "TRANS_COMP,Transfer Complete." "0,1"
bitfld.word 0x0 0. "CMD_COMP,Command Complete." "0,1"
line.word 0x2 "ER_INT_STAT,Error Interrupt Status."
bitfld.word 0x2 12. "DMA,DMA Error." "0,1"
bitfld.word 0x2 9. "ADMA,ADMA Error." "0,1"
bitfld.word 0x2 8. "AUTO_CMD_12,Auto CMD Error." "0,1"
bitfld.word 0x2 7. "CURRENT_LIMIT,Current Limit Error." "0,1"
newline
bitfld.word 0x2 6. "DATA_END_BIT,Data End Bit Error." "0,1"
bitfld.word 0x2 5. "DATA_CRC,Data CRC Error." "0,1"
bitfld.word 0x2 4. "DATA_TO,Data Timeout Error." "0,1"
bitfld.word 0x2 3. "CMD_IDX,Command Index Error." "0,1"
newline
bitfld.word 0x2 2. "CMD_END_BIT,Command End Bit Error." "0,1"
bitfld.word 0x2 1. "CMD_CRC,Command CRC Error." "0,1"
bitfld.word 0x2 0. "CMD_TO,Command Timeout Error." "0,1"
line.word 0x4 "INT_EN,Normal Interrupt Status Enable."
bitfld.word 0x4 12. "RETUNING,Re-Tuning Event Status Enable." "0,1"
bitfld.word 0x4 8. "CARD_INT,Card Interrupt Status Enable." "0,1"
bitfld.word 0x4 7. "CARD_REMOVAL,Card Removal Status Enable." "0,1"
bitfld.word 0x4 6. "CARD_INSERT,Card Insertion Status Enable." "0,1"
newline
bitfld.word 0x4 5. "BUFFER_RD,Buffer Read Ready Status Enable." "0,1"
bitfld.word 0x4 4. "BUFFER_WR,Buffer Write Ready Status Enable." "0,1"
bitfld.word 0x4 3. "DMA,DMA Interrupt Status Enable." "0,1"
bitfld.word 0x4 2. "BLK_GAP,Block Gap Event Status Enable." "0,1"
newline
bitfld.word 0x4 1. "TRANS_COMP,Transfer Complete Status Enable." "0,1"
bitfld.word 0x4 0. "CMD_COMP,Command Complete Status Enable." "0,1"
line.word 0x6 "ER_INT_EN,Error Interrupt Status Enable."
bitfld.word 0x6 12. "VENDOR,Vendor Specific Error Status Enable." "0,1"
bitfld.word 0x6 10. "TUNING,Tuning Error Status Enable." "0,1"
bitfld.word 0x6 9. "ADMA,ADMA Error Status Enable." "0,1"
bitfld.word 0x6 8. "AUTO_CMD,Auto CMD Error Status Enable." "0,1"
newline
bitfld.word 0x6 6. "DATA_END_BIT,Data End Bit Error Status Enable." "0,1"
bitfld.word 0x6 5. "DATA_CRC,Data CRC Error Status Enable." "0,1"
bitfld.word 0x6 4. "DATA_TO,Data Timeout Error Status Enable." "0,1"
bitfld.word 0x6 3. "CMD_IDX,Command Index Error Status Enable." "0,1"
newline
bitfld.word 0x6 2. "CMD_END_BIT,Command End Bit Error Status Enable." "0,1"
bitfld.word 0x6 1. "CMD_CRC,Command CRC Error Status Enable." "0,1"
bitfld.word 0x6 0. "CMD_TO,Command Timeout Error Status Enable." "0,1"
line.word 0x8 "INT_SIGNAL,Normal Interrupt Signal Enable."
bitfld.word 0x8 12. "RETUNING,Re-Tuning Event Signal Enable." "0,1"
bitfld.word 0x8 8. "CARD_INT,Card Interrupt Signal Enable." "0,1"
bitfld.word 0x8 7. "CARD_REMOVAL,Card Removal Signal Enable." "0,1"
bitfld.word 0x8 6. "CARD_INSERT,Card Insertion Signal Enable." "0,1"
newline
bitfld.word 0x8 5. "BUFFER_RD,Buffer Read Ready Signal Enable." "0,1"
bitfld.word 0x8 4. "BUFFER_WR,Buffer Write Ready Signal Enable." "0,1"
bitfld.word 0x8 3. "DMA,DMA Interrupt Signal Enable." "0,1"
bitfld.word 0x8 2. "BLK_GAP,Block Gap Event Signal Enable." "0,1"
newline
bitfld.word 0x8 1. "TRANS_COMP,Transfer Complete Signal Enable." "0,1"
bitfld.word 0x8 0. "CMD_COMP,Command Complete Signal Enable." "0,1"
line.word 0xA "ER_INT_SIGNAL,Error Interrupt Signal Enable."
bitfld.word 0xA 12. "TAR_RESP,Target Response Error Signal Enable." "0,1"
bitfld.word 0xA 10. "TUNING,Tuning Error Signal Enable." "0,1"
bitfld.word 0xA 9. "ADMA,ADMA Error Signal Enable." "0,1"
bitfld.word 0xA 8. "AUTO_CMD,Auto CMD Error Signal Enable." "0,1"
newline
bitfld.word 0xA 7. "CURR_LIM,Current Limit Error Signal Enable." "0,1"
bitfld.word 0xA 6. "DATA_END_BIT,Data End Bit Error Signal Enable." "0,1"
bitfld.word 0xA 5. "DATA_CRC,Data CRC Error Signal Enable." "0,1"
bitfld.word 0xA 4. "DATA_TO,Data Timeout Error Signal Enable." "0,1"
newline
bitfld.word 0xA 3. "CMD_IDX,Command Index Error Signal Enable." "0,1"
bitfld.word 0xA 2. "CMD_END_BIT,Command End Bit Error Signal Enable." "0,1"
bitfld.word 0xA 1. "CMD_CRC,Command CRC Error Signal Enable." "0,1"
bitfld.word 0xA 0. "CMD_TO,Command Timeout Error Signal Enable." "0,1"
line.word 0xC "AUTO_CMD_ER,Auto CMD Error Status."
bitfld.word 0xC 7. "NOT_ISSUED,Command Not Issued By Auto CMD12 Error." "0,1"
bitfld.word 0xC 4. "INDEX,Auto CMD Index Error." "0,1"
bitfld.word 0xC 3. "END_BIT,Auto CMD End Bit Error." "0,1"
bitfld.word 0xC 2. "CRC,Auto CMD CRC Error." "0,1"
newline
bitfld.word 0xC 1. "TO,Auto CMD Timeout Error." "0,1"
bitfld.word 0xC 0. "NOT_EXCUTED,Auto CMD12 Not Executed." "0,1"
line.word 0xE "HOST_CN_2,Host Control 2."
bitfld.word 0xE 15. "PRESET_VAL_EN,Preset Value Enable." "0,1"
bitfld.word 0xE 14. "ASYNCH_INT,Asynchronous Interrupt Enable." "0,1"
bitfld.word 0xE 7. "SAMPLING_CLK,Sampling Clock Select." "0,1"
bitfld.word 0xE 6. "EXCUTE,Execute Tuning." "0,1"
newline
bitfld.word 0xE 4.--5. "DRIVER_STRENGTH,Driver Strength Select." "0,1,2,3"
bitfld.word 0xE 3. "SIGNAL_V1_8,1.8V Signaling Enable." "0,1"
bitfld.word 0xE 0.--1. "UHS,UHS Mode Select." "0,1,2,3"
rgroup.long 0x40++0xB
line.long 0x0 "CFG_0,Capabilities 0-31."
bitfld.long 0x0 30.--31. "SLOT_TYPE,Slot Type." "0,1,2,3"
bitfld.long 0x0 29. "ASYNC_INT,Asynchronous Interrupt Support." "0,1"
bitfld.long 0x0 28. "BIT_64_SYS_BUS,64-bit System Bus Support." "0,1"
bitfld.long 0x0 26. "V1_8,Voltage Support 1.8V." "0,1"
newline
bitfld.long 0x0 25. "V3_0,Voltage Support 3.0V." "0,1"
bitfld.long 0x0 24. "V3_3,Voltage Support 3.3V." "0,1"
bitfld.long 0x0 23. "SUSPEND,Suspend/Resume Support." "0,1"
bitfld.long 0x0 22. "SDMA,SDMA Support." "0,1"
newline
bitfld.long 0x0 21. "HS,High Speed Support." "0,1"
bitfld.long 0x0 19. "ADMA2,ADMA2 Support." "0,1"
bitfld.long 0x0 18. "BIT_8,8-bit Support for Embedded Device." "0,1"
bitfld.long 0x0 16.--17. "MAX_BLK_LEN,Max Block Length." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--15. 1. "CLK_FREQ,Base Clock Frequency For SD Clock."
bitfld.long 0x0 7. "TO_CLK_UNIT,Timeout Clock Unit." "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TO_CLK_FREQ,Timeout Clock Frequency."
line.long 0x4 "CFG_1,Capabilities 32-63."
hexmask.long.byte 0x4 16.--23. 1. "CLK_MULTI,Clock Multiplier."
bitfld.long 0x4 14.--15. "RETUNING,Re-Tuning Modes." "0,1,2,3"
bitfld.long 0x4 13. "TUNING_SDR50,Use Tuning for SDR50." "0,1"
hexmask.long.byte 0x4 8.--11. 1. "TIMER_CNT_TUNING,Timer Count for Re-Tuning."
newline
bitfld.long 0x4 6. "DRIVER_D,Driver Type D Support." "0,1"
bitfld.long 0x4 5. "DRIVER_C,Driver Type C Support." "0,1"
bitfld.long 0x4 4. "DRIVER_A,Driver Type A Support." "0,1"
bitfld.long 0x4 2. "DDR50,DDR50 Support." "0,1"
newline
bitfld.long 0x4 1. "SDR104,SDR104 Support." "0,1"
bitfld.long 0x4 0. "SDR50,SDR50 Support." "0,1"
line.long 0x8 "MAX_CURR_CFG,Maximum Current Capabilities."
hexmask.long.byte 0x8 16.--23. 1. "V1_8,Maximum Current for 1.8V."
hexmask.long.byte 0x8 8.--15. 1. "V3_0,Maximum Current for 3.0V."
hexmask.long.byte 0x8 0.--7. 1. "V3_3,Maximum Current for 3.3V."
wgroup.word 0x50++0x1
line.word 0x0 "FORCE_CMD,Force Event for Auto CMD Error Status."
bitfld.word 0x0 7. "NOT_ISSUED,Force Event for Command Not Issued By Auto CMD12 Error." "0,1"
bitfld.word 0x0 4. "INDEX,Force Event for Auto CMD Index Error." "0,1"
bitfld.word 0x0 3. "END_BIT,Force Event for Auto CMD End Bit Error." "0,1"
bitfld.word 0x0 2. "CRC,Force Event for Auto CMD CRC Error." "0,1"
newline
bitfld.word 0x0 1. "TO,Force Event for Auto CMD Timeout Error." "0,1"
bitfld.word 0x0 0. "NOT_EXCU,Force Event for Auto CMD12 Not Executed." "0,1"
group.word 0x52++0x1
line.word 0x0 "FORCE_EVENT_INT_STAT,Force Event for Error Interrupt Status."
bitfld.word 0x0 12.--14. "VENDOR,Force Event for Vendor Specific Error Status." "0,1,2,3,4,5,6,7"
bitfld.word 0x0 9. "ADMA,Force Event for ADMA Error." "0,1"
rbitfld.word 0x0 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1"
rbitfld.word 0x0 7. "CURR_LIMIT,Force Event for Current Limit Error." "0,1"
newline
rbitfld.word 0x0 6. "DATA_END_BIT,Force Event for Data End Bit Error." "0,1"
rbitfld.word 0x0 5. "DATA_CRC,Force Event for Data CRC Error." "0,1"
rbitfld.word 0x0 4. "DATA_TO,Force Event for Data Timeout Error." "0,1"
rbitfld.word 0x0 3. "CMD_INDEX,Force Event for Command Index Error." "0,1"
newline
rbitfld.word 0x0 2. "CMD_END_BIT,Force Event for Command End Bit Error." "0,1"
rbitfld.word 0x0 1. "CMD_CRC,Force Event for Command CRC Error." "0,1"
rbitfld.word 0x0 0. "CMD_TO,Force Event for Command Timeout Error." "0,1"
group.byte 0x54++0x0
line.byte 0x0 "ADMA_ER,ADMA Error Status."
bitfld.byte 0x0 2. "LEN_MISMATCH,ADMA Length Mismatch Error." "0,1"
bitfld.byte 0x0 0.--1. "STATE,ADMA Error State." "0,1,2,3"
group.long 0x58++0x7
line.long 0x0 "ADMA_ADDR_0,ADMA System Address 0-31."
hexmask.long 0x0 0.--31. 1. "ADDR,ADMA System Address Part 1 (part 2 is ADMA_ADDR_1)."
line.long 0x4 "ADMA_ADDR_1,ADMA System Address 32-63."
hexmask.long 0x4 0.--31. 1. "ADDR,ADMA System Address Part 1 (part 2 is ADMA_ADDR_1)."
rgroup.word 0x60++0xF
line.word 0x0 "PRESET_0,Preset Value for Initialization."
bitfld.word 0x0 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0x0 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0x0 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0x2 "PRESET_1,Preset Value for Default Speed."
bitfld.word 0x2 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0x2 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0x2 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0x4 "PRESET_2,Preset Value for High Speed."
bitfld.word 0x4 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0x4 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0x4 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0x6 "PRESET_3,Preset Value for SDR12."
bitfld.word 0x6 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0x6 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0x6 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0x8 "PRESET_4,Preset Value for SDR25."
bitfld.word 0x8 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0x8 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0x8 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0xA "PRESET_5,Preset Value for SDR50."
bitfld.word 0xA 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0xA 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0xA 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0xC "PRESET_6,Preset Value for SDR104."
bitfld.word 0xC 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0xC 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0xC 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
line.word 0xE "PRESET_7,Preset Value for DDR50."
bitfld.word 0xE 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3"
bitfld.word 0xE 10. "CLK_GEN,Clock Generator Select Value." "0,1"
hexmask.word 0xE 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value."
group.long 0xE0++0x3
line.long 0x0 "SHARED_BUS,SHARED_BUS."
rgroup.word 0xFC++0x1
line.word 0x0 "SLOT_INT,Slot Interrupt Status."
bitfld.word 0x0 0. "INT_SIGNALS,Interrupt Signal For Each Slot." "0,1"
group.word 0xFE++0x1
line.word 0x0 "HOST_CN_VER,Host Controller Version."
hexmask.word.byte 0x0 8.--15. 1. "VEND_VER,Vendor Version Number."
hexmask.word.byte 0x0 0.--7. 1. "SPEC_VER,Specification Version Number."
tree.end
endif
tree "SEMA (Semaphore)"
base ad:0x4003E000
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SEMAPHORES[$1],Read to test and set. returns prior value. Write 0 to clear semaphore."
bitfld.long 0x0 0. "sema," "0,1"
repeat.end
group.long 0x40++0xF
line.long 0x0 "irq0,Semaphore IRQ0 register."
bitfld.long 0x0 16. "cm4_irq," "0,1"
bitfld.long 0x0 0. "en," "0,1"
line.long 0x4 "mail0,Semaphore Mailbox 0 register."
hexmask.long 0x4 0.--31. 1. "data,"
line.long 0x8 "irq1,Semaphore IRQ1 register."
bitfld.long 0x8 16. "rv32_irq," "0,1"
bitfld.long 0x8 0. "en," "0,1"
line.long 0xC "mail1,Semaphore Mailbox 1 register."
hexmask.long 0xC 0.--31. 1. "data,"
group.long 0x100++0x3
line.long 0x0 "status,Semaphore status bits. 0 indicates the semaphore is free. 1 indicates taken."
bitfld.long 0x0 7. "status7," "0,1"
bitfld.long 0x0 6. "status6," "0,1"
bitfld.long 0x0 5. "status5," "0,1"
bitfld.long 0x0 4. "status4," "0,1"
bitfld.long 0x0 3. "status3," "0,1"
bitfld.long 0x0 2. "status2," "0,1"
bitfld.long 0x0 1. "status1," "0,1"
bitfld.long 0x0 0. "status0," "0,1"
tree.end
tree "SIMO (Single-Inductor Multiple-Output Power Supply)"
base ad:0x40004400
group.long 0x4++0x1B
line.long 0x0 "VREGO_A,Buck Voltage Regulator A Control Register"
bitfld.long 0x0 7. "RANGEA,Regulator Output Range Set" "0: Low output voltage range,1: High output voltage range"
hexmask.long.byte 0x0 0.--6. 1. "VSETA,Regulator Output Voltage Setting"
line.long 0x4 "VREGO_B,Buck Voltage Regulator B Control Register"
bitfld.long 0x4 7. "RANGEB,Regulator Output Range Set" "0: Low output voltage range,1: High output voltage range"
hexmask.long.byte 0x4 0.--6. 1. "VSETB,Regulator Output Voltage Setting"
line.long 0x8 "VREGO_C,Buck Voltage Regulator C Control Register"
bitfld.long 0x8 7. "RANGEC,Regulator Output Range Set" "0: Low output voltage range,1: High output voltage range"
hexmask.long.byte 0x8 0.--6. 1. "VSETC,Regulator Output Voltage Setting"
line.long 0xC "VREGO_D,Buck Voltage Regulator D Control Register"
bitfld.long 0xC 7. "RANGED,Regulator Output Range Set" "0: Low output voltage range,1: High output voltage range"
hexmask.long.byte 0xC 0.--6. 1. "VSETD,Regulator Output Voltage Setting"
line.long 0x10 "IPKA,High Side FET Peak Current VREGO_A/VREGO_B Register"
hexmask.long.byte 0x10 4.--7. 1. "IPKSETB,Voltage Regulator Peak Current Setting"
hexmask.long.byte 0x10 0.--3. 1. "IPKSETA,Voltage Regulator Peak Current Setting"
line.long 0x14 "IPKB,High Side FET Peak Current VREGO_C/VREGO_D Register"
hexmask.long.byte 0x14 4.--7. 1. "IPKSETD,Voltage Regulator Peak Current Setting"
hexmask.long.byte 0x14 0.--3. 1. "IPKSETC,Voltage Regulator Peak Current Setting"
line.long 0x18 "MAXTON,Maximum High Side FET Time On Register"
hexmask.long.byte 0x18 0.--3. 1. "TONSET,Sets the maximum on time for the high side FET  each increment represents 500ns"
rgroup.long 0x20++0xF
line.long 0x0 "ILOAD_A,Buck Cycle Count VREGO_A Register"
hexmask.long.byte 0x0 0.--7. 1. "ILOADA,Number of buck cycles that occur within the cycle clock"
line.long 0x4 "ILOAD_B,Buck Cycle Count VREGO_B Register"
hexmask.long.byte 0x4 0.--7. 1. "ILOADB,Number of buck cycles that occur within the cycle clock"
line.long 0x8 "ILOAD_C,Buck Cycle Count VREGO_C Register"
hexmask.long.byte 0x8 0.--7. 1. "ILOADC,Number of buck cycles that occur within the cycle clock"
line.long 0xC "ILOAD_D,Buck Cycle Count VREGO_D Register"
hexmask.long.byte 0xC 0.--7. 1. "ILOADD,Number of buck cycles that occur within the cycle clock"
group.long 0x30++0xF
line.long 0x0 "BUCK_ALERT_THR_A,Buck Cycle Count Alert VERGO_A Register"
hexmask.long.byte 0x0 0.--7. 1. "BUCKTHRA,Threshold for ILOADA to generate the BUCK_ALERT"
line.long 0x4 "BUCK_ALERT_THR_B,Buck Cycle Count Alert VERGO_B Register"
hexmask.long.byte 0x4 0.--7. 1. "BUCKTHRB,Threshold for ILOADB to generate the BUCK_ALERT"
line.long 0x8 "BUCK_ALERT_THR_C,Buck Cycle Count Alert VERGO_C Register"
hexmask.long.byte 0x8 0.--7. 1. "BUCKTHRC,Threshold for ILOADC to generate the BUCK_ALERT"
line.long 0xC "BUCK_ALERT_THR_D,Buck Cycle Count Alert VERGO_D Register"
hexmask.long.byte 0xC 0.--7. 1. "BUCKTHRD,Threshold for ILOADD to generate the BUCK_ALERT"
rgroup.long 0x40++0x13
line.long 0x0 "BUCK_OUT_READY,Buck Regulator Output Ready Register"
bitfld.long 0x0 3. "BUCKOUTRDYD,When set  indicates that the output voltage has reached its regulated value" "0: Output voltage not in range,1: Output voltage in range"
bitfld.long 0x0 2. "BUCKOUTRDYC,When set  indicates that the output voltage has reached its regulated value" "0: Output voltage not in range,1: Output voltage in range"
bitfld.long 0x0 1. "BUCKOUTRDYB,When set  indicates that the output voltage has reached its regulated value" "0: Output voltage not in range,1: Output voltage in range"
newline
bitfld.long 0x0 0. "BUCKOUTRDYA,When set  indicates that the output voltage has reached its regulated value" "0: Output voltage not in range,1: Output voltage in range"
line.long 0x4 "ZERO_CROSS_CAL_A,Zero Cross Calibration VERGO_A Register"
hexmask.long.byte 0x4 0.--3. 1. "ZXCALA,Zero Cross Calibrartion Value VREGO_A"
line.long 0x8 "ZERO_CROSS_CAL_B,Zero Cross Calibration VERGO_B Register"
hexmask.long.byte 0x8 0.--3. 1. "ZXCALB,Zero Cross Calibrartion Value VREGO_B"
line.long 0xC "ZERO_CROSS_CAL_C,Zero Cross Calibration VERGO_C Register"
hexmask.long.byte 0xC 0.--3. 1. "ZXCALC,Zero Cross Calibrartion Value VREGO_C"
line.long 0x10 "ZERO_CROSS_CAL_D,Zero Cross Calibration VERGO_D Register"
hexmask.long.byte 0x10 0.--3. 1. "ZXCALD,Zero Cross Calibrartion Value VREGO_D"
tree.end
tree "SIR (System Initialization Registers)"
base ad:0x40000400
rgroup.long 0x0++0x3
line.long 0x0 "SISTAT,System Initialization Status Register."
bitfld.long 0x0 1. "CRCERR,CRC Error Status. This bit is set by the system initialization block following power-up." "0: No CRC errors occurred during the read of the..,1: A CRC error occurred while reading the OTP. The.."
bitfld.long 0x0 0. "MAGIC,Magic Word Validation. This bit is set by the system initialization block following power-up." "0: Magic word was not set (OTP has not been..,1: Magic word was set (OTP contains valid settings)."
sif (cpuis("MAX78000"))
rgroup.long 0x4++0x3
line.long 0x0 "ADDR,Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)."
hexmask.long 0x0 0.--31. 1. "ERRADDR,"
endif
sif (cpuis("MAX78002"))
rgroup.long 0x4++0x3
line.long 0x0 "SIADDR,Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)."
hexmask.long 0x0 0.--31. 1. "ERRADDR,"
endif
rgroup.long 0x100++0x7
line.long 0x0 "FSTAT,funcstat register."
bitfld.long 0x0 7. "SMPHR,SMPHR function." "0,1"
sif (cpuis("MAX78002"))
bitfld.long 0x0 6. "SDIO,SDIO Function." "0,1"
endif
bitfld.long 0x0 2. "ADC,10-bit Sigma Delta ADC." "0,1"
sif (cpuis("MAX78002"))
bitfld.long 0x0 1. "USB,USB Function." "0,1"
newline
endif
bitfld.long 0x0 0. "FPU,FPU Function." "0,1"
line.long 0x4 "SFSTAT,Security function status register."
sif (cpuis("MAX78002"))
bitfld.long 0x4 3. "AES,AES Block." "0,1"
bitfld.long 0x4 2. "TRNG,TRNG Function." "0,1"
endif
sif (cpuis("MAX78000"))
bitfld.long 0x4 2. "AES,AES Block." "0,1"
bitfld.long 0x4 0. "TRNG,TRNG Function." "0,1"
endif
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
sif (cpuis("MAX78000"))
tree "SPI0"
base ad:0x400BE000
group.long 0x0++0x3
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
group.word ($2)++0x1
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
group.long 0x4++0x13
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select  when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
newline
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
bitfld.long 0x0 4. "SS_IO,Slave Select 0  IO direction  to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
newline
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity  each Slave Select can have unique polarity."
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
newline
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
newline
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
newline
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode  reload[15:8]."
newline
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode  reload[7:0]."
group.long 0x1C++0x13
line.long 0x0 "DMA,Register for controlling DMA."
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
newline
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
newline
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request  also level for threshold status. When RX FIFO has more than this many bytes  the associated events and conditions are triggered."
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
newline
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
newline
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request  also level for threshold status. When TX FIFO has fewer than this many bytes  the associated events and conditions are triggered."
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun  set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun  set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun  set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun  set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 11. "MST_DONE,Master Done  set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x8 "INTEN,Register for enabling interrupts."
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x10 "WKEN,Register for wake up enable."
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
newline
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
rgroup.long 0x30++0x3
line.long 0x0 "STAT,SPI Status register."
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode  set when transaction starts  cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode  set when Slave Select is asserted  cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
tree.end
endif
sif (cpuis("MAX78000"))
tree "SPI1"
base ad:0x40046000
group.long 0x0++0x3
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
group.word ($2)++0x1
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
group.long 0x4++0x13
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select  when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
newline
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
bitfld.long 0x0 4. "SS_IO,Slave Select 0  IO direction  to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
newline
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity  each Slave Select can have unique polarity."
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
newline
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
newline
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
newline
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode  reload[15:8]."
newline
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode  reload[7:0]."
group.long 0x1C++0x13
line.long 0x0 "DMA,Register for controlling DMA."
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
newline
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
newline
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request  also level for threshold status. When RX FIFO has more than this many bytes  the associated events and conditions are triggered."
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
newline
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
newline
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request  also level for threshold status. When TX FIFO has fewer than this many bytes  the associated events and conditions are triggered."
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun  set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun  set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun  set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun  set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 11. "MST_DONE,Master Done  set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x8 "INTEN,Register for enabling interrupts."
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x10 "WKEN,Register for wake up enable."
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
newline
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
rgroup.long 0x30++0x3
line.long 0x0 "STAT,SPI Status register."
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode  set when transaction starts  cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode  set when Slave Select is asserted  cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
tree.end
endif
sif (cpuis("MAX78002"))
tree "SPI0"
base ad:0x400BE000
group.long 0x0++0x3
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
group.word ($2)++0x1
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
group.long 0x4++0x13
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select  when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
newline
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
bitfld.long 0x0 4. "SS_IO,Slave Select 0  IO direction  to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
newline
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity  each Slave Select can have unique polarity."
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
newline
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
newline
bitfld.long 0x8 4. "SCLK_FB_INV,SCLK_FB_INV." "0,1"
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
newline
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
newline
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
bitfld.long 0x10 24.--26. "AFP_FCD,Automatic frequency prescalar." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
newline
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode  reload[15:8]."
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode  reload[7:0]."
group.long 0x1C++0x13
line.long 0x0 "DMA,Register for controlling DMA."
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
newline
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
newline
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request  also level for threshold status. When RX FIFO has more than this many bytes  the associated events and conditions are triggered."
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
newline
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
newline
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request  also level for threshold status. When TX FIFO has fewer than this many bytes  the associated events and conditions are triggered."
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun  set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun  set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun  set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun  set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 11. "MST_DONE,Master Done  set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x8 "INTEN,Register for enabling interrupts."
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x10 "WKEN,Register for wake up enable."
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
newline
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
rgroup.long 0x30++0x3
line.long 0x0 "STAT,SPI Status register."
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode  set when transaction starts  cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode  set when Slave Select is asserted  cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
tree.end
endif
sif (cpuis("MAX78002"))
tree "SPI1"
base ad:0x40046000
group.long 0x0++0x3
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
group.word ($2)++0x1
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
group.byte ($2)++0x0
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO  write to put into TX FIFO."
repeat.end
group.long 0x4++0x13
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select  when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
newline
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
bitfld.long 0x0 4. "SS_IO,Slave Select 0  IO direction  to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
newline
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity  each Slave Select can have unique polarity."
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
newline
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
newline
bitfld.long 0x8 4. "SCLK_FB_INV,SCLK_FB_INV." "0,1"
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
newline
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
newline
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
bitfld.long 0x10 24.--26. "AFP_FCD,Automatic frequency prescalar." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
newline
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode  reload[15:8]."
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode  reload[7:0]."
group.long 0x1C++0x13
line.long 0x0 "DMA,Register for controlling DMA."
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
newline
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
newline
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request  also level for threshold status. When RX FIFO has more than this many bytes  the associated events and conditions are triggered."
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
newline
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO  clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
newline
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request  also level for threshold status. When TX FIFO has fewer than this many bytes  the associated events and conditions are triggered."
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun  set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun  set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun  set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun  set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 11. "MST_DONE,Master Done  set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x8 "INTEN,Register for enabling interrupts."
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
newline
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
newline
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
line.long 0x10 "WKEN,Register for wake up enable."
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
newline
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
rgroup.long 0x30++0x3
line.long 0x0 "STAT,SPI Status register."
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode  set when transaction starts  cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode  set when Slave Select is asserted  cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
tree.end
endif
tree.end
tree "TMR (Timers)"
base ad:0x0
tree "TMR"
base ad:0x40010000
group.long 0x0++0x1F
line.long 0x0 "CNT,Timer Counter Register."
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
line.long 0x4 "CMP,Timer Compare Register."
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
line.long 0x8 "PWM,Timer PWM Register."
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
line.long 0xC "INTFL,Timer Interrupt Status Register."
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
line.long 0x10 "CTRL0,Timer Control Register."
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
newline
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
newline
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
line.long 0x18 "CTRL1,Timer Configuration Register."
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0  1 and 5 for Timer A" "0,1"
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
newline
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
line.long 0x1C "WKFL,Timer Wakeup Status Register."
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
tree.end
tree "TMR1"
base ad:0x40011000
group.long 0x0++0x1F
line.long 0x0 "CNT,Timer Counter Register."
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
line.long 0x4 "CMP,Timer Compare Register."
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
line.long 0x8 "PWM,Timer PWM Register."
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
line.long 0xC "INTFL,Timer Interrupt Status Register."
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
line.long 0x10 "CTRL0,Timer Control Register."
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
newline
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
newline
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
line.long 0x18 "CTRL1,Timer Configuration Register."
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0  1 and 5 for Timer A" "0,1"
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
newline
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
line.long 0x1C "WKFL,Timer Wakeup Status Register."
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
tree.end
tree "TMR2"
base ad:0x40012000
group.long 0x0++0x1F
line.long 0x0 "CNT,Timer Counter Register."
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
line.long 0x4 "CMP,Timer Compare Register."
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
line.long 0x8 "PWM,Timer PWM Register."
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
line.long 0xC "INTFL,Timer Interrupt Status Register."
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
line.long 0x10 "CTRL0,Timer Control Register."
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
newline
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
newline
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
line.long 0x18 "CTRL1,Timer Configuration Register."
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0  1 and 5 for Timer A" "0,1"
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
newline
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
line.long 0x1C "WKFL,Timer Wakeup Status Register."
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
tree.end
tree "TMR3"
base ad:0x40013000
group.long 0x0++0x1F
line.long 0x0 "CNT,Timer Counter Register."
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
line.long 0x4 "CMP,Timer Compare Register."
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
line.long 0x8 "PWM,Timer PWM Register."
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
line.long 0xC "INTFL,Timer Interrupt Status Register."
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
line.long 0x10 "CTRL0,Timer Control Register."
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
newline
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
newline
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
line.long 0x18 "CTRL1,Timer Configuration Register."
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0  1 and 5 for Timer A" "0,1"
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
newline
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
line.long 0x1C "WKFL,Timer Wakeup Status Register."
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
tree.end
tree "TMR4"
base ad:0x40080C00
group.long 0x0++0x1F
line.long 0x0 "CNT,Timer Counter Register."
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
line.long 0x4 "CMP,Timer Compare Register."
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
line.long 0x8 "PWM,Timer PWM Register."
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
line.long 0xC "INTFL,Timer Interrupt Status Register."
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
line.long 0x10 "CTRL0,Timer Control Register."
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
newline
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
newline
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
line.long 0x18 "CTRL1,Timer Configuration Register."
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0  1 and 5 for Timer A" "0,1"
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
newline
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
line.long 0x1C "WKFL,Timer Wakeup Status Register."
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
tree.end
tree "TMR5"
base ad:0x40081000
group.long 0x0++0x1F
line.long 0x0 "CNT,Timer Counter Register."
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
line.long 0x4 "CMP,Timer Compare Register."
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
line.long 0x8 "PWM,Timer PWM Register."
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
line.long 0xC "INTFL,Timer Interrupt Status Register."
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
line.long 0x10 "CTRL0,Timer Control Register."
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
newline
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
newline
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
line.long 0x18 "CTRL1,Timer Configuration Register."
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0  1 and 5 for Timer A" "0,1"
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
newline
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
line.long 0x1C "WKFL,Timer Wakeup Status Register."
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
tree.end
tree.end
tree "TRIMSIR (Trim System Initilazation Registers)"
base ad:0x40005400
group.long 0x8++0x3
line.long 0x0 "RTC,RTC Trim System Initialization Register."
bitfld.long 0x0 31. "LOCK,Lock." "0,1"
hexmask.long.byte 0x0 21.--25. 1. "X2TRIM,RTC X2 Trim."
hexmask.long.byte 0x0 16.--20. 1. "X1TRIM,RTC X1 Trim."
rgroup.long 0x34++0x3
line.long 0x0 "SIMO,SIMO Trim System Initialization Register."
bitfld.long 0x0 0.--2. "CLKDIV,SIMO Clock Divide." "0,1,2,3,4,5,6,7"
rgroup.long 0x3C++0x3
line.long 0x0 "IPOLO,IPO Low Trim System Initialization Register."
hexmask.long.byte 0x0 0.--7. 1. "IPO_LIMITLO,IPO Low Limit Trim."
group.long 0x40++0x7
line.long 0x0 "CTRL,Control Trim System Initialization Register."
bitfld.long 0x0 29.--31. "INRO_TRIM,INRO Clock Trim." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24.--25. "INRO_SEL,INRO Clock Select." "0,1,2,3"
hexmask.long.word 0x0 15.--23. 1. "IPO_LIMITHI,IPO High Trim Limit."
hexmask.long.byte 0x0 8.--14. 1. "VDDA_LIMITHI,VDDA High Trim Limit."
hexmask.long.byte 0x0 0.--6. 1. "VDDA_LIMITLO,VDDA Low Trim Limit."
line.long 0x4 "INRO,RTC Trim System Initialization Register."
bitfld.long 0x4 6.--7. "LPCLKSEL,INRO Low Power Mode Clock Select." "0,1,2,3"
bitfld.long 0x4 3.--5. "TRIM30K,INRO 30KHz Trim." "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "TRIM16K,INRO 16KHz Trim." "0,1,2,3,4,5,6,7"
tree.end
tree "TRNG (True Random Number Generator)"
base ad:0x4004D000
group.long 0x0++0x7
line.long 0x0 "CTRL,TRNG Control Register."
bitfld.long 0x0 15. "KEYWIPE,To wipe the Battery Backed key." "0,1"
bitfld.long 0x0 3. "KEYGEN,AES Key Generate. When enabled  the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the.." "0,1"
bitfld.long 0x0 1. "RND_IE,To enable IRQ generation when a new 32-bit Random number is ready." "0: Disable,1: Enable"
line.long 0x4 "STATUS,Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled. read returns 0x0000 0000."
bitfld.long 0x4 0. "RDY,32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1." "0: TRNG Busy,1: 32 bit random data is ready"
rgroup.long 0x8++0x3
line.long 0x0 "DATA,Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled. read returns 0x0000 0000."
hexmask.long 0x0 0.--31. 1. "DATA,Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled  read returns 0x0000 0000."
tree.end
tree "UART (Universal Asynchronous Receiver Transmitter)"
base ad:0x0
tree "UART"
base ad:0x40042000
group.long 0x0++0x3
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
newline
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
newline
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Status register"
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
group.long 0x8++0x1B
line.long 0x0 "INT_EN,Interrupt Enable control register"
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
line.long 0x4 "INT_FL,Interrupt status flags Control register"
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
line.long 0x8 "CLKDIV,Clock Divider register"
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
line.long 0xC "OSR,Over Sampling Rate register"
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
line.long 0x14 "PNR,Pin register"
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1  the RTS IO is set to high level. If set to 0  the RTS IO is set to low level." "0,1"
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
line.long 0x18 "FIFO,FIFO Read/Write register"
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
group.long 0x30++0xB
line.long 0x0 "DMA,DMA Configuration register"
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value  then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value  then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
line.long 0x4 "WKEN,Wake up enable Control register"
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
line.long 0x8 "WKFL,Wake up Flags register"
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
tree.end
tree "UART1"
base ad:0x40043000
group.long 0x0++0x3
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
newline
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
newline
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Status register"
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
group.long 0x8++0x1B
line.long 0x0 "INT_EN,Interrupt Enable control register"
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
line.long 0x4 "INT_FL,Interrupt status flags Control register"
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
line.long 0x8 "CLKDIV,Clock Divider register"
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
line.long 0xC "OSR,Over Sampling Rate register"
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
line.long 0x14 "PNR,Pin register"
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1  the RTS IO is set to high level. If set to 0  the RTS IO is set to low level." "0,1"
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
line.long 0x18 "FIFO,FIFO Read/Write register"
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
group.long 0x30++0xB
line.long 0x0 "DMA,DMA Configuration register"
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value  then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value  then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
line.long 0x4 "WKEN,Wake up enable Control register"
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
line.long 0x8 "WKFL,Wake up Flags register"
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
tree.end
tree "UART2"
base ad:0x40044000
group.long 0x0++0x3
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
newline
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
newline
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Status register"
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
group.long 0x8++0x1B
line.long 0x0 "INT_EN,Interrupt Enable control register"
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
line.long 0x4 "INT_FL,Interrupt status flags Control register"
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
line.long 0x8 "CLKDIV,Clock Divider register"
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
line.long 0xC "OSR,Over Sampling Rate register"
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
line.long 0x14 "PNR,Pin register"
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1  the RTS IO is set to high level. If set to 0  the RTS IO is set to low level." "0,1"
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
line.long 0x18 "FIFO,FIFO Read/Write register"
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
group.long 0x30++0xB
line.long 0x0 "DMA,DMA Configuration register"
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value  then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value  then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
line.long 0x4 "WKEN,Wake up enable Control register"
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
line.long 0x8 "WKFL,Wake up Flags register"
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
tree.end
tree "UART3"
base ad:0x40081400
group.long 0x0++0x3
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
newline
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
newline
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Status register"
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
group.long 0x8++0x1B
line.long 0x0 "INT_EN,Interrupt Enable control register"
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
line.long 0x4 "INT_FL,Interrupt status flags Control register"
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
line.long 0x8 "CLKDIV,Clock Divider register"
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
line.long 0xC "OSR,Over Sampling Rate register"
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
line.long 0x14 "PNR,Pin register"
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1  the RTS IO is set to high level. If set to 0  the RTS IO is set to low level." "0,1"
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
line.long 0x18 "FIFO,FIFO Read/Write register"
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
group.long 0x30++0xB
line.long 0x0 "DMA,DMA Configuration register"
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value  then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value  then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
line.long 0x4 "WKEN,Wake up enable Control register"
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
line.long 0x8 "WKFL,Wake up Flags register"
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
tree.end
tree.end
sif (cpuis("MAX78002"))
tree "USBHS (USB 2.0 High-Speed Controller)"
base ad:0x400B1000
group.byte 0x0++0x1
line.byte 0x0 "FADDR,Function address register."
rbitfld.byte 0x0 7. "UPDATE,Set when ADDR is written  cleared when new address takes effect." "0,1"
newline
hexmask.byte 0x0 0.--6. 1. "ADDR,Function address for this controller."
line.byte 0x1 "POWER,Power management register."
bitfld.byte 0x1 7. "ISO_UPDATE,Wait for SOF during Isochronous xfers." "0,1"
newline
bitfld.byte 0x1 6. "SOFTCONN,Softconn." "0,1"
newline
bitfld.byte 0x1 5. "HS_ENABLE,High-speed mode enable." "0,1"
newline
rbitfld.byte 0x1 4. "HS_MODE,High-speed mode detected." "0,1"
newline
rbitfld.byte 0x1 3. "RESET,Bus reset detected." "0,1"
newline
bitfld.byte 0x1 2. "RESUME,Generate resume signaling." "0,1"
newline
rbitfld.byte 0x1 1. "SUSPEND,Suspend mode detected." "0,1"
newline
bitfld.byte 0x1 0. "EN_SUSPENDM,Enable SUSPENDM signal." "0,1"
rgroup.word 0x2++0x3
line.word 0x0 "INTRIN,Interrupt register for EP0 and IN EP1-15."
bitfld.word 0x0 15. "EP15_IN_INT,Endpoint 15 interrupt." "0,1"
newline
bitfld.word 0x0 14. "EP14_IN_INT,Endpoint 14 interrupt." "0,1"
newline
bitfld.word 0x0 13. "EP13_IN_INT,Endpoint 13 interrupt." "0,1"
newline
bitfld.word 0x0 12. "EP12_IN_INT,Endpoint 12 interrupt." "0,1"
newline
bitfld.word 0x0 11. "EP11_IN_INT,Endpoint 11 interrupt." "0,1"
newline
bitfld.word 0x0 10. "EP10_IN_INT,Endpoint 10 interrupt." "0,1"
newline
bitfld.word 0x0 9. "EP9_IN_INT,Endpoint 9 interrupt." "0,1"
newline
bitfld.word 0x0 8. "EP8_IN_INT,Endpoint 8 interrupt." "0,1"
newline
bitfld.word 0x0 7. "EP7_IN_INT,Endpoint 7 interrupt." "0,1"
newline
bitfld.word 0x0 6. "EP6_IN_INT,Endpoint 6 interrupt." "0,1"
newline
bitfld.word 0x0 5. "EP5_IN_INT,Endpoint 5 interrupt." "0,1"
newline
bitfld.word 0x0 4. "EP4_IN_INT,Endpoint 4 interrupt." "0,1"
newline
bitfld.word 0x0 3. "EP3_IN_INT,Endpoint 3 interrupt." "0,1"
newline
bitfld.word 0x0 2. "EP2_IN_INT,Endpoint 2 interrupt." "0,1"
newline
bitfld.word 0x0 1. "EP1_IN_INT,Endpoint 1 interrupt." "0,1"
newline
bitfld.word 0x0 0. "EP0_IN_INT,Endpoint 0 interrupt." "0,1"
line.word 0x2 "INTROUT,Interrupt register for OUT EP 1-15."
bitfld.word 0x2 15. "EP15_OUT_INT,Endpoint 15 interrupt." "0,1"
newline
bitfld.word 0x2 14. "EP14_OUT_INT,Endpoint 14 interrupt." "0,1"
newline
bitfld.word 0x2 13. "EP13_OUT_INT,Endpoint 13 interrupt." "0,1"
newline
bitfld.word 0x2 12. "EP12_OUT_INT,Endpoint 12 interrupt." "0,1"
newline
bitfld.word 0x2 11. "EP11_OUT_INT,Endpoint 11 interrupt." "0,1"
newline
bitfld.word 0x2 10. "EP10_OUT_INT,Endpoint 10 interrupt." "0,1"
newline
bitfld.word 0x2 9. "EP9_OUT_INT,Endpoint 9 interrupt." "0,1"
newline
bitfld.word 0x2 8. "EP8_OUT_INT,Endpoint 8 interrupt." "0,1"
newline
bitfld.word 0x2 7. "EP7_OUT_INT,Endpoint 7 interrupt." "0,1"
newline
bitfld.word 0x2 6. "EP6_OUT_INT,Endpoint 6 interrupt." "0,1"
newline
bitfld.word 0x2 5. "EP5_OUT_INT,Endpoint 5 interrupt." "0,1"
newline
bitfld.word 0x2 4. "EP4_OUT_INT,Endpoint 4 interrupt." "0,1"
newline
bitfld.word 0x2 3. "EP3_OUT_INT,Endpoint 3 interrupt." "0,1"
newline
bitfld.word 0x2 2. "EP2_OUT_INT,Endpoint 2 interrupt." "0,1"
newline
bitfld.word 0x2 1. "EP1_OUT_INT,Endpoint 1 interrupt." "0,1"
group.word 0x6++0x3
line.word 0x0 "INTRINEN,Interrupt enable for EP 0 and IN EP 1-15."
bitfld.word 0x0 15. "EP15_IN_INT_EN,Endpoint 15 interrupt enable." "0,1"
newline
bitfld.word 0x0 14. "EP14_IN_INT_EN,Endpoint 14 interrupt enable." "0,1"
newline
bitfld.word 0x0 13. "EP13_IN_INT_EN,Endpoint 13 interrupt enable." "0,1"
newline
bitfld.word 0x0 12. "EP12_IN_INT_EN,Endpoint 12 interrupt enable." "0,1"
newline
bitfld.word 0x0 11. "EP11_IN_INT_EN,Endpoint 11 interrupt enable." "0,1"
newline
bitfld.word 0x0 10. "EP10_IN_INT_EN,Endpoint 10 interrupt enable." "0,1"
newline
bitfld.word 0x0 9. "EP9_IN_INT_EN,Endpoint 9 interrupt enable." "0,1"
newline
bitfld.word 0x0 8. "EP8_IN_INT_EN,Endpoint 8 interrupt enable." "0,1"
newline
bitfld.word 0x0 7. "EP7_IN_INT_EN,Endpoint 7 interrupt enable." "0,1"
newline
bitfld.word 0x0 6. "EP6_IN_INT_EN,Endpoint 6 interrupt enable." "0,1"
newline
bitfld.word 0x0 5. "EP5_IN_INT_EN,Endpoint 5 interrupt enable." "0,1"
newline
bitfld.word 0x0 4. "EP4_IN_INT_EN,Endpoint 4 interrupt enable." "0,1"
newline
bitfld.word 0x0 3. "EP3_IN_INT_EN,Endpoint 3 interrupt enable." "0,1"
newline
bitfld.word 0x0 2. "EP2_IN_INT_EN,Endpoint 2 interrupt enable." "0,1"
newline
bitfld.word 0x0 1. "EP1_IN_INT_EN,Endpoint 1 interrupt enable." "0,1"
newline
bitfld.word 0x0 0. "EP0_INT_EN,Endpoint 0 interrupt enable." "0,1"
line.word 0x2 "INTROUTEN,Interrupt enable for OUT EP 1-15."
bitfld.word 0x2 15. "EP15_OUT_INT_EN,Endpoint 15 interrupt." "0,1"
newline
bitfld.word 0x2 14. "EP14_OUT_INT_EN,Endpoint 14 interrupt." "0,1"
newline
bitfld.word 0x2 13. "EP13_OUT_INT_EN,Endpoint 13 interrupt." "0,1"
newline
bitfld.word 0x2 12. "EP12_OUT_INT_EN,Endpoint 12 interrupt." "0,1"
newline
bitfld.word 0x2 11. "EP11_OUT_INT_EN,Endpoint 11 interrupt." "0,1"
newline
bitfld.word 0x2 10. "EP10_OUT_INT_EN,Endpoint 10 interrupt." "0,1"
newline
bitfld.word 0x2 9. "EP9_OUT_INT_EN,Endpoint 9 interrupt." "0,1"
newline
bitfld.word 0x2 8. "EP8_OUT_INT_EN,Endpoint 8 interrupt." "0,1"
newline
bitfld.word 0x2 7. "EP7_OUT_INT_EN,Endpoint 7 interrupt." "0,1"
newline
bitfld.word 0x2 6. "EP6_OUT_INT_EN,Endpoint 6 interrupt." "0,1"
newline
bitfld.word 0x2 5. "EP5_OUT_INT_EN,Endpoint 5 interrupt." "0,1"
newline
bitfld.word 0x2 4. "EP4_OUT_INT_EN,Endpoint 4 interrupt." "0,1"
newline
bitfld.word 0x2 3. "EP3_OUT_INT_EN,Endpoint 3 interrupt." "0,1"
newline
bitfld.word 0x2 2. "EP2_OUT_INT_EN,Endpoint 2 interrupt." "0,1"
newline
bitfld.word 0x2 1. "EP1_OUT_INT_EN,Endpoint 1 interrupt." "0,1"
rgroup.byte 0xA++0x0
line.byte 0x0 "INTRUSB,Interrupt register for common USB interrupts."
bitfld.byte 0x0 3. "SOF_INT,Start of Frame." "0,1"
newline
bitfld.byte 0x0 2. "RESET_INT,Bus reset detected." "0,1"
newline
bitfld.byte 0x0 1. "RESUME_INT,Resume detected." "0,1"
newline
bitfld.byte 0x0 0. "SUSPEND_INT,Suspend detected." "0,1"
group.byte 0xB++0x0
line.byte 0x0 "INTRUSBEN,Interrupt enable for common USB interrupts."
bitfld.byte 0x0 3. "SOF_INT_EN,Start of Frame." "0,1"
newline
bitfld.byte 0x0 2. "RESET_INT_EN,Bus reset detected." "0,1"
newline
bitfld.byte 0x0 1. "RESUME_INT_EN,Resume detected." "0,1"
newline
bitfld.byte 0x0 0. "SUSPEND_INT_EN,Suspend detected." "0,1"
rgroup.word 0xC++0x1
line.word 0x0 "FRAME,Frame number."
hexmask.word 0x0 0.--10. 1. "FRAMENUM,Read the last received frame number  that is the 11-bit frame number received in the SOF packet."
group.byte 0xE++0x1
line.byte 0x0 "INDEX,Index for banked registers."
hexmask.byte 0x0 0.--3. 1. "INDEX,Index Register Access Selector."
line.byte 0x1 "TESTMODE,USB 2.0 test mode enable register."
bitfld.byte 0x1 5. "FORCE_FS,Force USB to Full-speed after reset." "0,1"
newline
bitfld.byte 0x1 4. "FORCE_HS,Force USB to High-speed after reset." "0,1"
newline
bitfld.byte 0x1 3. "TEST_PKT,Transmit fixed test packet." "0,1"
newline
bitfld.byte 0x1 2. "TEST_K,Force USB to continuous K state." "0,1"
newline
bitfld.byte 0x1 1. "TEST_J,Force USB to continuous J state." "0,1"
newline
bitfld.byte 0x1 0. "TEST_SE0_NAK,Respond to any valid IN token with NAK." "0,1"
group.word 0x10++0x1
line.word 0x0 "INMAXP,Maximum packet size for INx endpoint (x == INDEX)."
hexmask.word.byte 0x0 11.--15. 1. "NUMPACKMINUS1,Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk.."
newline
hexmask.word 0x0 0.--10. 1. "MAXPACKETSIZE,Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes  that is transmitted for each microframe. The maximum value is 1024  subject to the limitations of the endpoint type set in USB 2.0 Specification  Chapter 9"
group.byte 0x12++0x0
line.byte 0x0 "CSR0,Control status register for EP 0 (when INDEX == 0)."
bitfld.byte 0x0 7. "SERV_SETUP_END,Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set" "0,1"
newline
bitfld.byte 0x0 6. "SERV_OUTPKTRDY,Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set." "0,1"
newline
bitfld.byte 0x0 5. "SEND_STALL,Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set." "0,1"
newline
rbitfld.byte 0x0 4. "SETUP_END,Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear." "0,1"
newline
bitfld.byte 0x0 3. "DATA_END,Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after.." "0,1"
newline
bitfld.byte 0x0 2. "SENT_STALL,Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear." "0,1"
newline
bitfld.byte 0x0 1. "INPKTRDY,EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared." "?,1: Write a 1 after writing a data packet to the IN.."
newline
rbitfld.byte 0x0 0. "OUTPKTRDY,EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO." "0,1"
group.byte 0x12++0x1
line.byte 0x0 "INCSRL,Control status lower register for INx endpoint (x == INDEX)."
bitfld.byte 0x0 7. "INCOMPTX,Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from.." "0,1"
newline
bitfld.byte 0x0 6. "CLRDATATOG,Write 1 to clear IN endpoint data-toggle to 0." "0,1"
newline
bitfld.byte 0x0 5. "SENTSTALL,Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted  at which time the IN FIFO is flushed  and inpktrdy is cleared. Write 0 to clear." "0,1"
newline
rbitfld.byte 0x0 4. "SENDSTALL,Send STALL Handshake." "0: Terminate STALL handhsake,1: Respond to an IN token with a STALL handshake"
newline
bitfld.byte 0x0 3. "FLUSHFIFO,Flush Next Packet from IN FIFO. Write 1 to clear" "0,1"
newline
bitfld.byte 0x0 2. "UNDERRUN,Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear" "0,1"
newline
bitfld.byte 0x0 1. "FIFONOTEMPTY,Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear." "0,1"
newline
rbitfld.byte 0x0 0. "INPKTRDY,IN Packet Ready. Write a 1 to clear" "0,1"
line.byte 0x1 "INCSRU,Control status upper register for INx endpoint (x == INDEX)."
bitfld.byte 0x1 7. "AUTOSET,Auto Set inpktrdy." "0: USBHS_INCSRL_inpktrdy must be set by firmware.,1: USBHS_INCSRL_inpktrdy is automatically set."
newline
bitfld.byte 0x1 6. "ISO,Isochronous Transfer Enable" "0: Enable IN Bulk and IN interrupt transfers.,1: Enable IN Isochronous transfers."
newline
bitfld.byte 0x1 5. "MODE,Endpoint Direction Mode." "0: Endpoint direction is OUT.,1: Endpoint direction is IN."
newline
bitfld.byte 0x1 3. "FRCDATATOG,Force In Data - Toggle" "0: Toggle data-toglge only when an ACK is received.,1: Toggle data-toggle regardless of ACK."
newline
bitfld.byte 0x1 1. "DPKTBUFDIS,Double Packet Buffering Disable" "0: Enable Double packet buffering.,1: Disable Double Packet Buffering."
group.word 0x14++0x1
line.word 0x0 "OUTMAXP,Maximum packet size for OUTx endpoint (x == INDEX)."
hexmask.word.byte 0x0 11.--15. 1. "NUMPACKMINUS1,Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize."
newline
hexmask.word 0x0 0.--10. 1. "MAXPACKETSIZE,Maximum Packet in a Single Transaction. This is the maximum packet size  in bytes  that is transmitted for each microframe. The maximum value is 1024  subject to the limitations for the endpoint type set in USB2.0 spesification  chapter 9."
group.byte 0x16++0x1
line.byte 0x0 "OUTCSRL,Control status lower register for OUTx endpoint (x == INDEX)."
bitfld.byte 0x0 7. "CLRDATATOG," "0,1"
newline
bitfld.byte 0x0 6. "SENTSTALL," "0,1"
newline
bitfld.byte 0x0 5. "SENDSTALL," "0,1"
newline
bitfld.byte 0x0 4. "FLUSHFIFO," "0,1"
newline
rbitfld.byte 0x0 3. "DATAERROR," "0,1"
newline
bitfld.byte 0x0 2. "OVERRUN," "0,1"
newline
rbitfld.byte 0x0 1. "FIFOFULL," "0,1"
newline
bitfld.byte 0x0 0. "OUTPKTRDY," "0,1"
line.byte 0x1 "OUTCSRU,Control status upper register for OUTx endpoint (x == INDEX)."
bitfld.byte 0x1 7. "AUTOCLEAR," "0,1"
newline
bitfld.byte 0x1 6. "ISO," "0,1"
newline
bitfld.byte 0x1 4. "DISNYET," "0,1"
newline
bitfld.byte 0x1 1. "DPKTBUFDIS," "0,1"
newline
rbitfld.byte 0x1 0. "INCOMPRX," "0,1"
rgroup.word 0x18++0x1
line.word 0x0 "COUNT0,Number of received bytes in EP 0 FIFO (INDEX == 0)."
hexmask.word.byte 0x0 0.--6. 1. "COUNT0,Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1"
rgroup.word 0x18++0x1
line.word 0x0 "OUTCOUNT,Number of received bytes in OUT EPx FIFO (x == INDEX)."
hexmask.word 0x0 0.--12. 1. "OUTCOUNT,Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO."
group.long 0x20++0x3F
line.long 0x0 "FIFO0,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x0 0.--31. 1. "USBHS_FIFO0,USBHS Endpoint FIFO Read/Write Register."
line.long 0x4 "FIFO1,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x4 0.--31. 1. "USBHS_FIFO1,USBHS Endpoint FIFO Read/Write Register."
line.long 0x8 "FIFO2,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x8 0.--31. 1. "USBHS_FIFO2,USBHS Endpoint FIFO Read/Write Register."
line.long 0xC "FIFO3,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0xC 0.--31. 1. "USBHS_FIFO3,USBHS Endpoint FIFO Read/Write Register."
line.long 0x10 "FIFO4,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x10 0.--31. 1. "USBHS_FIFO4,USBHS Endpoint FIFO Read/Write Register."
line.long 0x14 "FIFO5,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x14 0.--31. 1. "USBHS_FIFO5,USBHS Endpoint FIFO Read/Write Register."
line.long 0x18 "FIFO6,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x18 0.--31. 1. "USBHS_FIFO6,USBHS Endpoint FIFO Read/Write Register."
line.long 0x1C "FIFO7,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x1C 0.--31. 1. "USBHS_FIFO7,USBHS Endpoint FIFO Read/Write Register."
line.long 0x20 "FIFO8,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x20 0.--31. 1. "USBHS_FIFO8,USBHS Endpoint FIFO Read/Write Register."
line.long 0x24 "FIFO9,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x24 0.--31. 1. "USBHS_FIFO9,USBHS Endpoint FIFO Read/Write Register."
line.long 0x28 "FIFO10,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x28 0.--31. 1. "USBHS_FIFO10,USBHS Endpoint FIFO Read/Write Register."
line.long 0x2C "FIFO11,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x2C 0.--31. 1. "USBHS_FIFO11,USBHS Endpoint FIFO Read/Write Register."
line.long 0x30 "FIFO12,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x30 0.--31. 1. "USBHS_FIFO12,USBHS Endpoint FIFO Read/Write Register."
line.long 0x34 "FIFO13,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x34 0.--31. 1. "USBHS_FIFO13,USBHS Endpoint FIFO Read/Write Register."
line.long 0x38 "FIFO14,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x38 0.--31. 1. "USBHS_FIFO14,USBHS Endpoint FIFO Read/Write Register."
line.long 0x3C "FIFO15,Read for OUT data FIFO. write for IN data FIFO."
hexmask.long 0x3C 0.--31. 1. "USBHS_FIFO15,USBHS Endpoint FIFO Read/Write Register."
group.word 0x6C++0x1
line.word 0x0 "HWVERS,HWVERS"
hexmask.word 0x0 0.--15. 1. "USBHS_HWVERS,USBHS Register."
rgroup.byte 0x78++0x1
line.byte 0x0 "EPINFO,Endpoint hardware information."
hexmask.byte 0x0 4.--7. 1. "OUTENDPOINTS,"
newline
hexmask.byte 0x0 0.--3. 1. "INTENDPOINTS,"
line.byte 0x1 "RAMINFO,RAM width information."
hexmask.byte 0x1 0.--3. 1. "RAMBITS,"
group.byte 0x7A++0x0
line.byte 0x0 "SOFTRESET,Software reset register."
bitfld.byte 0x0 1. "RSTXS," "0,1"
newline
bitfld.byte 0x0 0. "RSTS," "0,1"
group.word 0x80++0x3
line.word 0x0 "CTUCH,Chirp timeout timer setting."
hexmask.word 0x0 0.--15. 1. "C_T_UCH,HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host."
line.word 0x2 "CTHSRTN,Sets delay between HS resume to UTM normal operating mode."
hexmask.word 0x2 0.--15. 1. "C_T_HSTRN,High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends  the when the USBHS resumes normal operation."
group.long 0x400++0x1B
line.long 0x0 "MXM_USB_REG_00,MXM_USB_REG_00"
line.long 0x4 "M31_PHY_UTMI_RESET,M31_PHY_UTMI_RESET"
line.long 0x8 "M31_PHY_UTMI_VCONTROL,M31_PHY_UTMI_VCONTROL"
line.long 0xC "M31_PHY_CLK_EN,M31_PHY_CLK_EN"
line.long 0x10 "M31_PHY_PONRST,M31_PHY_PONRST"
line.long 0x14 "M31_PHY_NONCRY_RSTB,M31_PHY_NONCRY_RSTB"
line.long 0x18 "M31_PHY_NONCRY_EN,M31_PHY_NONCRY_EN"
group.long 0x420++0x87
line.long 0x0 "M31_PHY_U2_COMPLIANCE_EN,M31_PHY_U2_COMPLIANCE_EN"
line.long 0x4 "M31_PHY_U2_COMPLIANCE_DAC_ADJ,M31_PHY_U2_COMPLIANCE_DAC_ADJ"
line.long 0x8 "M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN,M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN"
line.long 0xC "M31_PHY_CLK_RDY,M31_PHY_CLK_RDY"
line.long 0x10 "M31_PHY_PLL_EN,M31_PHY_PLL_EN"
line.long 0x14 "M31_PHY_BIST_OK,M31_PHY_BIST_OK"
line.long 0x18 "M31_PHY_DATA_OE,M31_PHY_DATA_OE"
line.long 0x1C "M31_PHY_OSCOUTEN,M31_PHY_OSCOUTEN"
line.long 0x20 "M31_PHY_LPM_ALIVE,M31_PHY_LPM_ALIVE"
line.long 0x24 "M31_PHY_HS_BIST_MODE,M31_PHY_HS_BIST_MODE"
line.long 0x28 "M31_PHY_CORECLKIN,M31_PHY_CORECLKIN"
line.long 0x2C "M31_PHY_XTLSEL,M31_PHY_XTLSEL"
line.long 0x30 "M31_PHY_LS_EN,M31_PHY_LS_EN"
line.long 0x34 "M31_PHY_DEBUG_SEL,M31_PHY_DEBUG_SEL"
line.long 0x38 "M31_PHY_DEBUG_OUT,M31_PHY_DEBUG_OUT"
line.long 0x3C "M31_PHY_OUTCLKSEL,M31_PHY_OUTCLKSEL"
line.long 0x40 "M31_PHY_XCFGI_31_0,M31_PHY_XCFGI_31_0"
line.long 0x44 "M31_PHY_XCFGI_63_32,M31_PHY_XCFGI_63_32"
line.long 0x48 "M31_PHY_XCFGI_95_64,M31_PHY_XCFGI_95_64"
line.long 0x4C "M31_PHY_XCFGI_127_96,M31_PHY_XCFGI_127_96"
line.long 0x50 "M31_PHY_XCFGI_137_128,M31_PHY_XCFGI_137_128"
line.long 0x54 "M31_PHY_XCFG_HS_COARSE_TUNE_NUM,M31_PHY_XCFG_HS_COARSE_TUNE_NUM"
line.long 0x58 "M31_PHY_XCFG_HS_FINE_TUNE_NUM,M31_PHY_XCFG_HS_FINE_TUNE_NUM"
line.long 0x5C "M31_PHY_XCFG_FS_COARSE_TUNE_NUM,M31_PHY_XCFG_FS_COARSE_TUNE_NUM"
line.long 0x60 "M31_PHY_XCFG_FS_FINE_TUNE_NUM,M31_PHY_XCFG_FS_FINE_TUNE_NUM"
line.long 0x64 "M31_PHY_XCFG_LOCK_RANGE_MAX,M31_PHY_XCFG_LOCK_RANGE_MAX"
line.long 0x68 "M31_PHY_XCFGI_LOCK_RANGE_MIN,M31_PHY_XCFGI_LOCK_RANGE_MIN"
line.long 0x6C "M31_PHY_XCFG_OB_RSEL,M31_PHY_XCFG_OB_RSEL"
line.long 0x70 "M31_PHY_XCFG_OC_RSEL,M31_PHY_XCFG_OC_RSEL"
line.long 0x74 "M31_PHY_XCFGO,M31_PHY_XCFGO"
line.long 0x78 "MXM_INT,USB Added Maxim Interrupt Flag Register."
bitfld.long 0x78 1. "NOVBUS,NOVBUS" "0,1"
newline
bitfld.long 0x78 0. "VBUS,VBUS" "0,1"
line.long 0x7C "MXM_INT_EN,USB Added Maxim Interrupt Enable Register."
bitfld.long 0x7C 1. "NOVBUS,NOVBUS" "0,1"
newline
bitfld.long 0x7C 0. "VBUS,VBUS" "0,1"
line.long 0x80 "MXM_SUSPEND,USB Added Maxim Suspend Register."
bitfld.long 0x80 0. "SEL,Suspend register" "0,1"
line.long 0x84 "MXM_REG_A4,USB Added Maxim Power Status Register"
bitfld.long 0x84 0. "VRST_VDDB_N_A,VRST_VDDB_N_A" "0,1"
tree.end
endif
tree "WDT (Watchdog Timer)"
base ad:0x0
tree "WDT"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CTRL,Watchdog Timer Control Register."
bitfld.long 0x0 31. "RST_LATE,Windowed Watchdog Timer Reset Flag Too Late." "0: The event has not occurred.,1: The event has occurred."
bitfld.long 0x0 30. "RST_EARLY,Windowed Watchdog Timer Reset Flag Too Soon." "0: The event has not occurred.,1: The event has occurred."
newline
bitfld.long 0x0 29. "WIN_EN,Enables the Windowed Watchdog Function." "0: Windowed Mode Disabled (i.e. Compatibility Mode).,1: Windowed Mode Enabled."
bitfld.long 0x0 28. "CLKRDY,Clock Status." "0,1"
newline
bitfld.long 0x0 27. "CLKRDY_IE,Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock." "0,1"
hexmask.long.byte 0x0 20.--23. 1. "RST_EARLY_VAL,Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST.."
newline
hexmask.long.byte 0x0 16.--19. 1. "INT_EARLY_VAL,Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog.."
bitfld.long 0x0 12. "INT_EARLY,Windowed Watchdog Timer Interrupt Flag Too Soon." "0: No interrupt is pending.,1: An interrupt is pending."
newline
bitfld.long 0x0 11. "WDT_RST_EN,Windowed Watchdog Timer Reset Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 10. "WDT_INT_EN,Windowed Watchdog Timer Interrupt Enable." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 9. "INT_LATE,Windowed Watchdog Timer Interrupt Flag Too Late." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 8. "EN,Windowed Watchdog Timer Enable." "0: Disable.,1: Enable."
newline
hexmask.long.byte 0x0 4.--7. 1. "RST_LATE_VAL,Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time.."
hexmask.long.byte 0x0 0.--3. 1. "INT_LATE_VAL,Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the.."
wgroup.long 0x4++0x3
line.long 0x0 "RST,Windowed Watchdog Timer Reset Register."
hexmask.long.byte 0x0 0.--7. 1. "RESET,Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur  if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT.."
group.long 0x8++0x3
line.long 0x0 "CLKSEL,Windowed Watchdog Timer Clock Select Register."
bitfld.long 0x0 0.--2. "SOURCE,WWDT Clock Selection Register." "0,1,2,3,4,5,6,7"
rgroup.long 0xC++0x3
line.long 0x0 "CNT,Windowed Watchdog Timer Count Register."
hexmask.long 0x0 0.--31. 1. "COUNT,Current Value of the Windowed Watchdog Timer Counter."
tree.end
tree "WDT1"
base ad:0x40080800
group.long 0x0++0x3
line.long 0x0 "CTRL,Watchdog Timer Control Register."
bitfld.long 0x0 31. "RST_LATE,Windowed Watchdog Timer Reset Flag Too Late." "0: The event has not occurred.,1: The event has occurred."
bitfld.long 0x0 30. "RST_EARLY,Windowed Watchdog Timer Reset Flag Too Soon." "0: The event has not occurred.,1: The event has occurred."
newline
bitfld.long 0x0 29. "WIN_EN,Enables the Windowed Watchdog Function." "0: Windowed Mode Disabled (i.e. Compatibility Mode).,1: Windowed Mode Enabled."
bitfld.long 0x0 28. "CLKRDY,Clock Status." "0,1"
newline
bitfld.long 0x0 27. "CLKRDY_IE,Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock." "0,1"
hexmask.long.byte 0x0 20.--23. 1. "RST_EARLY_VAL,Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST.."
newline
hexmask.long.byte 0x0 16.--19. 1. "INT_EARLY_VAL,Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog.."
bitfld.long 0x0 12. "INT_EARLY,Windowed Watchdog Timer Interrupt Flag Too Soon." "0: No interrupt is pending.,1: An interrupt is pending."
newline
bitfld.long 0x0 11. "WDT_RST_EN,Windowed Watchdog Timer Reset Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 10. "WDT_INT_EN,Windowed Watchdog Timer Interrupt Enable." "0: Disable.,1: Enable."
newline
bitfld.long 0x0 9. "INT_LATE,Windowed Watchdog Timer Interrupt Flag Too Late." "0: No interrupt is pending.,1: An interrupt is pending."
bitfld.long 0x0 8. "EN,Windowed Watchdog Timer Enable." "0: Disable.,1: Enable."
newline
hexmask.long.byte 0x0 4.--7. 1. "RST_LATE_VAL,Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time.."
hexmask.long.byte 0x0 0.--3. 1. "INT_LATE_VAL,Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the.."
wgroup.long 0x4++0x3
line.long 0x0 "RST,Windowed Watchdog Timer Reset Register."
hexmask.long.byte 0x0 0.--7. 1. "RESET,Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur  if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT.."
group.long 0x8++0x3
line.long 0x0 "CLKSEL,Windowed Watchdog Timer Clock Select Register."
bitfld.long 0x0 0.--2. "SOURCE,WWDT Clock Selection Register." "0,1,2,3,4,5,6,7"
rgroup.long 0xC++0x3
line.long 0x0 "CNT,Windowed Watchdog Timer Count Register."
hexmask.long 0x0 0.--31. 1. "COUNT,Current Value of the Windowed Watchdog Timer Counter."
tree.end
tree.end
tree "WUT (Wake-Up Timer)"
base ad:0x40006400
group.long 0x0++0x7
line.long 0x0 "CNT,Count. This register stores the current timer count."
hexmask.long 0x0 0.--31. 1. "COUNT,Timer Count Value."
line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001."
hexmask.long 0x4 0.--31. 1. "COMPARE,Timer Compare Value."
sif (cpuis("MAX78000"))
group.long 0xC++0x3
line.long 0x0 "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt."
bitfld.long 0x0 0. "IRQ_CLR,Clear Interrupt." "0,1"
endif
sif (cpuis("MAX78002"))
group.long 0xC++0x3
line.long 0x0 "INTFL,Wakeup Timer Interrupt Register"
bitfld.long 0x0 0. "IRQ_CLR,Timer Interrupt." "0,1"
endif
group.long 0x10++0x13
line.long 0x0 "CTRL,Timer Control Register."
sif (cpuis("MAX78000"))
bitfld.long 0x0 8. "PRES3,MSB of prescaler value." "0,1"
bitfld.long 0x0 7. "TEN,Timer Enable." "0: Disable.,1: Enable."
bitfld.long 0x0 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low."
bitfld.long 0x0 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock  F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128."
bitfld.long 0x0 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,?,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode."
newline
endif
sif (cpuis("MAX78002"))
bitfld.long 0x0 8. "PRES3,Timer Prescaler Select." "0,1"
bitfld.long 0x0 7. "TEN,Timer Enable." "0,1"
bitfld.long 0x0 6. "TPOL,Timer pOLARITY." "0,1"
bitfld.long 0x0 3.--5. "PRES,Timer Prescaler Select." "0,1,2,3,4,5,6,7"
endif
line.long 0x4 "NOLCMP,Timer Non-Overlapping Compare Register."
hexmask.long.byte 0x4 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A."
hexmask.long.byte 0x4 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'."
line.long 0x8 "PRESET,Preset register."
hexmask.long 0x8 0.--31. 1. "PRESET,Preset Value."
line.long 0xC "RELOAD,Reload register."
hexmask.long 0xC 0.--31. 1. "RELOAD,Rerload Value."
line.long 0x10 "SNAPSHOT,Snapshot register."
hexmask.long 0x10 0.--31. 1. "SNAPSHOT,Snapshot Value."
tree.end
AUTOINDENT.OFF