; -------------------------------------------------------------------------------- ; @Title: LPC3130/31 On-Chip Peripherals ; @Props: Released ; @Author: BOB ; @Changelog: 2009-09-04 BOB ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: UM10314_1.pdf Rev. 1 (2009-03-04) ; @Core: ARM926EJ-S ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perlpc313x.per 7592 2017-02-18 13:54:14Z askoncej $ config 16. 8. width 0xb tree "ARM Core Registers" AUTOINDENT.PUSH AUTOINDENT.OFF width 8. tree "ID Registers" group c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision" group c15:0x0100--0x0100 line.long 0x0 "CTR,Cache Type" bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f" bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes" textline " " bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..." bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1" bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16" textline " " bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..." bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1" bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16" group c15:0x0200--0x0200 line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register" bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes" bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes" tree.end tree "MMU Control and Configuration" width 8. group c15:0x0001--0x0001 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable" bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable" bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable" bitfld.long 0x0 7. " B ,Endianism" "Little,Big" textline " " bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable" bitfld.long 0x0 0. " M ,MMU" "Disable,Enable" textline " " group c15:0x0002--0x0002 line.long 0x0 "TTBR,Translation Table Base Register" hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address" textline " " group c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group c15:0x0005--0x0005 line.long 0x0 "DFSR,Data Fault Status Register" bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page" group c15:0x0105--0x0105 line.long 0x0 "IFSR,Instruction Fault Status Register" bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page" group c15:0x0006--0x0006 line.long 0x0 "DFAR,Data Fault Address Register" textline " " group c15:0x000a--0x000a line.long 0x0 "TLBR,TLB Lockdown Register" bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. " P ,P bit" "0,1" textline " " group c15:0x000d--0x000d line.long 0x0 "FCSEPID,FCSE Process ID" group c15:0x010d--0x010d line.long 0x0 "CONTEXT,Context ID" tree.end tree "Cache Control and Configuration" group c15:0x0009--0x0009 line.long 0x0 "DCACHE,Data Cache Lockdown" bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1" bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1" bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1" bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1" group c15:0x0109--0x0109 line.long 0x0 "ICACHE,Instruction Cache Lockdown" bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1" bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1" bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1" bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1" tree.end tree "TCM Control and Configuration" group c15:0x0019--0x0019 line.long 0x0 "DTCM,Data TCM Region Register" hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address" bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res" bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable" group c15:0x0119--0x0119 line.long 0x0 "ITCM,Instruction TCM Region Register" hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address" bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res" bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable" tree.end tree "Test and Debug" group c15:0x000f--0x000f line.long 0x0 "DOVRR,Debug Override Register" bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable" bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort" bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort" textline " " bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable" bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable" bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable" bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT" group c15:0x001f--0x001f line.long 0x0 "ADDRESS,Debug/Test Address" ;wgroup c15:0x402f--0x402f ; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry" ;wgroup c15:0x403f--0x403f ; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry" ;wgroup c15:0x404f--0x404f ; line.long 0x0 "RMTLBPA,Read PA in main TLB entry" ;wgroup c15:0x405f--0x405f ; line.long 0x0 "WMTLBPA,Write PA in main TLB entry" ;wgroup c15:0x407f--0x407f ; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM" ;wgroup c15:0x412f--0x412f ; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry" ;wgroup c15:0x413f--0x413f ; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry" ;wgroup c15:0x414f--0x414f ; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry" ;wgroup c15:0x415f--0x415f ; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry" ;wgroup c15:0x417f--0x417f ; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM" group c15:0x101f--0x101f line.long 0x0 "TRACE,Trace Control" bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall" bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall" group c15:0x700f--0x700f line.long 0x0 "CACHE,Cache Debug Control" bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through" bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable" bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable" group c15:0x701f--0x701f line.long 0x0 "MMU,MMU Debug Control" bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable" bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable" bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable" bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable" textline " " bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable" bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable" bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable" bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable" group c15:0x002f--0x002f line.long 0x0 "REMAP,Memory Region Remap" bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB" bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB" textline " " bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB" bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB" tree.end tree "ICEbreaker" width 8. group ice:0x0--0x5 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled" textline " " bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled" bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x4 "DBGSTAT,Debug Status Register" bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res" bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java" bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb" bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled" bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x8 "VECTOR,Vector Catch Register" bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena" bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena" bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena" bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena" bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena" bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena" bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena" line.long 0x10 "COMCTRL,Debug Communication Control Register" bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend" bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend" line.long 0x14 "COMDATA,Debug Communication Data Register" group ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" group ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" tree.end AUTOINDENT.POP tree.end tree "Flash (NAND Flash Controller)" base ad:0x17000800 width 19. group.long 0x00++0x1b line.long 0x00 "NANDIRQSTATUS1,Status register of first 32 bits interrupt register" eventfld.long 0x00 31. " INT31S ,mNAND_RYBN3 positive edge" "Not asserted,Asserted" eventfld.long 0x00 30. " INT30S ,mNAND_RYBN2 positive edge" "Not asserted,Asserted" textline " " eventfld.long 0x00 29. " INT29S ,mNAND_RYBN1 positive edge" "Not asserted,Asserted" eventfld.long 0x00 28. " INT28S ,mNAND_RYBN0 positive edge" "Not asserted,Asserted" textline " " eventfld.long 0x00 27. " INT27S ,RAM 1 erased" "Not asserted,Asserted" eventfld.long 0x00 26. " INT26S ,RAM 0 erased" "Not asserted,Asserted" textline " " eventfld.long 0x00 25. " INT25S ,Write page 1 done" "Not asserted,Asserted" eventfld.long 0x00 24. " INT24S ,Write page 0 done" "Not asserted,Asserted" textline " " eventfld.long 0x00 23. " INT23S ,Read page 1 done" "Not asserted,Asserted" eventfld.long 0x00 22. " INT22S ,Read page 0 done" "Not asserted,Asserted" textline " " eventfld.long 0x00 21. " INT21S ,RAM 0 decoded" "Not asserted,Asserted" eventfld.long 0x00 20. " INT20S ,RAM 0 encoded" "Not asserted,Asserted" textline " " eventfld.long 0x00 19. " INT19S ,RAM 1 decoded" "Not asserted,Asserted" eventfld.long 0x00 18. " INT18S ,RAM 1 encoded" "Not asserted,Asserted" textline " " eventfld.long 0x00 17. " INT17S ,RAM 0 decoded with 0 errors" "Not asserted,Asserted" eventfld.long 0x00 16. " INT16S ,RAM 0 decoded with 1 error" "Not asserted,Asserted" textline " " eventfld.long 0x00 15. " INT15S ,RAM 0 decoded with 2 errors" "Not asserted,Asserted" eventfld.long 0x00 14. " INT14S ,RAM 0 decoded with 3 errors" "Not asserted,Asserted" textline " " eventfld.long 0x00 13. " INT13S ,RAM 0 decoded with 4 errors" "Not asserted,Asserted" eventfld.long 0x00 12. " INT12S ,RAM 0 decoded with 5 errors" "Not asserted,Asserted" textline " " eventfld.long 0x00 11. " INT11S ,RAM 0 uncorrectable" "Not asserted,Asserted" eventfld.long 0x00 10. " INT10S ,RAM 1 decoded with 0 errors" "Not asserted,Asserted" textline " " eventfld.long 0x00 9. " INT9S ,RAM 1 decoded with 1 error" "Not asserted,Asserted" eventfld.long 0x00 8. " INT8S ,RAM 1 decoded with 2 errors" "Not asserted,Asserted" textline " " eventfld.long 0x00 7. " INT7S ,RAM 1 decoded with 3 errors" "Not asserted,Asserted" eventfld.long 0x00 6. " INT6S ,RAM 1 decoded with 4 errors" "Not asserted,Asserted" textline " " eventfld.long 0x00 5. " INT5S ,RAM 1 decoded with 5 errors" "Not asserted,Asserted" eventfld.long 0x00 4. " INT4S ,RAM 1 uncorrectable" "Not asserted,Asserted" line.long 0x04 "NANDIRQMASK1,Mask register for first 32 bits interrupt register" bitfld.long 0x04 31. " INT31M ,mNAND_RYBN3 positive edge mask" "Masked,Not masked" bitfld.long 0x04 30. " INT30M ,mNAND_RYBN2 positive edge mask" "Masked,Not masked" textline " " bitfld.long 0x04 29. " INT29M ,mNAND_RYBN1 positive edge mask" "Masked,Not masked" bitfld.long 0x04 28. " INT28M ,mNAND_RYBN0 positive edge mask" "Masked,Not masked" textline " " bitfld.long 0x04 27. " INT27M ,RAM 1 erased mask" "Masked,Not masked" bitfld.long 0x04 26. " INT26M ,RAM 0 erased mask" "Masked,Not masked" textline " " bitfld.long 0x04 25. " INT25M ,Write page 1 done mask" "Masked,Not masked" bitfld.long 0x04 24. " INT24M ,Write page 0 done mask" "Masked,Not masked" textline " " bitfld.long 0x04 23. " INT23M ,Read page 1 done mask" "Masked,Not masked" bitfld.long 0x04 22. " INT22M ,Read page 0 done mask" "Masked,Not masked" textline " " bitfld.long 0x04 21. " INT21M ,RAM 0 decoded mask" "Masked,Not masked" bitfld.long 0x04 20. " INT20M ,RAM 0 encoded mask" "Masked,Not masked" textline " " bitfld.long 0x04 19. " INT19M ,RAM 1 decoded mask" "Masked,Not masked" bitfld.long 0x04 18. " INT18M ,RAM 1 encoded mask" "Masked,Not masked" textline " " bitfld.long 0x04 17. " INT17M ,RAM 0 decoded with 0 errors mask" "Masked,Not masked" bitfld.long 0x04 16. " INT16M ,RAM 0 decoded with 1 error mask" "Masked,Not masked" textline " " bitfld.long 0x04 15. " INT15M ,RAM 0 decoded with 2 errors mask" "Masked,Not masked" bitfld.long 0x04 14. " INT14M ,RAM 0 decoded with 3 errors mask" "Masked,Not masked" textline " " bitfld.long 0x04 13. " INT13M ,RAM 0 decoded with 4 errors mask" "Masked,Not masked" bitfld.long 0x04 12. " INT12M ,RAM 0 decoded with 5 errors mask" "Masked,Not masked" textline " " bitfld.long 0x04 11. " INT11M ,RAM 0 uncorrectable mask" "Masked,Not masked" bitfld.long 0x04 10. " INT10M ,RAM 1 decoded with 0 errors mask" "Masked,Not masked" textline " " bitfld.long 0x04 9. " INT9M ,RAM 1 decoded with 1 error mask" "Masked,Not masked" bitfld.long 0x04 8. " INT8M ,RAM 1 decoded with 2 errors mask" "Masked,Not masked" textline " " bitfld.long 0x04 7. " INT7M ,RAM 1 decoded with 3 errors mask" "Masked,Not masked" bitfld.long 0x04 6. " INT6M ,RAM 1 decoded with 4 errors mask" "Masked,Not masked" textline " " bitfld.long 0x04 5. " INT5M ,RAM 1 decoded with 5 errors mask" "Masked,Not masked" bitfld.long 0x04 4. " INT4M ,RAM 1 uncorrectable mask" "Masked,Not masked" line.long 0x08 "NANDIRQSTATUSRAW1,Unmasked status register of first 32 bits interrupt register" eventfld.long 0x08 31. " INT31R ,mNAND_RYBN3 positive edge raw value" "Not asserted,Asserted" eventfld.long 0x08 30. " INT30R ,mNAND_RYBN2 positive edge raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 29. " INT29R ,mNAND_RYBN1 positive edge raw value" "Not asserted,Asserted" eventfld.long 0x08 28. " INT28R ,mNAND_RYBN0 positive edge raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 27. " INT27R ,RAM 1 erased raw value" "Not asserted,Asserted" eventfld.long 0x08 26. " INT26R ,RAM 0 erased raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 25. " INT25R ,Write page 1 done raw value" "Not asserted,Asserted" eventfld.long 0x08 24. " INT24R ,Write page 0 done raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 23. " INT23R ,Read page 1 done raw value" "Not asserted,Asserted" eventfld.long 0x08 22. " INT22R ,Read page 0 done raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 21. " INT21R ,RAM 0 decoded raw value" "Not asserted,Asserted" eventfld.long 0x08 20. " INT20R ,RAM 0 encoded raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 19. " INT19R ,RAM 1 decoded raw value" "Not asserted,Asserted" eventfld.long 0x08 18. " INT18R ,RAM 1 encoded raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 17. " INT17R ,RAM 0 decoded with 0 errors raw value" "Not asserted,Asserted" eventfld.long 0x08 16. " INT16R ,RAM 0 decoded with 1 error raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 15. " INT15R ,RAM 0 decoded with 2 errors raw value" "Not asserted,Asserted" eventfld.long 0x08 14. " INT14R ,RAM 0 decoded with 3 errors raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 13. " INT13R ,RAM 0 decoded with 4 errors raw value" "Not asserted,Asserted" eventfld.long 0x08 12. " INT12R ,RAM 0 decoded with 5 errors raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 11. " INT11R ,RAM 0 uncorrectable raw value" "Not asserted,Asserted" eventfld.long 0x08 10. " INT10R ,RAM 1 decoded with 0 errors raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 9. " INT9R ,RAM 1 decoded with 1 error raw value" "Not asserted,Asserted" eventfld.long 0x08 8. " INT8R ,RAM 1 decoded with 2 errors raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 7. " INT7R ,RAM 1 decoded with 3 errors raw value" "Not asserted,Asserted" eventfld.long 0x08 6. " INT6R ,RAM 1 decoded with 4 errors raw value" "Not asserted,Asserted" textline " " eventfld.long 0x08 5. " INT5R ,RAM 1 decoded with 5 errors raw value" "Not asserted,Asserted" eventfld.long 0x08 4. " INT4R ,RAM 1 uncorrectable raw value" "Not asserted,Asserted" line.long 0x0c "NANDCONFIG,NAND flash controller configuration register" bitfld.long 0x0C 15. " PEC ,Power off ECC clock" "Off,On" bitfld.long 0x0C 13. " ECGC ,Enable ECC clock gating" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " ECC_MODE ,ECC mode" "5 bit ECC,8 bit ECC" bitfld.long 0x0C 10.--11. " TL ,Transfer limit" "528 bytes,516 bytes,512 bytes,528 bytes" textline " " bitfld.long 0x0C 8. " DC ,Deactivate CE enable" "Not deactivated,Deactivated" bitfld.long 0x0C 7. " M ,512 mode" "512,516" textline " " bitfld.long 0x0C 5.--6. " LC ,Latency Configuration" "0 wait state,1 wait states,2 wait states,2 wait states" bitfld.long 0x0C 4. " ES ,Endianess setting" "Little endian,Big endian" textline " " bitfld.long 0x0C 3. " DE ,DMA external enable" "Disabled,Enabled" bitfld.long 0x0C 1. " WD ,Wide device" "8 bit,16 bit" textline " " bitfld.long 0x0C 0. " EC ,ECC on" "Disabled,Enabled" line.long 0x10 "NANDIOCONFIG,Register which holds the default value settings for IO signals" bitfld.long 0x10 24. " NI ,Nand IO drive default" "Input,Output" hexmask.long.word 0x10 8.--23. 1. " DN ,Data to nand default" bitfld.long 0x10 6.--7. " CD ,CLE default" "0,1,1,1" bitfld.long 0x10 4.--5. " AD ,ALE default" "0,1,1,1" textline " " bitfld.long 0x10 2.--3. " WD ,WE_n default" "0,1,1,1" bitfld.long 0x10 0.--1. " RD ,RE_n defaul" "0,1,1,1" line.long 0x14 "NANDTIMING1,First NAND flash controller timing register" bitfld.long 0x14 20.--21. " TSRD ,Single data input delay" "1,1,2,3" bitfld.long 0x14 16.--18. " TALS ,Address setup time" "1,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. " TALH ,Address hold time" "1,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. " TCLS ,Command setup time" "1,1,2,3,4,5,6,7" textline " " bitfld.long 0x14 0.--2. " TCLH ,Command hold time" "1,1,2,3,4,5,6,7" line.long 0x18 "NANDTIMING2,Second NAND flash controller timing register" bitfld.long 0x18 28.--31. " TDRD ,Data input delay" "1,1,2,3,4,5,6,7,?..." bitfld.long 0x18 24.--26. " TEBIDEL ,EBI delay time" "1,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. " TCH ,Chip select hold time" "1,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. " TCS ,Chip select setup time" "1,1,2,3,4,5,6,7" textline " " bitfld.long 0x18 12.--14. " TREH ,Read enable high hold" "1,1,2,3,4,5,6,7,?..." bitfld.long 0x18 8.--11. " TRP ,Read enable pulse width" "1,1,2,3,4,5,6,7,?..." bitfld.long 0x18 4.--6. " TWH ,Write enable high hold" "1,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. " TWP ,Write enable pulse width" "1,1,2,3,4,5,6,7" wgroup.long 0x20++0x13 line.long 0x00 "NANDSETCMD,Register to send specific command towards NAND flash device" hexmask.long.word 0x00 0.--15. 1. " CV ,Command value" line.long 0x04 "NANDSETADDR,Register to send specific address towards NAND flash device" hexmask.long.word 0x04 0.--15. 1. " AV ,Address value" line.long 0x08 "NANDWRITEDATA,Register to send specific data towards NAND flash device" hexmask.long.word 0x08 0.--15. 1. " WV ,Write value" line.long 0x0c "NANDSETCE,Register to set all CE signals and WP_n signal" bitfld.long 0x0C 4. " WP ,WP_n pin value" "Low,High" bitfld.long 0x0C 3. " CV3 ,Chip select 3" "Low,High" bitfld.long 0x0C 2. " CV2 ,Chip select 2" "Low,High" bitfld.long 0x0C 1. " CV1 ,Chip select 1" "Low,High" bitfld.long 0x0C 0. " CV0 ,Chip select 0" "Low,High" line.long 0x10 "NANDREADDATA,Register to check read data from NAND flash device" hexmask.long.word 0x10 0.--15. 1. " RV ,Read value" rgroup.long 0x34++0x3 line.long 0x00 "NANDCHECKSTS,Check status of 8 predefined interrupts" bitfld.long 0x00 8. " R3R ,mNAND_RYBN3 rising edge" "Not detected,Detected" bitfld.long 0x00 7. " R2R ,mNAND_RYBN2 rising edge" "Not detected,Detected" textline " " bitfld.long 0x00 6. " R1R ,mNAND_RYBN1 rising edge" "Not detected,Detected" bitfld.long 0x00 5. " R0R ,mNAND_RYBN0 rising edge" "Not detected,Detected" textline " " bitfld.long 0x00 4. " R3 ,mNAND_RYBN3 value" "Low,High" bitfld.long 0x00 3. " R2 ,mNAND_RYBN2 value" "Low,High" textline " " bitfld.long 0x00 2. " R1 ,mNAND_RYBN1 value" "Low,High" bitfld.long 0x00 1. " R0 ,mNAND_RYBN0 value" "Low,High" textline " " bitfld.long 0x00 0. " VB ,APB busy" "Idle,Busy" wgroup.long 0x38++0x3 line.long 0x00 "NANDCONTROLFLOW,Register which holds command to read and write pages" bitfld.long 0x00 5. " W1 ,Writes the content of SRAM1 to the NAND flash" "Not started,Started" bitfld.long 0x00 4. " W0 ,Writes the content of SRAM0 to the NAND flash" "Not started,Started" textline " " bitfld.long 0x00 1. " R1 ,Read a defined number of bytes from the NAND flash to SRAM1" "Not started,Started" bitfld.long 0x00 0. " R0 ,Read a defined number of bytes from the NAND flash to SRAM0" "Not started,Started" group.long 0x40++0x3 line.long 0x00 "NANDGPIO1,Register to program IO pins which can be used as GPIO" bitfld.long 0x00 26. " NAND_GPIO_CONF ,Modul function mode" "Normal,GPIO" bitfld.long 0x00 25. " WP_n ,Value on WP_n" "Normal,GPIO" textline " " bitfld.long 0x00 24. " CLE ,Value on CLE" "Normal,GPIO" bitfld.long 0x00 23. " ALE ,Value on ALE" "Normal,GPIO" textline " " bitfld.long 0x00 22. " RE_n ,Value on RE_n" "Normal,GPIO" bitfld.long 0x00 21. " WE_n ,Value on WE_n" "Normal,GPIO" textline " " bitfld.long 0x00 20. " CE4_n ,Value on NAND_NCS_3" "Normal,GPIO" bitfld.long 0x00 19. " CE3_n ,Value on NAND_NCS_2" "Normal,GPIO" textline " " bitfld.long 0x00 18. " CE2_n ,Value on NAND_NCS_1" "Normal,GPIO" bitfld.long 0x00 17. " CE1_n ,Value on NAND_NCS_0" "Normal,GPIO" textline " " bitfld.long 0x00 16. " NAND_IO_DRIVE ,Value on Nand io drive" "Normal,GPIO" hexmask.long.word 0x00 0.--15. 1. " Data_nand_IO ,Value on data to Nand IO" rgroup.long 0x44++0x3 line.long 0x00 "NANDGPIO2,Register to program IO pins which can be used as GPIO" bitfld.long 0x00 19. " RnB3 ,Read value from mNAND_RYBN3" "Low,High" bitfld.long 0x00 18. " RnB2 ,Read value from mNAND_RYBN2" "Low,High" textline " " bitfld.long 0x00 17. " RnB1 ,Read value from mNAND_RYBN1" "Low,High" bitfld.long 0x00 16. " RnB0 ,Read value from mNAND_RYBN0" "Low,High" textline " " hexmask.long.word 0x00 0.--15. 1. " DataNAND ,Read data from NAND IO" group.long 0x48++0xb line.long 0x00 "NANDIRQSTATUS2,Status register of second 32 bits interrupt register" eventfld.long 0x00 4. " INT36S ,Page access while APB access" "Not asserted,Asserted" eventfld.long 0x00 3. " INT35S ,APB access while page access" "Not asserted,Asserted" textline " " eventfld.long 0x00 2. " INT34S ,Flash access while busy" "Not asserted,Asserted" eventfld.long 0x00 1. " INT33S ,RAM1 access while busy" "Not asserted,Asserted" textline " " eventfld.long 0x00 0. " INT32S ,RAM0 access while busy" "Not asserted,Asserted" line.long 0x04 "NANDIRQMASK2,Mask register for second 32 bits interrupt register" bitfld.long 0x04 4. " INT36M ,Page access while APB access masks" "Masked,Not masked" bitfld.long 0x04 3. " INT35M ,APB access while page access mask" "Masked,Not masked" textline " " bitfld.long 0x04 2. " INT34M ,Flash access while busy mask" "Masked,Not masked" bitfld.long 0x04 1. " INT33M ,RAM1 access while busy mask" "Masked,Not masked" textline " " bitfld.long 0x04 0. " INT32M ,RAM0 access while busy mask" "Masked,Not masked" line.long 0x08 "NANDIRQSTATUSRAW2,Unmasked status register of second 32 bits interrupt register" eventfld.long 0x08 4. " INT36R ,Page access while APB access" "Not asserted,Asserted" eventfld.long 0x08 3. " INT35R ,APB access while page access" "Not asserted,Asserted" textline " " eventfld.long 0x08 2. " INT34R ,Flash access while busy" "Not asserted,Asserted" eventfld.long 0x08 1. " INT33R ,RAM1 access while busy" "Not asserted,Asserted" textline " " eventfld.long 0x08 0. " INT32R ,RAM0 access while busy" "Not asserted,Asserted" rgroup.long 0x78++0x3 line.long 0x00 "NANDECCERRSTATUS,ECC error status register in 8-symbol ECC mode" bitfld.long 0x00 4.--7. " N_ERR_1 ,Number of errors in RAM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " N_ERR_0 ,Number of errors in RAM0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "MPMC (Multi-Port Memory Controller)" base ad:0x17008000 width 0x17 group.long 0x0++0x3 line.long 0x0 "MPMCControl,MPMC Control Register" bitfld.long 0x0 2. " L ,Low-power mode control" "Normal,Low-power" bitfld.long 0x0 1. " M ,Address mirror control" "Normal,Reset" bitfld.long 0x0 0. " E ,MPMC Enable control" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "MPMCStatus,MPMC Status Register" bitfld.long 0x0 2. " SA ,Operating mode of the MPMC" "Normal,Self-refresh" bitfld.long 0x0 1. " S ,Write buffer status" "Empty,Not empty" bitfld.long 0x0 0. " B ,Memory controller busy" "Idle,Busy" width 0x17 group.long 0x8++0x3 line.long 0x0 "MPMCConfig,MPMC Configuration Register" bitfld.long 0x0 8. " CLK ,Clock ratio;CLK HCLK:MPMCCLKOUT ratio" "1:1,1:2" bitfld.long 0x0 0. " N ,Endian mode" "Little-endian,Big-endian" width 0x17 group.long 0x20++0xB line.long 0x0 "MPMCDynamicControl,Dynamic Memory Control" bitfld.long 0x0 13. " DP ,Low-power SDRAM deep-sleep mode" "Normal,Deep power down" bitfld.long 0x0 7.--8. " I ,SDRAM initialization" "NORMAL,MODE,PALL,NOP" textline " " bitfld.long 0x0 5. " MMC ,Memory clock control" "Enabled,Disabled" bitfld.long 0x0 2. " SR ,Self-refresh request,MPMCSREFREQ" "Normal,Self-refresh" textline " " bitfld.long 0x0 1. " CS ,Dynamic memory clock control" "Stops,Runs continouosly" bitfld.long 0x0 0. " CE ,Dynamic memory clock enable" "Deasserted,Driven high" width 0x17 line.long 0x4 "MPMCDynamicRefresh,Dynamic Memory Refresh Timer" hexmask.long.word 0x4 0.--10. 1. " REFRESH ,Refresh timer" line.long 0x8 "MPMCDynamicReadConfig,Dynamic Memory Read Configuration" bitfld.long 0x8 0.--1. " RD ,Read data strategy" "CLKOUT,MPMCCLKDELAY,MPMCCLKDELAY+1,MPMCCLKDELAY+2" group.long 0x30++0x2B line.long 0x0 "MPMCDynamictRP,Dynamic Memory Percentage Command Period" bitfld.long 0x0 0.--3. " tRP ,Precharge command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x4 "MPMCDynamictRAS,Dynamic Memory Active to Precharge Command Period" bitfld.long 0x4 0.--3. " tRAS ,Active to precharge command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x8 "MPMCDynamictSREX,Dynamic Memory Self-refresh Exit Time" bitfld.long 0x8 0.--3. " tSREX ,Self-refresh exit time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0xC "MPMCDynamictAPR,Dynamic Memory Last Data Out to Active Time" bitfld.long 0xC 0.--3. " tAPR ,Last-data-out to active command time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x10 "MPMCDynamictDAL,Dynamic Memory Data-in to Active Command Time" bitfld.long 0x10 0.--3. " tDAL ,Data-in to active command" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" line.long 0x14 "MPMCDynamictWR,Dynamic Memory Write Recovery Time" bitfld.long 0x14 0.--3. " tWR ,Write recovery time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x18 "MPMCDynamictRC,Dynamic Memory Active to Active Command Period" bitfld.long 0x18 0.--4. " tRC ,Active to active command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x1C "MPMCDynamictRFC,Dynamic Memory Auto-refresh Period" bitfld.long 0x1C 0.--4. " tRFC ,Auto-refresh period and auto-refresh to active command period" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x20 "MPMCDynamictXSR,Dynamic Memory Exit Self-refresh" bitfld.long 0x20 0.--4. " tXSR ,Exit self-refresh to active command time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x24 "MPMCDynamictRRD,Dynamic Memory Active Bank A to Active Bank B Time" bitfld.long 0x24 0.--3. " tRRD ,Active bank A to active bank B latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x28 "MPMCDynamictMRD,Dynamic Memory Load Mode register to Active Command Time" bitfld.long 0x28 0.--3. " tMRD ,Load mode register to active command time" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" group.long 0x80++0x3 line.long 0x00 "MPMCStaticExtendedWait,Static Memory Extended Wait" hexmask.long.word 0x00 0.--9. 1. " EXTENDEDWAIT ,External wait time out" width 0x17 tree "Bank 0" width 0x14 group.long (0x100+0x0)++0x7 line.long 0x00 "MPMCDynamicConfig0,Dynamic Memory Configuration" bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AM[14] ,Address Mapping[14]" "0,1" bitfld.long 0x00 12. " AM[12] ,Address Mapping[12]" "0,1" textline " " bitfld.long 0x00 9.--11. " AM[11:9] ,Address Mapping[11:9]" "000,001,010,011,100,101,110,111" bitfld.long 0x00 7.--8. " AM[8:7] ,Address Mapping[8:7]" "00,01,10,11" textline " " bitfld.long 0x00 3.--4. " MD ,Memory Device" "SDRAM,Low-Power SDRAM,Micron SyncFlash,?..." line.long 0x04 "MPMCDynamicRasCas0,Dynamic Memory RAS & CAS" bitfld.long 0x04 8.--9. " CAS ,CAS Latency" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" bitfld.long 0x04 0.--1. " RAS ,RAS latency (active to read/write delay)" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" width 0x14 group.long (0x200+0x0)++0x1b line.long 0x00 "MPMCStaticConfig0,Static Memory Configuration" bitfld.long 0x00 20. " WP ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BLS ,nBLOUT[1:0] and EBI_nWE signals behavior (nBLOUT[1:0] Writes/EBI_nWE Writes/nBLOUT[1:0] Reads)" "Low/Active/High,Low/Inactive/Low" bitfld.long 0x00 6. " PC ,Chip select polarity" "Active LOW,Active HIGH" bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,?..." width 0x14 line.long 0x04 "MPMCStaticWaitWen0,Static Memory Write Enable Delay" bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x08 "MPMCStaticWaitOen0,Static Memory Output Enable Delay" bitfld.long 0x08 0.--3. " WAITOEN ,Wait Output Enable" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" line.long 0x0C "MPMCStaticWaitRd0,Static Memory Read Delay" bitfld.long 0x0C 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x10 "MPMCStaticWaitPage0,Static Memory Page Mode Read Delay" bitfld.long 0x10 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x14 "MPMCStaticWaitWr0,Static Memory Write Delay" bitfld.long 0x14 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles" line.long 0x18 "MPMCStaticWaitTurn0,Static Memory Turn Round Delay" bitfld.long 0x18 0.--3. " WAITTURN ,Bus turnaround cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" tree.end tree "Bank 1" width 0x14 group.long (0x100+0x20)++0x7 line.long 0x00 "MPMCDynamicConfig1,Dynamic Memory Configuration" bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AM[14] ,Address Mapping[14]" "0,1" bitfld.long 0x00 12. " AM[12] ,Address Mapping[12]" "0,1" textline " " bitfld.long 0x00 9.--11. " AM[11:9] ,Address Mapping[11:9]" "000,001,010,011,100,101,110,111" bitfld.long 0x00 7.--8. " AM[8:7] ,Address Mapping[8:7]" "00,01,10,11" textline " " bitfld.long 0x00 3.--4. " MD ,Memory Device" "SDRAM,Low-Power SDRAM,Micron SyncFlash,?..." line.long 0x04 "MPMCDynamicRasCas1,Dynamic Memory RAS & CAS" bitfld.long 0x04 8.--9. " CAS ,CAS Latency" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" bitfld.long 0x04 0.--1. " RAS ,RAS latency (active to read/write delay)" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" width 0x14 group.long (0x200+0x20)++0x1b line.long 0x00 "MPMCStaticConfig1,Static Memory Configuration" bitfld.long 0x00 20. " WP ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BLS ,nBLOUT[1:0] and EBI_nWE signals behavior (nBLOUT[1:0] Writes/EBI_nWE Writes/nBLOUT[1:0] Reads)" "Low/Active/High,Low/Inactive/Low" bitfld.long 0x00 6. " PC ,Chip select polarity" "Active LOW,Active HIGH" bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,?..." width 0x14 line.long 0x04 "MPMCStaticWaitWen1,Static Memory Write Enable Delay" bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x08 "MPMCStaticWaitOen1,Static Memory Output Enable Delay" bitfld.long 0x08 0.--3. " WAITOEN ,Wait Output Enable" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" line.long 0x0C "MPMCStaticWaitRd1,Static Memory Read Delay" bitfld.long 0x0C 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x10 "MPMCStaticWaitPage1,Static Memory Page Mode Read Delay" bitfld.long 0x10 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x14 "MPMCStaticWaitWr1,Static Memory Write Delay" bitfld.long 0x14 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles" line.long 0x18 "MPMCStaticWaitTurn1,Static Memory Turn Round Delay" bitfld.long 0x18 0.--3. " WAITTURN ,Bus turnaround cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" tree.end tree "Bank 2" width 0x14 group.long (0x100+0x40)++0x7 line.long 0x00 "MPMCDynamicConfig2,Dynamic Memory Configuration" bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AM[14] ,Address Mapping[14]" "0,1" bitfld.long 0x00 12. " AM[12] ,Address Mapping[12]" "0,1" textline " " bitfld.long 0x00 9.--11. " AM[11:9] ,Address Mapping[11:9]" "000,001,010,011,100,101,110,111" bitfld.long 0x00 7.--8. " AM[8:7] ,Address Mapping[8:7]" "00,01,10,11" textline " " bitfld.long 0x00 3.--4. " MD ,Memory Device" "SDRAM,Low-Power SDRAM,Micron SyncFlash,?..." line.long 0x04 "MPMCDynamicRasCas2,Dynamic Memory RAS & CAS" bitfld.long 0x04 8.--9. " CAS ,CAS Latency" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" bitfld.long 0x04 0.--1. " RAS ,RAS latency (active to read/write delay)" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" width 0x14 group.long (0x200+0x40)++0x1b line.long 0x00 "MPMCStaticConfig2,Static Memory Configuration" bitfld.long 0x00 20. " WP ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BLS ,nBLOUT[1:0] and EBI_nWE signals behavior (nBLOUT[1:0] Writes/EBI_nWE Writes/nBLOUT[1:0] Reads)" "Low/Active/High,Low/Inactive/Low" bitfld.long 0x00 6. " PC ,Chip select polarity" "Active LOW,Active HIGH" bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,?..." width 0x14 line.long 0x04 "MPMCStaticWaitWen2,Static Memory Write Enable Delay" bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x08 "MPMCStaticWaitOen2,Static Memory Output Enable Delay" bitfld.long 0x08 0.--3. " WAITOEN ,Wait Output Enable" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" line.long 0x0C "MPMCStaticWaitRd2,Static Memory Read Delay" bitfld.long 0x0C 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x10 "MPMCStaticWaitPage2,Static Memory Page Mode Read Delay" bitfld.long 0x10 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x14 "MPMCStaticWaitWr2,Static Memory Write Delay" bitfld.long 0x14 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles" line.long 0x18 "MPMCStaticWaitTurn2,Static Memory Turn Round Delay" bitfld.long 0x18 0.--3. " WAITTURN ,Bus turnaround cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" tree.end tree "Bank 3" width 0x14 group.long (0x100+0x60)++0x7 line.long 0x00 "MPMCDynamicConfig3,Dynamic Memory Configuration" bitfld.long 0x00 20. " P ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AM[14] ,Address Mapping[14]" "0,1" bitfld.long 0x00 12. " AM[12] ,Address Mapping[12]" "0,1" textline " " bitfld.long 0x00 9.--11. " AM[11:9] ,Address Mapping[11:9]" "000,001,010,011,100,101,110,111" bitfld.long 0x00 7.--8. " AM[8:7] ,Address Mapping[8:7]" "00,01,10,11" textline " " bitfld.long 0x00 3.--4. " MD ,Memory Device" "SDRAM,Low-Power SDRAM,Micron SyncFlash,?..." line.long 0x04 "MPMCDynamicRasCas3,Dynamic Memory RAS & CAS" bitfld.long 0x04 8.--9. " CAS ,CAS Latency" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" bitfld.long 0x04 0.--1. " RAS ,RAS latency (active to read/write delay)" "Reserved,1 CCLK cycle,2 CCLK cycles,3 CCLK cycles" width 0x14 group.long (0x200+0x60)++0x1b line.long 0x00 "MPMCStaticConfig3,Static Memory Configuration" bitfld.long 0x00 20. " WP ,Write protect" "Not protected,Protected" bitfld.long 0x00 19. " B ,Buffer enable" "Disabled,Enabled" bitfld.long 0x00 8. " EW ,Extended wait" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BLS ,nBLOUT[1:0] and EBI_nWE signals behavior (nBLOUT[1:0] Writes/EBI_nWE Writes/nBLOUT[1:0] Reads)" "Low/Active/High,Low/Inactive/Low" bitfld.long 0x00 6. " PC ,Chip select polarity" "Active LOW,Active HIGH" bitfld.long 0x00 3. " PM ,Page mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MW ,Memory width" "8 bit,16 bit,?..." width 0x14 line.long 0x04 "MPMCStaticWaitWen3,Static Memory Write Enable Delay" bitfld.long 0x04 0.--3. " WAITWEN ,Wait write enable" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" line.long 0x08 "MPMCStaticWaitOen3,Static Memory Output Enable Delay" bitfld.long 0x08 0.--3. " WAITOEN ,Wait Output Enable" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" line.long 0x0C "MPMCStaticWaitRd3,Static Memory Read Delay" bitfld.long 0x0C 0.--4. " WAITRD ,Non-page mode read wait states or asynchronous page mode readfirst access wait state" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x10 "MPMCStaticWaitPage3,Static Memory Page Mode Read Delay" bitfld.long 0x10 0.--4. " WAITPAGE ,Asynchronous page mode read after the first read wait states" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" line.long 0x14 "MPMCStaticWaitWr3,Static Memory Write Delay" bitfld.long 0x14 0.--4. " WAITWR ,Write wait states" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles" line.long 0x18 "MPMCStaticWaitTurn3,Static Memory Turn Round Delay" bitfld.long 0x18 0.--3. " WAITTURN ,Bus turnaround cycles" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles" tree.end width 0xB tree.end tree.open "USB OTG (On-The-Go) Controller" base ad:0x19000000 width 12. tree "Device/Host Capability" rgroup.byte 0x100++0x0 line.byte 0x0 "CAPLENGTH,Capability Register Length Register" rgroup.word 0x102++0x1 line.word 0x0 "HCIVERSION,Host Interface Version Number Register" rgroup.long 0x104++0x7 line.long 0x0 "HCSPARAMS,Host Control Structural Parameters Register" bitfld.long 0x00 24.--27. " N_TT ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " N_PTT ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16. " PI ,Port Indicators" "Not supported,Supported" bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included" textline " " bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4 "HCCPARAMS,Host Control Capability Parameters Register" hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "1 micro-frame,2 micro-frames,3 micro-frames,4 micro-frames,5 micro-frames,6 micro-frames,7 micro-frames,8 micro-frames,Entire frame,Entire frame,Entire frame,Entire frame,Entire frame,Entire frame,Entire frame,Entire frame" textline " " bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Not capable,Capable" bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "1024 elements,Programmable" textline " " bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Not capable,Capable" rgroup.word 0x120++0x1 line.word 0x0 "DCIVERSION,Device Interface Version Number Register" rgroup.long 0x124++0x3 line.long 0x0 "DCCPARAMS,Device Controller Capability Parameters Register" bitfld.long 0x0 8. " HC ,Host Capable" "Not capable,Capable" bitfld.long 0x0 7. " DC ,Device Capable" "Not capable,Capable" textline " " bitfld.long 0x00 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 18. tree "Device/Host Operational" if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x140++0x03 line.long 0x0 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" textline " " bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard" bitfld.long 0x00 12. " ATDTW ,Add DTD Tripwire" "Not added,Added" textline " " bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Run/Stop" "Detach event,Attach event" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x140++0x03 line.long 0x0 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. 3. 15. " FS ,Frame List Size" "1024 elements,512 elements,256 elements,128 elements,64 elements,32 elements,16 elements,8 elements" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stopped,Running" else hgroup.long 0x140++0x03 hide.long 0x00 "USBCMD,USB Command Register" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x144++0x3 line.long 0x00 "USBSTS,USB Status Register" bitfld.long 0x00 16. " NAKI ,NAK Interrupt Bit" "No interrupt,Interrupt" eventfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not received,Received" eventfld.long 0x00 6. " URI ,USB Reset Received" "Not received,Received" textline " " eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not detected,Detected" eventfld.long 0x00 1. " UEI ,USB Error Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x144++0x3 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 19. " UPI ,Interrupt on completion of a USB transaction (USBHSTPERINT)" "No interrupt,Interrupt" textline " " eventfld.long 0x00 18. " UAI ,USB Host Asynchronous Interrupt (USBHSTASYNCINT)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RCL ,Reclamation" "No reclamation,Reclamation" bitfld.long 0x00 12. " HCH ,HC HaIted" "Not halted,Halted" textline " " eventfld.long 0x00 7. " SRI ,SOF Received" "Not received,Received" eventfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " FRI ,Frame List Rollover" "No rollover,Rollover" eventfld.long 0x00 2. " PCI ,Port Change Detect" "Not detected,Detected" textline " " eventfld.long 0x00 1. " UEI ,USB Error Interrupt (USBERRINT)" "No interrupt,Interrupt" eventfld.long 0x00 0. " UI ,USB Interrupt (USBINT)" "No interrupt,Interrupt" else hgroup.long 0x144++0x3 hide.long 0x00 "USBSTS,USB Status Register" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x148++0x3 line.long 0x00 "USBINTR,USB Interrupts Enable Register" bitfld.long 0x00 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x148++0x3 line.long 0x00 "USBINTR,USB Interrupts Enable Register" bitfld.long 0x00 19. " UPIA ,USB Host Periodic Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " UAIE ,USB Host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ULPIE ,ULPI Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UEE ,USB Error Interrupt (USBERRINT) Enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB Interrupt (USBINT) Enable" "Disabled,Enabled" else hgroup.long 0x148++0x3 hide.long 0x00 "USBINTR,USB Interrupts Enable Register" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) rgroup.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 3.--13. 1. " FRINDEX[13:3] ,Current frame number of the last frame transmitted" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==(0x0||0x1)) hgroup.long 0x14C++0x3 hide.long 0x00 "FRINDEX,USB Frame Index Register" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x800c) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 3.--5. 1. " FRINDEX[5:3] ,Frame list current index" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x8008) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 3.--6. 1. " FRINDEX[6:3] ,Frame list current index" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x8004) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 3.--7. 1. " FRINDEX[7:3] ,Frame list current index" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x8000) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 3.--8. 1. " FRINDEX[8:3] ,Frame list current index" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x000c) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 3.--9. 1. " FRINDEX[9:3] ,Frame list current index" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x0008) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 3.--10. 1. " FRINDEX[10:3] ,Frame list current index" elif ((d.l(ad:(0x19000000+0x140))&0x800c)==0x0004) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 3.--11. 1. " FRINDEX[11:3] ,Frame list current index" else group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" bitfld.long 0x00 0.--2. " FRINDEX[2:0] ,Current micro frame number" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 3.--12. 1. " FRINDEX[12:3] ,Frame list current index" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) ; USBMODE[CM[1:0](0-1)] = Device(2) group.long 0x154++0x7 line.long 0x0 "DEVICEADDR,Device Controller USB Device Address" hexmask.long.byte 0x0 25.--31. 2. " USBADR ,Device Address" bitfld.long 0x00 24. " USBADRA ,Device address advance" "Disabled,Enabled" line.long 0x4 "ENDPOINTLISTADDR,Device Controller Endpoint List Address" hexmask.long 0x4 11.--31. 0x800 " EPBASE[31:11] ,Endpoint Base" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) ; USBMODE[CM[1:0](0-1)] = Host(3) group.long 0x154++0x7 line.long 0x0 "PERIODICLISTBASE,Frame List Base Address" hexmask.long 0x0 12.--31. 0x1000 " PERBASE ,Base Address (Low)" line.long 0x4 "ASYNCLISTADDR,Host Controller Next Asynchronous Address" hexmask.long 0x4 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low (LPL)" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x15c++0x3 line.long 0x00 "TTCTRL,TT Control Register" hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Hub address when FS or LS device are connected directly" else hgroup.long 0x15c++0x3 hide.long 0x00 "TTCTRL,TT Control Register" endif group.long 0x160++0x3 line.long 0x0 "BURSTSIZE,Programmable Burst Size" hexmask.long.word 0x0 8.--15. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x0 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x164++0x3 line.long 0x00 "TXFILLTUNING,TX Fill Tuning Register" hexmask.long.byte 0x00 16.--21. 1. " TXFIFOTHR ,FIFO burst threshold" hexmask.long.byte 0x00 8.--12. 1. " TXSCHEAL ,Scheduler health counter" textline " " hexmask.long.byte 0x00 0.--7. 1. " TXSCHOH ,Scheduler overhead" else hgroup.long 0x164++0x3 hide.long 0x00 "TXFILLTUNING,TX Fill Tuning Register" endif group.long 0x168++0x3 line.long 0x0 "TXTTFILLTUNING,Host TT Transmit Pre-Buffer Packet Tuning" group.long 0x174++0x3 line.long 0x0 "BINTERVAL,BINTERVAL Register" bitfld.long 0x00 0.--3. " BINT ,bInterval value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x178++0x7 line.long 0x0 "ENDPTNAK,Endpoint NAK" eventfld.long 0x0 19. " EPTN3 ,TX Endpoint NAK 3" "No NAK,NAK" eventfld.long 0x0 18. " EPTN2 ,TX Endpoint NAK 2" "No NAK,NAK" textline " " eventfld.long 0x0 17. " EPTN1 ,TX Endpoint NAK 1" "No NAK,NAK" eventfld.long 0x0 16. " EPTN0 ,TX Endpoint NAK 0" "No NAK,NAK" textline " " eventfld.long 0x0 3. " EPRN3 ,RX Endpoint NAK 3" "No NAK,NAK" eventfld.long 0x0 2. " EPRN2 ,RX Endpoint NAK 2" "No NAK,NAK" textline " " eventfld.long 0x0 1. " EPRN1 ,RX Endpoint NAK 1" "No NAK,NAK" eventfld.long 0x0 0. " EPRN0 ,RX Endpoint NAK 0" "No NAK,NAK" else hgroup.long 0x178++0x7 hide.long 0x0 "ENDPTNAK,Endpoint NAK" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x17c++0x3 line.long 0x00 "ENDPTNAKEN,Endpoint NAK Enable" bitfld.long 0x00 19. " EPTNE3 ,TX Endpoint NAK Enable 3" "Disabled,Enabled" bitfld.long 0x00 18. " EPTNE2 ,TX Endpoint NAK Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " EPTNE1 ,TX Endpoint NAK Enable 1" "Disabled,Enabled" bitfld.long 0x00 16. " EPTNE0 ,TX Endpoint NAK Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EPRNE3 ,RX Endpoint NAK Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " EPRNE2 ,RX Endpoint NAK Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " EPRNE1 ,RX Endpoint NAK Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " EPRNE0 ,RX Endpoint NAK Enable 0" "Disabled,Enabled" else hgroup.long 0x17c++0x3 hide.long 0x00 "ENDPTNAKEN,Endpoint NAK Enable" endif if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x184++0x3 line.long 0x0 "PORTSC1,Port Status/Control 1" bitfld.long 0x0 26.--27. " PSPD ,Port Speed" "Full,Reserved,High,?..." textline " " bitfld.long 0x0 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x0 23. " PHCD ,PHY Low Power Suspend - Clock Disable" "Enabled,Disabled" textline " " bitfld.long 0x0 16.--19. " PTC ,Port Test Control" "TEST_MODE_DISABLE,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,?..." bitfld.long 0x0 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Green,?..." textline " " bitfld.long 0x0 9. " HSP ,High-Speed Port" "Not high-speed,High-speed" bitfld.long 0x0 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x0 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x0 6. " FPR ,Force Port Resume" "Not resumed,Resumed" textline " " eventfld.long 0x0 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x0 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " CCS ,Current Connect Status" "Not connected,Connected" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x184++0x3 line.long 0x0 "PORTSC1,Port Status/Control 1" bitfld.long 0x0 26.--27. " PSPD ,Port Speed" "Full,Low,High,?..." textline " " bitfld.long 0x0 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x0 23. " PHCD ,PHY Low Power Suspend - Clock Disable" "Enabled,Disabled" textline " " bitfld.long 0x0 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled" bitfld.long 0x0 21. " WKDC ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x0 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x0 16.--19. " PTC ,Port Test Control" "TEST_MODE_DISABLE,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x0 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Green,?..." textline " " bitfld.long 0x0 12. " PP ,Port Power Control" "Off,On" bitfld.long 0x0 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..." textline " " bitfld.long 0x0 9. " HSP ,High-Speed Status" "Not high-speed,High-speed" bitfld.long 0x0 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x0 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x0 6. " FPR ,Force Port Resume" "Not resumed,Resumed" textline " " eventfld.long 0x0 5. " OCC ,Over-current Change" "Not changed,Changed" bitfld.long 0x0 4. " OCA ,Over-current Active" "Not active,Active" textline " " eventfld.long 0x0 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed" bitfld.long 0x0 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " eventfld.long 0x0 1. " CSC ,Connect Status Change" "Not changed,Changed" eventfld.long 0x0 0. " CCS ,Current Connect Status" "Not connected,Connected" else group.long 0x184++0x3 line.long 0x0 "PORTSC1,Port Status/Control 1" endif group.long 0x1A4++0x3 line.long 0x0 "OTGSC,On-The-Go (OTG) Status and Control" bitfld.long 0x0 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 29. " 1msE ,1 millisecond timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x0 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x0 21. " 1msS ,1 millisecond timer Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x0 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x0 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x0 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt" textline " " eventfld.long 0x0 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt" eventfld.long 0x0 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x0 14. " DPS ,Data Bus Pulsing Status" "Not pulsing,Pulsing" bitfld.long 0x0 13. " 1msT ,1 millisecond timer toggle" "Low,High" textline " " bitfld.long 0x0 12. " BSE ,B Session End" "Not below,Below" bitfld.long 0x0 11. " BSV ,B Session Valid" "Not valid,Valid" textline " " bitfld.long 0x0 10. " ASV ,A Session Valid" "Not valid,Valid" bitfld.long 0x0 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " bitfld.long 0x0 8. " ID ,USB ID" "A device,B device" bitfld.long 0x0 7. " HABA ,Hardware assist B-disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " HADP ,Hardware assist data pulse" "Not started,Started" bitfld.long 0x0 5. " IDPU ,ID Pull-up" "No pull-up,Pull-up" textline " " bitfld.long 0x0 4. " DP ,Data Pulsing" "Not pulsing,Pulsing" bitfld.long 0x0 3. " OT ,OTG Termination" "Not terminated,Terminated" textline " " bitfld.long 0x0 2. " HAAR ,Hardware assist auto_reset" "Disabled,Enabled" bitfld.long 0x0 1. " VC ,VBUS Charge" "Not charged,Charged" textline " " bitfld.long 0x0 0. " VD ,VBUS_Discharge" "Not discharged,Discharged" if (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x2) group.long 0x1A8++0x7 line.long 0x0 "USBMODE,USB Device Mode" bitfld.long 0x0 4. " SDIS ,Stream Disable Mode" "Inactive,Active" bitfld.long 0x0 3. " SLOM ,Setup Lockout Mode" "On,Off" textline " " bitfld.long 0x0 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x0 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" elif (((data.long(ad:(0x19000000+0x1A8)))&0x3)==0x3) group.long 0x1A8++0x7 line.long 0x0 "USBMODE,USB Device Mode" bitfld.long 0x0 5. " VBPS ,VBUS power select" "Low,High" bitfld.long 0x0 4. " SDIS ,Stream Disable Mode" "Inactive,Active" textline " " bitfld.long 0x0 2. " ES ,Endian Select" "Little,Big" bitfld.long 0x0 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" else group.long 0x1A8++0x7 line.long 0x0 "USBMODE,USB Device Mode" textline " " bitfld.long 0x0 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" endif tree.end width 16. tree "Device Endpoint" group.long 0x1ac++0x3 line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status" eventfld.long 0x00 3. " ENDPTSETUPSTAT3 ,Setup Endpoint Status 3" "Not received,Received" eventfld.long 0x00 2. " ENDPTSETUPSTAT2 ,Setup Endpoint Status 2" "Not received,Received" textline " " eventfld.long 0x00 1. " ENDPTSETUPSTAT1 ,Setup Endpoint Status 1" "Not received,Received" eventfld.long 0x00 0. " ENDPTSETUPSTAT0 ,Setup Endpoint Status 0" "Not received,Received" group.long 0x1B0++0x7 line.long 0x0 "ENDPTPRIME,Endpoint Initialization" bitfld.long 0x0 19. " PETB3 ,Prime Endpoint Transmit Buffer 3" "Not primed,Primed" bitfld.long 0x0 18. " PETB2 ,Prime Endpoint Transmit Buffer 2" "Not primed,Primed" textline " " bitfld.long 0x0 17. " PETB1 ,Prime Endpoint Transmit Buffer 1" "Not primed,Primed" bitfld.long 0x0 16. " PETB0 ,Prime Endpoint Transmit Buffer 0" "Not primed,Primed" textline " " bitfld.long 0x0 3. " PERB3 ,Prime Endpoint Receive Buffer 3" "Not primed,Primed" bitfld.long 0x0 2. " PERB2 ,Prime Endpoint Receive Buffer 2" "Not primed,Primed" textline " " bitfld.long 0x0 1. " PERB1 ,Prime Endpoint Receive Buffer 1" "Not primed,Primed" bitfld.long 0x0 0. " PERB0 ,Prime Endpoint Receive Buffer 0" "Not primed,Primed" line.long 0x4 "ENDPTFLUSH,Endpoint De-Initialize" bitfld.long 0x4 19. " FETB3 ,Flush Endpoint Transmit Buffer 3" "Not flushed,Flushed" bitfld.long 0x4 18. " FETB2 ,Flush Endpoint Transmit Buffer 2" "Not flushed,Flushed" textline " " bitfld.long 0x4 17. " FETB1 ,Flush Endpoint Transmit Buffer 1" "Not flushed,Flushed" bitfld.long 0x4 16. " FETB0 ,Flush Endpoint Transmit Buffer 0" "Not flushed,Flushed" textline " " bitfld.long 0x4 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x4 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" textline " " bitfld.long 0x4 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" bitfld.long 0x4 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed" rgroup.long 0x1B8++0x3 line.long 0x0 "ENDPTSTAT,Endpoint Status" bitfld.long 0x0 19. " ETBR3 ,Endpoint Transmit Buffer Ready 3" "Not ready,Ready" bitfld.long 0x0 18. " ETBR2 ,Endpoint Transmit Buffer Ready 2" "Not ready,Ready" textline " " bitfld.long 0x0 17. " ETBR1 ,Endpoint Transmit Buffer Ready 1" "Not ready,Ready" bitfld.long 0x0 16. " ETBR0 ,Endpoint Transmit Buffer Ready 0" "Not ready,Ready" textline " " bitfld.long 0x0 3. " ERBR3 ,Endpoint Receive Buffer Ready 3" "Not ready,Ready" bitfld.long 0x0 2. " ERBR2 ,Endpoint Receive Buffer Ready 2" "Not ready,Ready" textline " " bitfld.long 0x0 1. " ERBR1 ,Endpoint Receive Buffer Ready 1" "Not ready,Ready" bitfld.long 0x0 0. " ERBR0 ,Endpoint Receive Buffer Ready 0" "Not ready,Ready" group.long 0x1BC++0x3 line.long 0x0 "ENDPTCOMPLETE,Endpoint Complete" eventfld.long 0x0 19. " ETCE3 ,Endpoint Transmit Complete Event 3" "No event,Event" eventfld.long 0x0 18. " ETCE2 ,Endpoint Transmit Complete Event 2" "No event,Event" textline " " eventfld.long 0x0 17. " ETCE1 ,Endpoint Transmit Complete Event 1" "No event,Event" eventfld.long 0x0 16. " ETCE0 ,Endpoint Transmit Complete Event 0" "No event,Event" textline " " eventfld.long 0x0 3. " ERCE3 ,Endpoint Receive Complete Event 3" "No event,Event" eventfld.long 0x0 2. " ERCE2 ,Endpoint Receive Complete Event 2" "No event,Event" textline " " eventfld.long 0x0 1. " ERCE1 ,Endpoint Receive Complete Event 1" "No event,Event" eventfld.long 0x0 0. " ERCE0 ,Endpoint Receive Complete Event 0" "No event,Event" group.long 0x1C0++0xf line.long 0x0 "ENDPTCTRL0,Endpoint Control 0" bitfld.long 0x0 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x0 18.--19. " TXT ,TX Endpoint Type" "Control,?..." textline " " bitfld.long 0x0 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled" bitfld.long 0x0 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2.--3. " RXT ,RX Endpoint Type" "Control,?..." bitfld.long 0x0 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled" line.long 0x4 "ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..." textline " " bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled" line.long 0x8 "ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..." textline " " bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled" line.long 0xC "ENDPTCTRL3,Endpoint Control 3" bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Not inhibited,Inhibited" bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Not inhibited,Inhibited" bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..." textline " " bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled" tree.end width 0xb tree.end tree.open "DMA (DMA controller)" base ad:0x17000000 width 21. tree "Channel Registers" tree "Channel 0" group.long (0x00+0x0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 0" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 0" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 0" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 0" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 0" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x0)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 0" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 1" group.long (0x00+0x20)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 1" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 1" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 1" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 1" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 1" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x20)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 1" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 2" group.long (0x00+0x40)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 2" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 2" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 2" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 2" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 2" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x40)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 2" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 3" group.long (0x00+0x60)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 3" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 3" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 3" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 3" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 3" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x60)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 3" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 4" group.long (0x00+0x80)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 4" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 4" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 4" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 4" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 4" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x80)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 4" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 5" group.long (0x00+0xA0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 5" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 5" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 5" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 5" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 5" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0xA0)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 5" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 6" group.long (0x00+0xC0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 6" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 6" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 6" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 6" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 6" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0xC0)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 6" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 7" group.long (0x00+0xE0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 7" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 7" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 7" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 7" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 7" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0xE0)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 7" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 8" group.long (0x00+0x100)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 8" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 8" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 8" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 8" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 8" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x100)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 8" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 9" group.long (0x00+0x120)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 9" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 9" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 9" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 9" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 9" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x120)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 9" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 10" group.long (0x00+0x140)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 10" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 10" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 10" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 10" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 10" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x140)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 10" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree "Channel 11" group.long (0x00+0x160)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 11" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 11" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 11" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 11" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." line.long 0x10 "ENABLE,Enable register for channel 11" bitfld.long 0x10 0. " ENABLE ,Channel Enable" "Disabled,Enabled" group.long (0x1c+0x160)++0x3 line.long 0x00 "TRANSFER_COUNTER,Transfer counter register for channel 11" hexmask.long.tbyte 0x00 0.--20. 1. " TRANSFER_COUNTER ,Amount of cycles to transfer" tree.end tree.end tree "Alternate Channel Registers" tree "Alternate Channel 0" wgroup.long (0x200+0x0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 0" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 0" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 0" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 0" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 1" wgroup.long (0x200+0x10)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 1" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 1" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 1" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 1" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 2" wgroup.long (0x200+0x20)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 2" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 2" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 2" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 2" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 3" wgroup.long (0x200+0x30)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 3" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 3" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 3" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 3" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 4" wgroup.long (0x200+0x40)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 4" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 4" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 4" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 4" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 5" wgroup.long (0x200+0x50)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 5" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 5" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 5" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 5" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 6" wgroup.long (0x200+0x60)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 6" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 6" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 6" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 6" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 7" wgroup.long (0x200+0x70)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 7" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 7" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 7" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 7" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 8" wgroup.long (0x200+0x80)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 8" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 8" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 8" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 8" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 9" wgroup.long (0x200+0x90)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 9" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 9" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 9" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 9" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 10" wgroup.long (0x200+0xA0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 10" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 10" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 10" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 10" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree "Alternate Channel 11" wgroup.long (0x200+0xB0)++0x13 line.long 0x00 "SOURCE_ADDRESS,Source address register of channel 11" line.long 0x04 "DESTINATION_ADDRESS,Destination address register of channel 11" line.long 0x08 "TRANSFER_LENGTH,Transfer length register for channel 11" hexmask.long.tbyte 0x08 0.--20. 1. " TRANSFER_LENGTH ,Amount of cycles to transfer" line.long 0x0c "CONFIGURATION,Configuration register for channel 11" bitfld.long 0x0C 18. " CIRCULAR_BUFFER ,Channel looping (enable bit never cleared)" "Disabled,Enabled" textline " " bitfld.long 0x0C 17. " COMPANION_CHANNEL_ENABLE ,Companion Channel Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13.--15. " COMPANION_CHANNEL_NR ,Companion Channel Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 12. " INVERT_ENDIANESS ,Endianess inversion" "Not inverted,Inverted" textline " " bitfld.long 0x0C 10.--11. " TRANSFER_SIZE ,Size of each transfer" "Words,Half-words,Bytes,Burst" textline " " bitfld.long 0x0C 5.--9. " READ_SLAVE_NR ,Read Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." textline " " bitfld.long 0x0C 0.--4. " WRITE_SLAVE_NR ,Write Address Incrementation Mode" "Unconditional,Ipint_tx,Ipint_rx,uart_ rx,uart tx,I2c0,I2c1,I2STX0_dma_req_left,I2STX0_dma_req_right,I2STX1_dma_req_left,I2STX1_dma_req_right,I2SRX0_dma_req_left,I2SRX0_dma_req_right,I2SRX1_dma_req_left,I2SRX1_dma_req_right,Reserved,Reserved,lcd_interface_dma_req,spi_tx_dmareq,spi_rx_dmareq,sd_mmc_dmasreq,?..." tree.end tree.end width 23. tree "Global Control Registers" group.long 0x400++0xb line.long 0x00 "ALT_ENABLE,Alternative Enable Register" bitfld.long 0x00 11. " ALT_CH_EN11 ,Channel 11 Enable" "Disabled,Enabled" bitfld.long 0x00 10. " ALT_CH_EN10 ,Channel 10 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ALT_CH_EN9 ,Channel 9 Enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALT_CH_EN8 ,Channel 8 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ALT_CH_EN7 ,Channel 7 Enable" "Disabled,Enabled" bitfld.long 0x00 6. " ALT_CH_EN6 ,Channel 6 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ALT_CH_EN5 ,Channel 5 Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ALT_CH_EN4 ,Channel 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ALT_CH_EN3 ,Channel 3 Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ALT_CH_EN2 ,Channel 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ALT_CH_EN1 ,Channel 1 Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ALT_CH_EN0 ,Channel 0 Enable" "Disabled,Enabled" line.long 0x04 "IRQ_STATUS_CLEAR,IRQ Status Clear Register" eventfld.long 0x04 31. " DMA_ABORT ,DMA abort" "Not occurred,Occurred" eventfld.long 0x04 30. " SOFT_INTERRUPT ,Soft interrupt; scatter gather" "Not occurred,Occurred" textline " " eventfld.long 0x04 23. " HALF_WAY_11 ,Channel 11 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 22. " FINISHED_11 ,Channel 11 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 21. " HALF_WAY_10 ,Channel 10 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 20. " FINISHED_10 ,Channel 10 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 19. " HALF_WAY_9 ,Channel 9 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 18. " FINISHED_9 ,Channel 9 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 17. " HALF_WAY_8 ,Channel 8 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 16. " FINISHED_8 ,Channel 8 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 15. " HALF_WAY_7 ,Channel 7 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 14. " FINISHED_7 ,Channel 7 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 13. " HALF_WAY_6 ,Channel 6 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 12. " FINISHED_6 ,Channel 6 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 11. " HALF_WAY_5 ,Channel 5 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 10. " FINISHED_5 ,Channel 5 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 9. " HALF_WAY_4 ,Channel 4 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 8. " FINISHED_4 ,Channel 4 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 7. " HALF_WAY_3 ,Channel 3 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 6. " FINISHED_3 ,Channel 3 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 5. " HALF_WAY_2 ,Channel 2 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 4. " FINISHED_2 ,Channel 2 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 3. " HALF_WAY_1 ,Channel 1 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 2. " FINISHED_1 ,Channel 1 is finished" "Not occurred,Occurred" textline " " eventfld.long 0x04 1. " HALF_WAY_0 ,Channel 0 is more than half-way" "Not occurred,Occurred" eventfld.long 0x04 0. " FINISHED_0 ,Channel 0 is finished" "Not occurred,Occurred" line.long 0x08 "IRQ_MASK,IRQ Mask Register" bitfld.long 0x08 31. " MASK_DMA_ABORT ,DMA abort interrupt" "Masked,Not masked" bitfld.long 0x08 30. " MASK_SOFT_INTERRUPT ,Soft interrupt; scatter gather interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 23. " MASK_HALF_WAY_11 ,Mask channel 11 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 22. " MASK_FINISHED_11 ,Mask channel 11 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 21. " MASK_HALF_WAY_10 ,Mask channel 10 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 20. " MASK_FINISHED_10 ,Mask channel 10 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 19. " MASK_HALF_WAY_9 ,Mask channel 9 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 18. " MASK_FINISHED_9 ,Mask channel 9 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 17. " MASK_HALF_WAY_8 ,Mask channel 8 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 16. " MASK_FINISHED_8 ,Mask channel 8 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 15. " MASK_HALF_WAY_7 ,Mask channel 7 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 14. " MASK_FINISHED_7 ,Mask channel 7 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 13. " MASK_HALF_WAY_6 ,Mask channel 6 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 12. " MASK_FINISHED_6 ,Mask channel 6 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 11. " MASK_HALF_WAY_5 ,Mask channel 5 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 10. " MASK_FINISHED_5 ,Mask channel 5 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 9. " MASK_HALF_WAY_4 ,Mask channel 4 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 8. " MASK_FINISHED_4 ,Mask channel 4 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 7. " MASK_HALF_WAY_3 ,Mask channel 3 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 6. " MASK_FINISHED_3 ,Mask channel 3 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 5. " MASK_HALF_WAY_2 ,Mask channel 2 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 4. " MASK_FINISHED_2 ,Mask channel 2 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 3. " MASK_HALF_WAY_1 ,Mask channel 1 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 2. " MASK_FINISHED_1 ,Mask channel 1 is finished interrupt" "Masked,Not masked" textline " " bitfld.long 0x08 1. " MASK_HALF_WAY_0 ,Mask channel 0 is more than half-way interrupt" "Masked,Not masked" bitfld.long 0x08 0. " MASK_FINISHED_0 ,Mask channel 0 is finished interrupt" "Masked,Not masked" rgroup.long 0x40C++0x3 line.long 0x00 "TEST_FIFO_RESP_STATUS,Test FIFO Response Status Register" wgroup.long 0x410++0x3 line.long 0x00 "SOFT_INT,Software Interrupt Register" bitfld.long 0x00 0. " ENABLE_SOFT_INTERRUPT ,Soft_interrupt IRQ Enable" "No effect,Enabled" tree.end width 0xb tree.end tree "Interrupt Controller" base ad:0x60000000 width 20. group.long 0x00++0x07 line.long 0x00 "INT_PRIORITYMASK_0,Interrupt Target 0 Priority Threshold" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY_LIMITER ,Priority limiter" line.long 0x04 "INT_PRIORITYMASK_1,Interrupt Target 0 Priority Threshold" hexmask.long.byte 0x04 0.--7. 1. " PRIORITY_LIMITER ,Priority limiter" group.long 0x100++0x07 line.long 0x00 "INT_VECTOR_0,Vector Register for Target 0 (nIRQ)" hexmask.long 0x00 11.--31. 0x800 " TABLE_ADDR ,Table start address" hexmask.long.byte 0x00 3.--10. 1. " INDEX ,Index (interrupt request line)" line.long 0x04 "INT_VECTOR_1,Vector register for target 1 (nFIQ)" hexmask.long 0x04 11.--31. 0x800 " TABLE_ADDR ,Table start address" hexmask.long.byte 0x04 3.--10. 1. " INDEX ,Index (interrupt request line)" rgroup.long 0x200++0x07 line.long 0x00 "INT_PENDING_1_31,Interrupt-pending status register" bitfld.long 0x0 29. " PEND_ISRAM1 ,Interrupt request 29(ISRAM0_MRC_FINISHED) is pending" "No interrupt,Interrupt" bitfld.long 0x0 28. " PEND_ISRAM0 ,Interrupt request 28(ISRAM1_MRC_FINISHED) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 27. " PEND_USB_OTG ,Interrupt request 27(USB_OTG_IRQ) is pending" "No interrupt,Interrupt" bitfld.long 0x0 26. " PEND_MCI ,Interrupt request 26(SD_MMC_INTR) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 25. " PEND_FLASH ,Interrupt request 25(NANDFLASH_CTRL_IRQ_NAND) is pending" "No interrupt,Interrupt" bitfld.long 0x0 24. " PEND_DMA ,Interrupt request 24(DMA_IRQ) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 23. " PEND_SPI_INT ,Interrupt request 23(SPI_INT) is pending" "No interrupt,Interrupt" bitfld.long 0x0 22. " PEND_SPI_OV ,Interrupt request 22(SPI_OV_INT) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 21. " PEND_SPI_RX ,Interrupt request 21(SPI_RX_INT) is pending" "No interrupt,Interrupt" bitfld.long 0x0 20. " PEND_SPI_TX ,Interrupt request 20(SPI_TX_INT) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 19. " PEND_SPI_SMS ,Interrupt request 19(SPI_SMS_INT) is pending" "No interrupt,Interrupt" bitfld.long 0x0 18. " PEND_LCD ,Interrupt request 18(LCD_INTERFACE_IRQ) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 16. " PEND_I2SRX1 ,Interrupt request 16(I2SRX1_IRQ) is pending" "No interrupt,Interrupt" bitfld.long 0x0 15. " PEND_I2SRX0 ,Interrupt request 15(I2SRX0_IRQ) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 14. " PEND_I2STX1 ,Interrupt request 14(I2STX1_IRQ) is pending" "No interrupt,Interrupt" bitfld.long 0x0 13. " PEND_I2STX0 ,Interrupt request 13(I2STX0_IRQ) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 12. " PEND_I2C1 ,Interrupt request 12(I2C1_NINTR) is pending" "No interrupt,Interrupt" bitfld.long 0x0 11. " PEND_I2C0 ,Interrupt request 11(I2C0_NINTR) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 10. " PEND_UART ,Interrupt request 10(UART_INTREQ) is pending" "No interrupt,Interrupt" bitfld.long 0x0 9. " PEND_ADC ,Interrupt request 9(ADC_INT) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 8. " PEND_TIMER3 ,Interrupt request 8(TIMER3_INTCT) is pending" "No interrupt,Interrupt" bitfld.long 0x0 7. " PEND_TIMER2 ,Interrupt request 7(TIMER2_INTCT) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 6. " PEND_TIMER1 ,Interrupt request 6(TIMER1_INTCT) is pending" "No interrupt,Interrupt" bitfld.long 0x0 5. " PEND_TIMER0 ,Interrupt request 5(TIMER0_INTCT) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 4. " PEND_EVENT_ROUTER_3 ,Interrupt request 4(CASCADED_IRQ_3) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " PEND_EVENT_ROUTER_2 ,Interrupt request 3(CASCADED_IRQ_2) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 2. " PEND_EVENT_ROUTER_1 ,Interrupt request 2(CASCADED_IRQ_1) is pending" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " PEND_EVENT_ROUTER_0 ,Interrupt request 1(CASCADED_IRQ_0) is pending" "No interrupt,Interrupt" width 15. rgroup.long 0x300++0x03 line.long 0x00 "INT_FEATURES,Interrupt controller features register" bitfld.long 0x00 16.--21. " T ,Number of targets" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 8.--15. 1. " P ,Number of priorities (minus one)" textline " " hexmask.long.byte 0x00 0.--7. 1. " N ,Number of interrupt requests" group.long 0x404++0x3f line.long 0x0 "INT_REQUEST_1,Interrupt Request 1 (Event Router 0) control register" bitfld.long 0x0 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x0 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x0 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x0 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x0 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x0 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x0 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x4 "INT_REQUEST_2,Interrupt Request 2 (Event Router 1) control register" bitfld.long 0x4 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x4 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x4 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x4 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x4 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x4 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x4 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x4 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x4 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x4 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x8 "INT_REQUEST_3,Interrupt Request 3 (Event Router 2) control register" bitfld.long 0x8 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x8 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x8 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x8 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x8 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x8 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x8 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x8 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x8 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x8 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0xC "INT_REQUEST_4,Interrupt Request 4 (Event Router 3) control register" bitfld.long 0xC 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0xC 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0xC 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0xC 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0xC 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0xC 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0xC 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0xC 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0xC 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0xC 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x10 "INT_REQUEST_5,Interrupt Request 5 (TIMER0) control register" bitfld.long 0x10 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x10 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x10 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x10 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x10 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x10 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x10 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x10 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x14 "INT_REQUEST_6,Interrupt Request 6 (TIMER1) control register" bitfld.long 0x14 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x14 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x14 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x14 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x14 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x14 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x14 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x14 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x14 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x18 "INT_REQUEST_7,Interrupt Request 7 (TIMER2) control register" bitfld.long 0x18 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x18 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x18 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x18 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x18 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x18 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x18 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x18 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x18 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x1C "INT_REQUEST_8,Interrupt Request 8 (TIMER3) control register" bitfld.long 0x1C 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x1C 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x1C 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x1C 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x1C 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x1C 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x1C 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x1C 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x20 "INT_REQUEST_9,Interrupt Request 9 (ADC) control register" bitfld.long 0x20 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x20 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x20 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x20 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x20 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x20 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x20 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x20 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x24 "INT_REQUEST_10,Interrupt Request 10 (UART) control register" bitfld.long 0x24 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x24 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x24 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x24 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x24 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x24 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x24 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x24 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x24 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x24 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x28 "INT_REQUEST_11,Interrupt Request 11 (I2C0) control register" bitfld.long 0x28 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x28 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x28 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x28 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x28 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x28 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x28 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x28 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x28 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x28 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x2C "INT_REQUEST_12,Interrupt Request 12 (I2C1) control register" bitfld.long 0x2C 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x2C 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x2C 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x2C 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x2C 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x2C 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x2C 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x2C 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x2C 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x2C 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x30 "INT_REQUEST_13,Interrupt Request 13 (I2STX0) control register" bitfld.long 0x30 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x30 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x30 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x30 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x30 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x30 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x30 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x30 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x30 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x30 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x34 "INT_REQUEST_14,Interrupt Request 14 (I2STX1) control register" bitfld.long 0x34 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x34 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x34 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x34 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x34 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x34 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x34 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x34 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x34 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x34 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x38 "INT_REQUEST_15,Interrupt Request 15 (I2SRX0) control register" bitfld.long 0x38 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x38 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x38 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x38 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x38 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x38 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x38 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x38 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x38 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x38 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x3C "INT_REQUEST_16,Interrupt Request 16 (I2SRX1) control register" bitfld.long 0x3C 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x3C 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x3C 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x3C 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x3C 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x3C 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x3C 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x3C 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x3C 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x3C 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" group.long 0x448++0x2f line.long 0x0 "INT_REQUEST_18,Interrupt Request 18 (LCD) control register" bitfld.long 0x0 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x0 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x0 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x0 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x0 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x0 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x0 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x4 "INT_REQUEST_19,Interrupt Request 19 (SPI_SMS) control register" bitfld.long 0x4 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x4 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x4 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x4 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x4 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x4 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x4 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x4 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x4 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x4 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x8 "INT_REQUEST_20,Interrupt Request 20 (SPI_TX) control register" bitfld.long 0x8 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x8 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x8 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x8 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x8 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x8 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x8 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x8 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x8 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x8 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0xC "INT_REQUEST_21,Interrupt Request 21 (SPI_RX) control register" bitfld.long 0xC 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0xC 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0xC 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0xC 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0xC 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0xC 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0xC 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0xC 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0xC 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0xC 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x10 "INT_REQUEST_22,Interrupt Request 22 (SPI_OV) control register" bitfld.long 0x10 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x10 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x10 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x10 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x10 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x10 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x10 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x10 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x14 "INT_REQUEST_23,Interrupt Request 23 (SPI) control register" bitfld.long 0x14 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x14 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x14 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x14 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x14 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x14 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x14 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x14 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x14 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x18 "INT_REQUEST_24,Interrupt Request 24 (DMA) control register" bitfld.long 0x18 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x18 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x18 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x18 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x18 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x18 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x18 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x18 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x18 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x18 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x1C "INT_REQUEST_25,Interrupt Request 25 (NANDFLASH) control register" bitfld.long 0x1C 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x1C 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x1C 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x1C 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x1C 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x1C 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x1C 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x1C 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x1C 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x20 "INT_REQUEST_26,Interrupt Request 26 (SD_MMC) control register" bitfld.long 0x20 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x20 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x20 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x20 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x20 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x20 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x20 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x20 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x24 "INT_REQUEST_27,Interrupt Request 27 (USB OTG) control register" bitfld.long 0x24 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x24 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x24 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x24 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x24 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x24 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x24 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x24 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x24 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x24 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x28 "INT_REQUEST_28,Interrupt Request 28 (ISRAM0) control register" bitfld.long 0x28 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x28 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x28 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x28 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x28 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x28 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x28 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x28 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x28 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x28 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" line.long 0x2C "INT_REQUEST_29,Interrupt Request 29 (ISRAM1) control register" bitfld.long 0x2C 31. " PENDING ,Pending interrupt request" "No interrupt,Interrupt" bitfld.long 0x2C 30. " SET_SWINT ,Set software-interrupt request (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x2C 29. " CLR_SWINT ,Clear software-interrupt request (Read as 0)" "No effect,Clear" bitfld.long 0x2C 28. " WE_PRIORITY_LEVEL ,Write-enable priority level (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x2C 27. " WE_TARGET ,Write-enable target (Read as 0)" "Disabled,Enabled" bitfld.long 0x2C 26. " WE_ENABLE ,Write enable (Read as 0)" "Disabled,Enabled" textline " " bitfld.long 0x2C 25. " WE_ACTIVE_LOW ,Write-enable active LOW (Read as 0)" "Disabled,Enabled" bitfld.long 0x2C 17. " ACTIVE_LOW ,Active-LOW interrupt line" "High,Low" textline " " bitfld.long 0x2C 16. " ENABLE ,Enable interrupt request" "Disabled,Enabled" bitfld.long 0x00 8.--13. " TARGET ,Interrupt target" "nIRQ,nFIQ,?..." textline " " hexmask.long.byte 0x2C 0.--7. 1. " PRIORITY_LEVEL ,Interrupt priority level" width 0xB tree.end tree.open "CGU" base ad:0x13004000 width 7. tree "Switch configuration for base clocks" group.long 0x00++0x2f line.long 0x0 "SCR0,Switch Configuration Register for SYS Base" bitfld.long 0x0 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x0 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x0 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x0 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x4 "SCR1,Switch Configuration Register for AHB0_APB0 Base" bitfld.long 0x4 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x4 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x4 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x4 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x8 "SCR2,Switch Configuration Register for AHB0_APB1 Base" bitfld.long 0x8 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x8 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x8 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x8 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0xC "SCR3,Switch Configuration Register for AHB0_APB2 Base" bitfld.long 0xC 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0xC 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0xC 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0xC 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x10 "SCR4,Switch Configuration Register for AHB0_APB3 Base" bitfld.long 0x10 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x10 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x10 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x10 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x14 "SCR5,Switch Configuration Register for PCM Base" bitfld.long 0x14 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x14 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x14 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x14 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x18 "SCR6,Switch Configuration Register for UART Base" bitfld.long 0x18 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x18 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x18 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x18 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x1C "SCR7,Switch Configuration Register for CLK1024FS Base" bitfld.long 0x1C 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x1C 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x1C 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x1C 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x20 "SCR8,Switch Configuration Register for I2SRX_BCK0 Base" bitfld.long 0x20 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x20 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x20 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x20 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x24 "SCR9,Switch Configuration Register for I2SRX_BCK1 Base" bitfld.long 0x24 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x24 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x24 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x24 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x28 "SCR10,Switch Configuration Register for SPI_CLK Base" bitfld.long 0x28 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x28 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x28 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x28 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" line.long 0x2C "SCR11,Switch Configuration Register for SYSCLK_O Base" bitfld.long 0x2C 3. " STOP ,Forces switch in disable mode" "Not stopped,Stopped" bitfld.long 0x2C 2. " RESET ,Asynchronous reset of both switches" "No reset,Reset" bitfld.long 0x2C 1. " ENF2 ,Side 2 of switch enable" "Disabled,Enabled" bitfld.long 0x2C 0. " ENF1 ,Side 1 of switch enable" "Disabled,Enabled" tree.end width 8. tree "Frequency select 1 for base clocks" group.long 0x030++0x2f line.long 0x0 "FS1_0,Frequency Select 1 Register for SYS Base" bitfld.long 0x0 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x4 "FS1_1,Frequency Select 1 Register for AHB0_APB0 Base" bitfld.long 0x4 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x8 "FS1_2,Frequency Select 1 Register for AHB0_APB1 Base" bitfld.long 0x8 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0xC "FS1_3,Frequency Select 1 Register for AHB0_APB2 Base" bitfld.long 0xC 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x10 "FS1_4,Frequency Select 1 Register for AHB0_APB3 Base" bitfld.long 0x10 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x14 "FS1_5,Frequency Select 1 Register for PCM Base" bitfld.long 0x14 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x18 "FS1_6,Frequency Select 1 Register for UART Base" bitfld.long 0x18 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x1C "FS1_7,Frequency Select 1 Register for CLK1024FS Base" bitfld.long 0x1C 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x20 "FS1_8,Frequency Select 1 Register for I2SRX_BCK0 Base" bitfld.long 0x20 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x24 "FS1_9,Frequency Select 1 Register for I2SRX_BCK1 Base" bitfld.long 0x24 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x28 "FS1_10,Frequency Select 1 Register for SPI_CLK Base" bitfld.long 0x28 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x2C "FS1_11,Frequency Select 1 Register for SYSCLK_O Base" bitfld.long 0x2C 0.--2. " FS1 ,Input frequency for side 1 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." tree.end tree "Frequency select 2 for base clocks" group.long 0x060++0x2f line.long 0x0 "FS2_0,Frequency Select 2 Register for SYS Base" bitfld.long 0x0 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x4 "FS2_1,Frequency Select 2 Register for AHB0_APB0 Base" bitfld.long 0x4 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x8 "FS2_2,Frequency Select 2 Register for AHB0_APB1 Base" bitfld.long 0x8 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0xC "FS2_3,Frequency Select 2 Register for AHB0_APB2 Base" bitfld.long 0xC 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x10 "FS2_4,Frequency Select 2 Register for AHB0_APB3 Base" bitfld.long 0x10 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x14 "FS2_5,Frequency Select 2 Register for PCM Base" bitfld.long 0x14 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x18 "FS2_6,Frequency Select 2 Register for UART Base" bitfld.long 0x18 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x1C "FS2_7,Frequency Select 2 Register for CLK1024FS Base" bitfld.long 0x1C 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x20 "FS2_8,Frequency Select 2 Register for I2SRX_BCK0 Base" bitfld.long 0x20 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x24 "FS2_9,Frequency Select 2 Register for I2SRX_BCK1 Base" bitfld.long 0x24 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x28 "FS2_10,Frequency Select 2 Register for SPI_CLK Base" bitfld.long 0x28 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." line.long 0x2C "FS2_11,Frequency Select 2 Register for SYSCLK_O Base" bitfld.long 0x2C 0.--2. " FS2 ,Input frequency for side 2 of the frequency switch" "ffast 12 MHz,I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HPPLL0 (Audio/I2S),HPPLL1 (System),?..." tree.end width 7. tree "Switch status for base clocks" rgroup.long 0x090++0x2f line.long 0x0 "SSR0,Switch Status Register for SYS Base" hexmask.long.byte 0x0 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x0 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x0 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x4 "SSR1,Switch Status Register for AHB0_APB0 Base" hexmask.long.byte 0x4 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x4 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x4 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x8 "SSR2,Switch Status Register for AHB0_APB1 Base" hexmask.long.byte 0x8 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x8 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x8 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0xC "SSR3,Switch Status Register for AHB0_APB2 Base" hexmask.long.byte 0xC 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0xC 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0xC 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x10 "SSR4,Switch Status Register for AHB0_APB3 Base" hexmask.long.byte 0x10 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x10 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x10 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x14 "SSR5,Switch Status Register for PCM Base" hexmask.long.byte 0x14 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x14 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x14 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x18 "SSR6,Switch Status Register for UART Base" hexmask.long.byte 0x18 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x18 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x18 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x1C "SSR7,Switch Status Register for CLK1024FS Base" hexmask.long.byte 0x1C 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x1C 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x1C 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x20 "SSR8,Switch Status Register for I2SRX_BCK0 Base" hexmask.long.byte 0x20 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x20 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x20 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x24 "SSR9,Switch Status Register for I2SRX_BCK1 Base" hexmask.long.byte 0x24 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x24 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x24 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x28 "SSR10,Switch Status Register for SPI_CLK Base" hexmask.long.byte 0x28 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x28 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x28 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" line.long 0x2C "SSR11,Switch Status Register for SYSCLK_O Base" hexmask.long.byte 0x2C 2.--4. 1. " FS ,Feedback of currently used frequency selection" bitfld.long 0x2C 1. " FS2STAT ,Side 2 of the frequency switch enable" "Disabled,Enabled" bitfld.long 0x2C 0. " F1STAT ,Side 1 of the frequency switch enable" "Disabled,Enabled" tree.end tree "Power control" group.long 0xc0++0x2f line.long 0x0 "PCR0,Power Control Register for APB0_CLK" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR1,Power Control Register for APB1_CLK" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR2,Power Control Register for APB2_CLK" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR3,Power Control Register for APB3_CLK" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR4,Power Control Register for APB4_CLK" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR5,Power Control Register for AHB_TO_INTC_CLK" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR6,Power Control Register for AHB0_CLK" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR7,Power Control Register for EBI_CLK" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR8,Power Control Register for DMA_PCLK" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x24 "PCR9,Power Control Register for DMA_CLK_GATED" bitfld.long 0x24 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x24 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x24 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x24 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x24 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x28 "PCR10,Power Control Register for NANDFLASH_S0_CLK" bitfld.long 0x28 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x28 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x28 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x28 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x28 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x2C "PCR11,Power Control Register for NANDFLASH_ECC_CLK" bitfld.long 0x2C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x2C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x2C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x2C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" sif (cpu()=="LPC3130") group.long 0xf0++0x2b line.long 0x0 "PCR13,Power Control Register for NANDFLASH_NAND_CLK" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR14,Power Control Register for NANDFLASH_PCLK" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR15,Power Control Register for CLOCK_OUT" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR16,Power Control Register for ARM926_CORE_CLK" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR17,Power Control Register for ARM926_BUSIF_CLK" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR18,Power Control Register for ARM926_RETIME_CLK" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR19,Power Control Register for SD_MMC_HCLK" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR20,Power Control Register for SD_MMC_CCLK_IN" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR21,Power Control Register for USB_OTG_AHB_CLK" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x24 "PCR22,Power Control Register for ISRAM0_CLK" bitfld.long 0x24 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x24 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x24 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x24 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x24 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x28 "PCR23,Power Control Register for RED_CTL_RSCLK" bitfld.long 0x28 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x28 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x28 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x28 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x28 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" group.long 0x124++0x33 line.long 0x0 "PCR25,Power Control Register for ISROM_CLK" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR26,Power Control Register for MPMC_CFG_CLK" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR27,Power Control Register for MPMC_CFG_CLK2" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR28,Power Control Register for MPMC_CFG_CLK3" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR29,Power Control Register for INTC_CLK" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR30,Power Control Register for AHB_TO_APB0_PCLK" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR31,Power Control Register for EVENT_ROUTER_PCLK" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR32,Power Control Register for ADC_PCLK" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR33,Power Control Register for ADC_CLK" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x24 "PCR34,Power Control Register for WDOG_PCLK" bitfld.long 0x24 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x24 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x24 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x24 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x24 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x28 "PCR35,Power Control Register for IOCONF_PCLK" bitfld.long 0x28 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x28 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x28 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x28 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x28 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x2C "PCR36,Power Control Register for CGU_PCLK" bitfld.long 0x2C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x2C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x2C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x2C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x30 "PCR37,Power Control Register for SYSCREG_PCLK" bitfld.long 0x30 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x30 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x30 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x30 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" else group.long 0xf0++0x63 line.long 0x0 "PCR13,Power Control Register for NANDFLASH_NAND_CLK" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR14,Power Control Register for NANDFLASH_PCLK" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR15,Power Control Register for CLOCK_OUT" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR16,Power Control Register for ARM926_CORE_CLK" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR17,Power Control Register for ARM926_BUSIF_CLK" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR18,Power Control Register for ARM926_RETIME_CLK" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR19,Power Control Register for SD_MMC_HCLK" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR20,Power Control Register for SD_MMC_CCLK_IN" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR21,Power Control Register for USB_OTG_AHB_CLK" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x24 "PCR22,Power Control Register for ISRAM0_CLK" bitfld.long 0x24 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x24 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x24 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x24 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x24 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x28 "PCR23,Power Control Register for RED_CTL_RSCLK" bitfld.long 0x28 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x28 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x28 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x28 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x28 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x2C "PCR24,Power Control Register for ISRAM1_CLK" bitfld.long 0x2C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x2C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x2C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x2C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x30 "PCR25,Power Control Register for ISROM_CLK" bitfld.long 0x30 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x30 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x30 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x30 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x34 "PCR26,Power Control Register for MPMC_CFG_CLK" bitfld.long 0x34 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x34 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x34 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x34 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x34 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x38 "PCR27,Power Control Register for MPMC_CFG_CLK2" bitfld.long 0x38 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x38 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x38 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x38 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x38 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x3C "PCR28,Power Control Register for MPMC_CFG_CLK3" bitfld.long 0x3C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x3C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x3C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x3C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x3C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x40 "PCR29,Power Control Register for INTC_CLK" bitfld.long 0x40 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x40 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x40 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x40 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x40 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x44 "PCR30,Power Control Register for AHB_TO_APB0_PCLK" bitfld.long 0x44 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x44 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x44 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x44 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x44 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x48 "PCR31,Power Control Register for EVENT_ROUTER_PCLK" bitfld.long 0x48 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x48 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x48 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x48 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x48 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4C "PCR32,Power Control Register for ADC_PCLK" bitfld.long 0x4C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x50 "PCR33,Power Control Register for ADC_CLK" bitfld.long 0x50 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x50 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x50 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x50 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x50 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x54 "PCR34,Power Control Register for WDOG_PCLK" bitfld.long 0x54 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x54 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x54 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x54 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x54 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x58 "PCR35,Power Control Register for IOCONF_PCLK" bitfld.long 0x58 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x58 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x58 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x58 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x58 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x5C "PCR36,Power Control Register for CGU_PCLK" bitfld.long 0x5C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x5C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x5C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x5C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x5C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x60 "PCR37,Power Control Register for SYSCREG_PCLK" bitfld.long 0x60 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x60 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x60 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x60 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x60 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" endif group.long 0x15c++0x73 line.long 0x0 "PCR39,Power Control Register for RNG_PCLK" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR40,Power Control Register for AHB_TO_APB1_PCLK" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR41,Power Control Register for TIMER0_PCLK" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR42,Power Control Register for TIMER1_PCLK" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR43,Power Control Register for TIMER2_PCLK" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR44,Power Control Register for TIMER3_PCLK" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR45,Power Control Register for PWM_PCLK_REGS" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR46,Power Control Register for PWM_CLK" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR47,Power Control Register for I2C0_PCLK" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x24 "PCR48,Power Control Register for I2C1_PCLK" bitfld.long 0x24 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x24 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x24 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x24 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x24 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x28 "PCR49,Power Control Register for AHB_TO_APB2_PCLK" bitfld.long 0x28 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x28 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x28 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x28 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x28 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x2C "PCR50,Power Control Register for PCM_PCLK" bitfld.long 0x2C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x2C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x2C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x2C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x30 "PCR51,Power Control Register for PCM_APB_PCLK" bitfld.long 0x30 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x30 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x30 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x30 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x34 "PCR52,Power Control Register for UART_APB_CLK" bitfld.long 0x34 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x34 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x34 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x34 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x34 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x38 "PCR53,Power Control Register for LCD_PCLK" bitfld.long 0x38 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x38 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x38 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x38 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x38 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x3C "PCR54,Power Control Register for LCD_CLK" bitfld.long 0x3C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x3C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x3C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x3C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x3C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x40 "PCR55,Power Control Register for SPI_PCLK" bitfld.long 0x40 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x40 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x40 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x40 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x40 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x44 "PCR56,Power Control Register for SPI_PCLK_GATED" bitfld.long 0x44 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x44 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x44 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x44 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x44 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x48 "PCR57,Power Control Register for AHB_TO_APB3_PCLK" bitfld.long 0x48 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x48 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x48 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x48 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x48 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4C "PCR58,Power Control Register for I2S_CFG_PCLK" bitfld.long 0x4C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x50 "PCR59,Power Control Register for EDGE_DET_PCLK" bitfld.long 0x50 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x50 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x50 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x50 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x50 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x54 "PCR60,Power Control Register for I2STX_FIFO_0_PCLK" bitfld.long 0x54 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x54 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x54 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x54 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x54 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x58 "PCR61,Power Control Register for I2STX_IF_0_PCLK" bitfld.long 0x58 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x58 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x58 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x58 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x58 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x5C "PCR62,Power Control Register for I2STX_FIFO_1_PCLK" bitfld.long 0x5C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x5C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x5C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x5C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x5C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x60 "PCR63,Power Control Register for I2STX_IF_1_PCLK" bitfld.long 0x60 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x60 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x60 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x60 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x60 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x64 "PCR64,Power Control Register for I2SRX_FIFO_0_PCLK" bitfld.long 0x64 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x64 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x64 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x64 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x64 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x68 "PCR65,Power Control Register for I2SRX_IF_0_PCLK" bitfld.long 0x68 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x68 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x68 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x68 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x68 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x6C "PCR66,Power Control Register for I2SRX_FIFO_1_PCLK" bitfld.long 0x6C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x6C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x6C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x6C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x6C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x70 "PCR67,Power Control Register for I2SRX_IF_1_PCLK" bitfld.long 0x70 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x70 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x70 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x70 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x70 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" group.long 0x21c++0x23 line.long 0x0 "PCR71,Power Control Register for PCM_CLK_IP" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR72,Power Control Register for UART_U_CLK" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR73,Power Control Register for I2S_EDGE_DETECT_CLK" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR74,Power Control Register for I2STX_BCK0_N" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR75,Power Control Register for I2STX_WS0" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR76,Power Control Register for I2STX_CLK0" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR77,Power Control Register for I2STX_BCK1_N" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR78,Power Control Register for I2STX_WS1" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR79,Power Control Register for CLK_256FS" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" group.long 0x1dc++0x23 line.long 0x0 "PCR87,Power Control Register for I2SRX_BCK0_N" bitfld.long 0x0 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x0 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x0 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x0 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x4 "PCR88,Power Control Register for I2SRX_WS0" bitfld.long 0x4 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x4 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x4 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x4 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x8 "PCR89,Power Control Register for I2SRX_BCK1_N" bitfld.long 0x8 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x8 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x8 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x8 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0xC "PCR90,Power Control Register for I2SRX_WS1" bitfld.long 0xC 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0xC 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0xC 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0xC 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x10 "PCR91,Power Control Register for I2SRX_BCK0" bitfld.long 0x10 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x10 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x10 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x10 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x14 "PCR92,Power Control Register for I2SRX_BCK1" bitfld.long 0x14 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x14 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x14 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x14 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x18 "PCR93,Power Control Register for SPI_CLK" bitfld.long 0x18 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x18 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x18 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x18 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x1C "PCR94,Power Control Register for SPI_CLK_GATED" bitfld.long 0x1C 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x1C 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x1C 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x1C 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" line.long 0x20 "PCR95,Power Control Register for SYSCLK_O" bitfld.long 0x20 4. " ENOUT_EN ,Internal output 'enableout' enable" "Disabled,Enabled" bitfld.long 0x20 3. " EXTEN_EN ,Clock under control of a signal from the target module or submodule" "Disabled,Enabled" bitfld.long 0x20 2. " WAKE_EN ,Enable by wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " AUTO ,Automatic control of clock output" "On,Off" bitfld.long 0x20 0. " PCRUN ,Output clock of the spreading stage enable" "Disabled,Enabled" tree.end tree "Power status" group.long 0x230++0x2f line.long 0x0 "PSR0,Power Statusl Register for APB0_CLK" bitfld.long 0x0 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x0 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4 "PSR1,Power Statusl Register for APB1_CLK" bitfld.long 0x4 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x8 "PSR2,Power Statusl Register for APB2_CLK" bitfld.long 0x8 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x8 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0xC "PSR3,Power Statusl Register for APB3_CLK" bitfld.long 0xC 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0xC 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x10 "PSR4,Power Statusl Register for APB4_CLK" bitfld.long 0x10 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x10 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x14 "PSR5,Power Statusl Register for AHB_TO_INTC_CLK" bitfld.long 0x14 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x14 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x18 "PSR6,Power Statusl Register for AHB0_CLK" bitfld.long 0x18 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x18 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x1C "PSR7,Power Statusl Register for EBI_CLK" bitfld.long 0x1C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x1C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x20 "PSR8,Power Statusl Register for DMA_PCLK" bitfld.long 0x20 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x20 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x24 "PSR9,Power Statusl Register for DMA_CLK_GATED" bitfld.long 0x24 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x24 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x28 "PSR10,Power Statusl Register for NANDFLASH_S0_CLK" bitfld.long 0x28 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x28 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x2C "PSR11,Power Statusl Register for NANDFLASH_ECC_CLK" bitfld.long 0x2C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x2C 0. " ACTIVE ,Clock status" "Inactive,Active" group.long 0x264++0x63 line.long 0x0 "PSR13,Power Statusl Register for NANDFLASH_NAND_CLK" bitfld.long 0x0 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x0 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4 "PSR14,Power Statusl Register for NANDFLASH_PCLK" bitfld.long 0x4 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x8 "PSR15,Power Statusl Register for CLOCK_OUT" bitfld.long 0x8 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x8 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0xC "PSR16,Power Statusl Register for ARM926_CORE_CLK" bitfld.long 0xC 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0xC 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x10 "PSR17,Power Statusl Register for ARM926_BUSIF_CLK" bitfld.long 0x10 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x10 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x14 "PSR18,Power Statusl Register for ARM926_RETIME_CLK" bitfld.long 0x14 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x14 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x18 "PSR19,Power Statusl Register for SD_MMC_HCLK" bitfld.long 0x18 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x18 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x1C "PSR20,Power Statusl Register for SD_MMC_CCLK_IN" bitfld.long 0x1C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x1C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x20 "PSR21,Power Statusl Register for USB_OTG_AHB_CLK" bitfld.long 0x20 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x20 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x24 "PSR22,Power Statusl Register for ISRAM0_CLK" bitfld.long 0x24 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x24 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x28 "PSR23,Power Statusl Register for RED_CTL_RSCLK" bitfld.long 0x28 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x28 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x2C "PSR24,Power Statusl Register for ISRAM1_CLK" bitfld.long 0x2C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x2C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x30 "PSR25,Power Statusl Register for ISROM_CLK" bitfld.long 0x30 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x30 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x34 "PSR26,Power Statusl Register for MPMC_CFG_CLK" bitfld.long 0x34 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x34 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x38 "PSR27,Power Statusl Register for MPMC_CFG_CLK2" bitfld.long 0x38 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x38 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x3C "PSR28,Power Statusl Register for MPMC_CFG_CLK3" bitfld.long 0x3C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x3C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x40 "PSR29,Power Statusl Register for INTC_CLK" bitfld.long 0x40 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x40 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x44 "PSR30,Power Statusl Register for AHB_TO_APB0_PCLK" bitfld.long 0x44 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x44 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x48 "PSR31,Power Statusl Register for EVENT_ROUTER_PCLK" bitfld.long 0x48 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x48 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4C "PSR32,Power Statusl Register for ADC_PCLK" bitfld.long 0x4C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x50 "PSR33,Power Statusl Register for ADC_CLK" bitfld.long 0x50 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x50 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x54 "PSR34,Power Statusl Register for WDOG_PCLK" bitfld.long 0x54 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x54 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x58 "PSR35,Power Statusl Register for IOCONF_PCLK" bitfld.long 0x58 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x58 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x5C "PSR36,Power Statusl Register for CGU_PCLK" bitfld.long 0x5C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x5C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x60 "PSR37,Power Statusl Register for SYSCREG_PCLK" bitfld.long 0x60 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x60 0. " ACTIVE ,Clock status" "Inactive,Active" group.long 0x2CC++0x73 line.long 0x0 "PSR39,Power Statusl Register for RNG_PCLK" bitfld.long 0x0 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x0 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4 "PSR40,Power Statusl Register for AHB_TO_APB1_PCLK" bitfld.long 0x4 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x8 "PSR41,Power Statusl Register for TIMER0_PCLK" bitfld.long 0x8 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x8 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0xC "PSR42,Power Statusl Register for TIMER1_PCLK" bitfld.long 0xC 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0xC 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x10 "PSR43,Power Statusl Register for TIMER2_PCLK" bitfld.long 0x10 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x10 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x14 "PSR44,Power Statusl Register for TIMER3_PCLK" bitfld.long 0x14 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x14 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x18 "PSR45,Power Statusl Register for PWM_PCLK_REGS" bitfld.long 0x18 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x18 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x1C "PSR46,Power Statusl Register for PWM_CLK" bitfld.long 0x1C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x1C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x20 "PSR47,Power Statusl Register for I2C0_PCLK" bitfld.long 0x20 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x20 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x24 "PSR48,Power Statusl Register for I2C1_PCLK" bitfld.long 0x24 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x24 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x28 "PSR49,Power Statusl Register for AHB_TO_APB2_PCLK" bitfld.long 0x28 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x28 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x2C "PSR50,Power Statusl Register for PCM_PCLK" bitfld.long 0x2C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x2C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x30 "PSR51,Power Statusl Register for PCM_APB_PCLK" bitfld.long 0x30 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x30 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x34 "PSR52,Power Statusl Register for UART_APB_CLK" bitfld.long 0x34 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x34 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x38 "PSR53,Power Statusl Register for LCD_PCLK" bitfld.long 0x38 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x38 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x3C "PSR54,Power Statusl Register for LCD_CLK" bitfld.long 0x3C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x3C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x40 "PSR55,Power Statusl Register for SPI_PCLK" bitfld.long 0x40 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x40 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x44 "PSR56,Power Statusl Register for SPI_PCLK_GATED" bitfld.long 0x44 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x44 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x48 "PSR57,Power Statusl Register for AHB_TO_APB3_PCLK" bitfld.long 0x48 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x48 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4C "PSR58,Power Statusl Register for I2S_CFG_PCLK" bitfld.long 0x4C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x50 "PSR59,Power Statusl Register for EDGE_DET_PCLK" bitfld.long 0x50 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x50 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x54 "PSR60,Power Statusl Register for I2STX_FIFO_0_PCLK" bitfld.long 0x54 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x54 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x58 "PSR61,Power Statusl Register for I2STX_IF_0_PCLK" bitfld.long 0x58 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x58 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x5C "PSR62,Power Statusl Register for I2STX_FIFO_1_PCLK" bitfld.long 0x5C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x5C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x60 "PSR63,Power Statusl Register for I2STX_IF_1_PCLK" bitfld.long 0x60 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x60 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x64 "PSR64,Power Statusl Register for I2SRX_FIFO_0_PCLK" bitfld.long 0x64 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x64 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x68 "PSR65,Power Statusl Register for I2SRX_IF_0_PCLK" bitfld.long 0x68 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x68 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x6C "PSR66,Power Statusl Register for I2SRX_FIFO_1_PCLK" bitfld.long 0x6C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x6C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x70 "PSR67,Power Statusl Register for I2SRX_IF_1_PCLK" bitfld.long 0x70 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x70 0. " ACTIVE ,Clock status" "Inactive,Active" group.long 0x34C++0x23 line.long 0x0 "PSR71,Power Statusl Register for PCM_CLK_IP" bitfld.long 0x0 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x0 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4 "PSR72,Power Statusl Register for UART_U_CLK" bitfld.long 0x4 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x8 "PSR73,Power Statusl Register for I2S_EDGE_DETECT_CLK" bitfld.long 0x8 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x8 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0xC "PSR74,Power Statusl Register for I2STX_BCK0_N" bitfld.long 0xC 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0xC 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x10 "PSR75,Power Statusl Register for I2STX_WS0" bitfld.long 0x10 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x10 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x14 "PSR76,Power Statusl Register for I2STX_CLK0" bitfld.long 0x14 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x14 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x18 "PSR77,Power Statusl Register for I2STX_BCK1_N" bitfld.long 0x18 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x18 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x1C "PSR78,Power Statusl Register for I2STX_WS1" bitfld.long 0x1C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x1C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x20 "PSR79,Power Statusl Register for CLK_256FS" bitfld.long 0x20 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x20 0. " ACTIVE ,Clock status" "Inactive,Active" group.long 0x38C++0x23 line.long 0x0 "PSR87,Power Statusl Register for I2SRX_BCK0_N" bitfld.long 0x0 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x0 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x4 "PSR88,Power Statusl Register for I2SRX_WS0" bitfld.long 0x4 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x4 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x8 "PSR89,Power Statusl Register for I2SRX_BCK1_N" bitfld.long 0x8 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x8 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0xC "PSR90,Power Statusl Register for I2SRX_WS1" bitfld.long 0xC 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0xC 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x10 "PSR91,Power Statusl Register for I2SRX_BCK0" bitfld.long 0x10 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x10 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x14 "PSR92,Power Statusl Register for I2SRX_BCK1" bitfld.long 0x14 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x14 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x18 "PSR93,Power Statusl Register for SPI_CLK" bitfld.long 0x18 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x18 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x1C "PSR94,Power Statusl Register for SPI_CLK_GATED" bitfld.long 0x1C 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x1C 0. " ACTIVE ,Clock status" "Inactive,Active" line.long 0x20 "PSR95,Power Statusl Register for SYSCLK_O" bitfld.long 0x20 1. " WAKEUP ,Wakeup condition for this clock" "Disabled,Enabled" bitfld.long 0x20 0. " ACTIVE ,Clock status" "Inactive,Active" tree.end tree "Enable select" group.long 0x3A0++0x2f line.long 0x0 "ESR0,Enable Select Register for APB0_CLK" bitfld.long 0x0 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x4 "ESR1,Enable Select Register for APB1_CLK" bitfld.long 0x4 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x8 "ESR2,Enable Select Register for APB2_CLK" bitfld.long 0x8 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0xC "ESR3,Enable Select Register for APB3_CLK" bitfld.long 0xC 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x10 "ESR4,Enable Select Register for APB4_CLK" bitfld.long 0x10 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x14 "ESR5,Enable Select Register for AHB_TO_INTC_CLK" bitfld.long 0x14 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x18 "ESR6,Enable Select Register for AHB0_CLK" bitfld.long 0x18 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x1C "ESR7,Enable Select Register for EBI_CLK" bitfld.long 0x1C 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x20 "ESR8,Enable Select Register for DMA_PCLK" bitfld.long 0x20 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x20 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x24 "ESR9,Enable Select Register for DMA_CLK_GATED" bitfld.long 0x24 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x24 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x28 "ESR10,Enable Select Register for NANDFLASH_S0_CLK" bitfld.long 0x28 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x28 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x2C "ESR11,Enable Select Register for NANDFLASH_ECC_CLK" bitfld.long 0x2C 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x2C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x3D4++0x43 line.long 0x0 "ESR13,Enable Select Register for NANDFLASH_NAND_CLK" bitfld.long 0x0 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x4 "ESR14,Enable Select Register for NANDFLASH_PCLK" bitfld.long 0x4 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x8 "ESR15,Enable Select Register for CLOCK_OUT" bitfld.long 0x8 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0xC "ESR16,Enable Select Register for ARM926_CORE_CLK" bitfld.long 0xC 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x10 "ESR17,Enable Select Register for ARM926_BUSIF_CLK" bitfld.long 0x10 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x14 "ESR18,Enable Select Register for ARM926_RETIME_CLK" bitfld.long 0x14 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x18 "ESR19,Enable Select Register for SD_MMC_HCLK" bitfld.long 0x18 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x1C "ESR20,Enable Select Register for SD_MMC_CCLK_IN" bitfld.long 0x1C 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x20 "ESR21,Enable Select Register for USB_OTG_AHB_CLK" bitfld.long 0x20 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x20 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x24 "ESR22,Enable Select Register for ISRAM0_CLK" bitfld.long 0x24 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x24 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x28 "ESR23,Enable Select Register for RED_CTL_RSCLK" bitfld.long 0x28 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x28 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x2C "ESR24,Enable Select Register for ISRAM1_CLK" bitfld.long 0x2C 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x2C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x30 "ESR25,Enable Select Register for ISROM_CLK" bitfld.long 0x30 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x30 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x34 "ESR26,Enable Select Register for MPMC_CFG_CLK" bitfld.long 0x34 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x34 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x38 "ESR27,Enable Select Register for MPMC_CFG_CLK2" bitfld.long 0x38 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x38 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x3C "ESR28,Enable Select Register for MPMC_CFG_CLK3" bitfld.long 0x3C 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x3C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x40 "ESR29,Enable Select Register for INTC_CLK" bitfld.long 0x40 1.--3. " ESR_SEL ,Fractional divider select" "FDC0,FDC1,FDC2,FDC3,FDC4,FDC5,FDC6,?..." bitfld.long 0x40 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x418++0x1f line.long 0x0 "ESR30,Enable Select Register for AHB_TO_APB0_PCLK" bitfld.long 0x0 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x4 "ESR31,Enable Select Register for EVENT_ROUTER_PCLK" bitfld.long 0x4 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x8 "ESR32,Enable Select Register for ADC_PCLK" bitfld.long 0x8 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0xC "ESR33,Enable Select Register for ADC_CLK" bitfld.long 0xC 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x10 "ESR34,Enable Select Register for WDOG_PCLK" bitfld.long 0x10 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x14 "ESR35,Enable Select Register for IOCONF_PCLK" bitfld.long 0x14 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x18 "ESR36,Enable Select Register for CGU_PCLK" bitfld.long 0x18 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x1C "ESR37,Enable Select Register for SYSCREG_PCLK" bitfld.long 0x1C 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x43C++0x3 line.long 0x00 "ESR39,Enable Select Register for RNG_PCLK" bitfld.long 0x00 1. " ESR_SEL ,Fractional divider select" "FDC7,FDC8" bitfld.long 0x00 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x440++0x27 line.long 0x0 "ESR40,Enable Select Register for AHB_TO_APB1_PCLK" bitfld.long 0x0 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x4 "ESR41,Enable Select Register for TIMER0_PCLK" bitfld.long 0x4 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x8 "ESR42,Enable Select Register for TIMER1_PCLK" bitfld.long 0x8 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0xC "ESR43,Enable Select Register for TIMER2_PCLK" bitfld.long 0xC 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x10 "ESR44,Enable Select Register for TIMER3_PCLK" bitfld.long 0x10 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x14 "ESR45,Enable Select Register for PWM_PCLK" bitfld.long 0x14 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x18 "ESR46,Enable Select Register for PWM_PCLK_REGS" bitfld.long 0x18 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x1C "ESR47,Enable Select Register for PWM_CLK" bitfld.long 0x1C 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x20 "ESR48,Enable Select Register for I2C0_PCLK" bitfld.long 0x20 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x20 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x24 "ESR49,Enable Select Register for I2C1_PCLK" bitfld.long 0x24 1. " ESR_SEL ,Fractional divider select" "FDC9,FDC10" bitfld.long 0x24 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x468++0x1f line.long 0x0 "ESR50,Enable Select Register for AHB_TO_APB2_PCLK" bitfld.long 0x0 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x4 "ESR51,Enable Select Register for PCM_PCLK" bitfld.long 0x4 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x8 "ESR52,Enable Select Register for PCM_APB_PCLK" bitfld.long 0x8 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0xC "ESR53,Enable Select Register for UART_APB_CLK" bitfld.long 0xC 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x10 "ESR54,Enable Select Register for LCD_PCLK" bitfld.long 0x10 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x14 "ESR55,Enable Select Register for LCD_CLK" bitfld.long 0x14 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x18 "ESR56,Enable Select Register for SPI_PCLK" bitfld.long 0x18 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x1C "ESR57,Enable Select Register for SPI_PCLK_GATED" bitfld.long 0x1C 1.--2. " ESR_SEL ,Fractional divider select" "FDC11,FDC12,FDC13,?..." bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x488++0x2b line.long 0x0 "ESR58,Enable Select Register for AHB_TO_APB3_PCLK" bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x4 "ESR59,Enable Select Register for I2S_CFG_PCLK" bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x8 "ESR60,Enable Select Register for EDGE_DET_PCLK" bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0xC "ESR61,Enable Select Register for I2STX_FIFO_0_PCLK" bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x10 "ESR62,Enable Select Register for I2STX_IF_0_PCLK" bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x14 "ESR63,Enable Select Register for I2STX_FIFO_1_PCLK" bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x18 "ESR64,Enable Select Register for I2STX_IF_1_PCLK" bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x1C "ESR65,Enable Select Register for I2SRX_FIFO_0_PCLK" bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x20 "ESR66,Enable Select Register for I2SRX_IF_0_PCLK" bitfld.long 0x20 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x24 "ESR67,Enable Select Register for I2SRX_FIFO_1_PCLK" bitfld.long 0x24 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x28 "ESR68,Enable Select Register for I2SRX_IF_1_PCLK" bitfld.long 0x28 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" group.long 0x4BC++0x7 line.long 0x0 "ESR71,Enable Select Register for PCM_CLK_IP" bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" line.long 0x4 "ESR72,Enable Select Register for UART_U_CLK" bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider (FDC14/FDC15/FDC16)" "Disabled,Enabled" group.long 0x4C4++0x2b line.long 0x0 "ESR73,Enable Select Register for I2S_EDGE_DETECT_CLK" bitfld.long 0x0 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x4 "ESR74,Enable Select Register for I2STX_BCK0_N" bitfld.long 0x4 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x8 "ESR75,Enable Select Register for I2STX_WS0" bitfld.long 0x8 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x8 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0xC "ESR76,Enable Select Register for I2STX_CLK0" bitfld.long 0xC 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0xC 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x10 "ESR77,Enable Select Register for I2STX_BCK1_N" bitfld.long 0x10 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x10 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x14 "ESR78,Enable Select Register for I2STX_WS1" bitfld.long 0x14 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x14 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x18 "ESR79,Enable Select Register for CLK_256FS" bitfld.long 0x18 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x18 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x1C "ESR80,Enable Select Register for I2SRX_BCK0_N" bitfld.long 0x1C 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x1C 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x20 "ESR81,Enable Select Register for I2SRX_WS0" bitfld.long 0x20 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x20 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x24 "ESR82,Enable Select Register for I2SRX_BCK1_N" bitfld.long 0x24 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x24 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" line.long 0x28 "ESR83,Enable Select Register for I2SRX_WS1" bitfld.long 0x28 1.--3. " ESR_SEL ,Fractional divider select" "FDC17,FDC18,FDC19,FDC20,FDC21,FDC22,?..." bitfld.long 0x28 0. " ESR_EN ,Enable generated from the fractional divider" "Disabled,Enabled" group.long 0x4FC++0x7 line.long 0x0 "ESR87,Enable Select Register for I2SRX_BCK0" bitfld.long 0x0 0. " ESR_EN ,Enable generated from the fractional divider (FDC23)" "Disabled,Enabled" line.long 0x4 "ESR88,Enable Select Register for I2SRX_BCK1" bitfld.long 0x4 0. " ESR_EN ,Enable generated from the fractional divider (FDC23)" "Disabled,Enabled" tree.end tree "Base Control for SYS Base" group.long 0x504++0x0f line.long 0x0 "BCR0,Base Control Register for SYS" bitfld.long 0x0 0. " FDRUN ,Operation of all the Fractional Dividers" "Disabled,Enabled" line.long 0x4 "BCR1,Base Control Register for AHB0_APB0" bitfld.long 0x4 0. " FDRUN ,Operation of all the Fractional Dividers" "Disabled,Enabled" line.long 0x8 "BCR2,Base Control Register for AHB0_APB1" bitfld.long 0x8 0. " FDRUN ,Operation of all the Fractional Dividers" "Disabled,Enabled" line.long 0xC "BCR3,Base Control Register for AHB0_APB2" bitfld.long 0xC 0. " FDRUN ,Operation of all the Fractional Dividers" "Disabled,Enabled" group.long 0x514++0x03 line.long 0x00 "BCR7,Base Control Register for CLK1024FS" bitfld.long 0x00 0. " FDRUN ,Operation of all the Fractional Dividers" "Disabled,Enabled" tree.end tree "Fractional Divider Configuration" group.long 0x518++0x5f line.long 0x0 "FDC0,Fractional divider configuration register" hexmask.long.byte 0x0 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x0 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x0 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x0 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x0 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x4 "FDC1,Fractional divider configuration register" hexmask.long.byte 0x4 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x4 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x4 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x4 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x4 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x8 "FDC2,Fractional divider configuration register" hexmask.long.byte 0x8 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x8 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x8 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x8 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x8 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0xC "FDC3,Fractional divider configuration register" hexmask.long.byte 0xC 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0xC 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0xC 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0xC 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0xC 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x10 "FDC4,Fractional divider configuration register" hexmask.long.byte 0x10 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x10 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x10 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x10 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x10 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x14 "FDC5,Fractional divider configuration register" hexmask.long.byte 0x14 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x14 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x14 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x14 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x14 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x18 "FDC6,Fractional divider configuration register" hexmask.long.byte 0x18 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x18 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x18 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x18 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x18 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x1C "FDC7,Fractional divider configuration register" hexmask.long.byte 0x1C 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x1C 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x1C 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x1C 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x1C 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x20 "FDC8,Fractional divider configuration register" hexmask.long.byte 0x20 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x20 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x20 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x20 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x20 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x24 "FDC9,Fractional divider configuration register" hexmask.long.byte 0x24 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x24 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x24 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x24 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x24 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x28 "FDC10,Fractional divider configuration register" hexmask.long.byte 0x28 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x28 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x28 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x28 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x28 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x2C "FDC11,Fractional divider configuration register" hexmask.long.byte 0x2C 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x2C 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x2C 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x2C 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x2C 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x30 "FDC12,Fractional divider configuration register" hexmask.long.byte 0x30 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x30 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x30 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x30 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x30 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x34 "FDC13,Fractional divider configuration register" hexmask.long.byte 0x34 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x34 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x34 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x34 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x34 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x38 "FDC14,Fractional divider configuration register" hexmask.long.byte 0x38 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x38 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x38 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x38 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x38 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x3C "FDC15,Fractional divider configuration register" hexmask.long.byte 0x3C 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x3C 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x3C 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x3C 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x3C 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x40 "FDC16,Fractional divider configuration register" hexmask.long.byte 0x40 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x40 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x40 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x40 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x40 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x44 "FDC17,Fractional Divider Configuration Register for Fractional Divider 17 (CLK1024FS)" hexmask.long.word 0x44 16.--28. 1. " MSUB , Modulo subtraction value" hexmask.long.word 0x44 3.--15. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x44 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x44 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x44 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x48 "FDC18,Fractional Divider Configuration Register for Fractional Divider (CLK1024FS)" hexmask.long.byte 0x48 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x48 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x48 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x48 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x48 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x4C "FDC19,Fractional Divider Configuration Register for Fractional Divider (CLK1024FS)" hexmask.long.byte 0x4C 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x4C 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x4C 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x4C 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x4C 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x50 "FDC20,Fractional Divider Configuration Register for Fractional Divider (CLK1024FS)" hexmask.long.byte 0x50 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x50 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x50 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x50 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x50 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x54 "FDC21,Fractional Divider Configuration Register for Fractional Divider (CLK1024FS)" hexmask.long.byte 0x54 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x54 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x54 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x54 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x54 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x58 "FDC22,Fractional Divider Configuration Register for Fractional Divider (CLK1024FS)" hexmask.long.byte 0x58 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x58 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x58 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x58 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x58 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" line.long 0x5C "FDC23,Fractional Divider Configuration Register for Fractional Divider (SPI_CLK)" hexmask.long.byte 0x5C 11.--18. 1. " MSUB , Modulo subtraction value" hexmask.long.byte 0x5C 3.--10. 1. " MADD ,Modulo addition value" textline " " bitfld.long 0x5C 2. " FDCTRL_STRETCH ,Clock stretch enable" "Disabled,Enabled" bitfld.long 0x5C 1. " FDCTRL_RESET ,Fractional divider asynchronous reset" "No reset,Reset" textline " " bitfld.long 0x5C 0. " FDCTRL_RUN ,Fractional divider enable" "Disabled,Enabled" tree.end width 10. tree "Dynamic fractional divider configuration" group.long 0x578++0x1b line.long 0x0 "DYN_FDC0,Dynamic Fractional Divider Configuration Register for Fractional Divider 0" bitfld.long 0x0 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0x0 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0x0 3.--10. 1. " MADD ,MADD value" bitfld.long 0x0 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0x0 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" line.long 0x4 "DYN_FDC1,Dynamic Fractional Divider Configuration Register for Fractional Divider 1" bitfld.long 0x4 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0x4 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0x4 3.--10. 1. " MADD ,MADD value" bitfld.long 0x4 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0x4 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" line.long 0x8 "DYN_FDC2,Dynamic Fractional Divider Configuration Register for Fractional Divider 2" bitfld.long 0x8 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0x8 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0x8 3.--10. 1. " MADD ,MADD value" bitfld.long 0x8 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0x8 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" line.long 0xC "DYN_FDC3,Dynamic Fractional Divider Configuration Register for Fractional Divider 3" bitfld.long 0xC 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0xC 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0xC 3.--10. 1. " MADD ,MADD value" bitfld.long 0xC 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0xC 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0xC 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" line.long 0x10 "DYN_FDC4,Dynamic Fractional Divider Configuration Register for Fractional Divider 4" bitfld.long 0x10 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0x10 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0x10 3.--10. 1. " MADD ,MADD value" bitfld.long 0x10 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0x10 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" line.long 0x14 "DYN_FDC5,Dynamic Fractional Divider Configuration Register for Fractional Divider 5" bitfld.long 0x14 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0x14 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0x14 3.--10. 1. " MADD ,MADD value" bitfld.long 0x14 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0x14 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" line.long 0x18 "DYN_FDC6,Dynamic Fractional Divider Configuration Register for Fractional Divider 6" bitfld.long 0x18 19. " STOP_AUTO_RESET ,Disables auto reset of fractional divider when changing from high-to-low or from low-to-high divider values" "Not stopped,Stopped" hexmask.long.byte 0x18 11.--18. 1. " MSUB ,MSUB value" textline " " hexmask.long.byte 0x18 3.--10. 1. " MADD ,MADD value" bitfld.long 0x18 2. " DYN_FDCTRL_STRETCH ,Stretching option during low speed operations enable" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " DYN_FDC_ALLOW ,Dynamic fractional divider" "Disabled,Enabled" bitfld.long 0x18 0. " DYN_FDCTRL_RUN ,Fractional divider during low speeds enable" "Disabled,Enabled" tree.end tree "Dynamic fractional divider selection" group.long 0x594++0x1b line.long 0x0 "DYN_SEL0,Dynamic Selection Register for Fractional Divider 0" bitfld.long 0x0 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x0 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x0 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x0 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x0 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" line.long 0x4 "DYN_SEL1,Dynamic Selection Register for Fractional Divider 1" bitfld.long 0x4 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x4 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x4 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x4 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x4 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x4 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x4 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x4 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" line.long 0x8 "DYN_SEL2,Dynamic Selection Register for Fractional Divider 2" bitfld.long 0x8 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x8 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x8 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x8 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x8 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x8 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x8 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x8 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" line.long 0xC "DYN_SEL3,Dynamic Selection Register for Fractional Divider 3" bitfld.long 0xC 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0xC 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0xC 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0xC 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0xC 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0xC 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0xC 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0xC 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" line.long 0x10 "DYN_SEL4,Dynamic Selection Register for Fractional Divider 4" bitfld.long 0x10 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x10 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x10 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x10 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x10 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x10 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" line.long 0x14 "DYN_SEL5,Dynamic Selection Register for Fractional Divider 5" bitfld.long 0x14 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x14 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0x14 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x14 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x14 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x14 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x14 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" line.long 0x18 "DYN_SEL6,Dynamic Selection Register for Fractional Divider 6" bitfld.long 0x18 8. " MPMC_REFRESH_REQ ,External SDRAM refresh generator transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x18 7. " ECC_RAM_BUSY ,Hispeed mode during ECC activity of Nandflash Controller" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " USB_OTG_MST_TRANS ,USB OTG transfers can enable high speed" "Disabled,Enabled" bitfld.long 0x18 5. " ARM926_LP_D_READY ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " ARM926_LP_D_TRANS ,ARM926 data transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x18 3. " ARM926_LP_I_READY ,ARM926 instruction last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x18 2. " ARM926_LP_I_TRANS ,ARM926 instruction transfers can enable high-speed" "Disabled,Enabled" bitfld.long 0x18 1. " DMA_READY ,dma last transfers can enable high-speed" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " DMA_TRANS ,dma transfers can enable high-speed" "Disabled,Enabled" tree.end width 14. tree "Power and oscillator control" group.long 0x00++0x3 line.long 0x0 "POWERMODE,Power mode register" bitfld.long 0x00 0.--1. " Powermode ,Powermode" "Reserved,Normal,Reserved,Wakeup enabled clocks disabled" rgroup.long 0x04++0x3 line.long 0x0 "WD_BARK,Watch dog bark register" bitfld.long 0x00 0. " WD_BARK ,Watchdog reset occurred" "No reset,Reset" group.long 0x08++0x7 line.long 0x00 "FFAST_ON,Activate fast oscillator register" bitfld.long 0x00 0. " FFAST_ON ,Activate fast oscillator" "Disabled,Enabled" line.long 0x04 "FFAST_BYPASS,Bypass comparator register fast oscillator" bitfld.long 0x04 0. " FFAST_BYPASS ,Oscillator test mode" "Low,High" tree.end width 27. tree "Reset control" group.long 0x18++0x23 line.long 0x00 "APB1_RESETN_SOFT,Reset register for AHB part of AHB_TO_APB1 bridge" bitfld.long 0x00 0. " APB1_RESETN_SOFT ,Reset for APB part of AHB_TO_APB1 bridge" "Reset,No reset" line.long 0x04 "AHB_TO_APB1_PNRES_SOFT,Reset register for APB part of AHB_TO_APB1 bridge" bitfld.long 0x04 0. " AHB_TO_APB1_PNRES_SOFT ,Reset for APB part of AHB_TO_APB1 bridge" "Reset,No reset" line.long 0x08 "APB2_RESETN_SOFT,Reset register for AHB part of AHB_TO_APB2 bridge" bitfld.long 0x8 0. " APB2_RESETN_SOFT ,Reset for AHB part of AHB_TO_APB1 bridge" "Reset,No reset" line.long 0x0c "AHB_TO_APB2_PNRES_SOFT,Reset register for APB part of AHB_TO_APB2 bridge" bitfld.long 0xc 0. " AHB_TO_APB2_PNRES_SOFT ,Reset for APB part of AHB_TO_APB2 bridge" "Reset,No reset" line.long 0x10 "APB3_RESETN_SOFT,Reset register for AHB part of AHB_TO_APB3 bridge" bitfld.long 0x10 0. " APB3_RESETN_SOFT ,Reset for AHB part of AHB_TO_APB3 bridge" "Reset,No reset" line.long 0x14 "AHB_TO_APB3_PNRES_SOFT,Reset register for APB part of AHB_TO_APB3 bridge" bitfld.long 0x14 0. " AHB_TO_APB3_PNRES_SOFT ,Reset for APB part of AHB_TO_APB3 bridge" "Reset,No reset" line.long 0x18 "APB4_RESETN_SOFT,Reset register for AHB_TO_APB4 bridge" bitfld.long 0x18 0. " APB4_RESETN_SOFT ,Reset for AHB part of AHB_TO_APB4 bridge" "Reset,No reset" line.long 0x1c "AHB_TO_INTC_RESETN_SOFT,Reset register for AHB_TO_INTC" bitfld.long 0x1c 0. " AHB_TO_INTC_RESETN_SOFT ,Reset for AHB_TO_INTC" "Reset,No reset" line.long 0x20 "AHB_TO_INTC_RESETN_SOFT,Reset register for AHB_TO_INTC" bitfld.long 0x20 0. " AHB_TO_INTC_RESETN_SOFT ,Reset for AHB_TO_INTC" "Reset,No reset" group.long 0x3c++0x63 line.long 0x00 "EBI_RESET_N_SOFT,Reset register for EBI" bitfld.long 0x00 0. " EBI_RESET_N_SOFT ,Reset register for EBI" "Reset,No reset" line.long 0x04 "PCM_PNRES_SOFT,Reset register for APB domain of PCM" bitfld.long 0x04 0. " PCM_PNRES_SOFT ,Reset for APB domain of PCM" "Reset,No reset" line.long 0x08 "PCM_RESET_N_SOFT,Reset register for synchronous clk_ip domain of PCM" bitfld.long 0x08 0. " PCM_RESET_N_SOFT ,Reset for synchronous clk_ip domain of PCM" "Reset,No reset" line.long 0x0c "PCM_RESET_ASYNC_N_SOFT,Reset register for asynchronous clk_ip domain of PCM" bitfld.long 0x0c 0. " PCM_RESET_ASYNC_N_SOFT ,Reset for asynchronous clk_ip domain of PCM" "Reset,No reset" line.long 0x10 "TIMER0_PNRES_SOFT,Reset register for Timer0" bitfld.long 0x10 0. " TIMER0_PNRES_SOFT ,Reset for Timer0" "Reset,No reset" line.long 0x14 "TIMER1_PNRES_SOFT,Reset register for Timer1" bitfld.long 0x14 0. " TIMER1_PNRES_SOFT ,Reset for Timer1" "Reset,No reset" line.long 0x18 "TIMER2_PNRES_SOFT,Reset register for Timer2" bitfld.long 0x18 0. " TIMER2_PNRES_SOFT ,Reset for Timer2" "Reset,No reset" line.long 0x1c "TIMER3_PNRES_SOFT,Reset register for Timer3" bitfld.long 0x1c 0. " TIMER3_PNRES_SOFT ,Reset for Timer3" "Reset,No reset" line.long 0x20 "ADC_PRESETN_SOFT,Reset register for controller of 10 bit ADC Interface" bitfld.long 0x20 0. " ADC_PRESETN_SOFT ,Reset for controller of 10 bit ADC Interface" "Reset,No reset" line.long 0x24 "ADC_RESETN_ADC10BITS_SOFT,Reset register for A/D converter of ADC Interface" bitfld.long 0x24 0. " ADC_RESETN_ADC10BITS_SOFT ,Reset for A/D converter of ADC Interface" "Reset,No reset" line.long 0x28 "PWM_RESET_AN_SOFT,Reset register for PWM" bitfld.long 0x28 0. " PWM_RESET_AN_SOFT ,Reset for PWM" "Reset,No reset" line.long 0x2c "UART_SYS_RST_AN_SOFT,Reset register UART/IrDA" bitfld.long 0x2c 0. " UART_SYS_RST_AN_SOFT ,Reset for UART/IrDA" "Reset,No reset" line.long 0x30 "I2C0_PNRES_SOFT,Reset register for I2C0" bitfld.long 0x30 0. " I2C0_PNRES_SOFT ,Reset for I2C0" "Reset,No reset" line.long 0x34 "I2C1_PNRES_SOFT,Reset register for I2C1" bitfld.long 0x34 0. " I2C1_PNRES_SOFT ,Reset for I2C1" "Reset,No reset" line.long 0x38 "I2S_CFG_RST_N_SOFT,Reset register for I2S_Config" bitfld.long 0x38 0. " I2S_CFG_RST_N_SOFT ,Reset for I2S_Config" "Reset,No reset" line.long 0x3c "I2S_NSOF_RST_N_SOFT,Reset register for NSOF counter of I2S_CONFIG" bitfld.long 0x3c 0. " I2S_NSOF_RST_N_SOFT ,Reset for NSOF counter of I2S_CONFIG" "Reset,No reset" line.long 0x40 "EDGE_DET_RST_N_SOFT,Reset register for Edge_det" bitfld.long 0x40 0. " EDGE_DET_RST_N_SOFT ,Reset for Edge_det" "Reset,No reset" line.long 0x44 "I2STX_FIFO_0_RST_N_SOFT,Reset register for I2STX_FIFO_0" bitfld.long 0x44 0. " I2STX_FIFO_0_RST_N_SOFT ,Reset for I2STX_FIFO_0" "Reset,No reset" line.long 0x48 "I2STX_IF_0_RST_N_SOFT,Reset register for I2STX_IF_0" bitfld.long 0x48 0. " I2STX_IF_0_RST_N_SOFT ,Reset for I2STX_IF_0" "Reset,No reset" line.long 0x4c "I2STX_FIFO_1_RST_N_SOFT,Reset register for I2STX_FIFO_1" bitfld.long 0x4c 0. " I2STX_FIFO_1_RST_N_SOFT ,Reset for I2STX_FIFO_1" "Reset,No reset" line.long 0x50 "I2STX_IF_1_RST_N_SOFT,Reset register for I2STX_IF_1" bitfld.long 0x50 0. " I2STX_IF_1_RST_N_SOFT ,Reset for I2STX_IF_1" "Reset,No reset" line.long 0x54 "I2SRX_FIFO_0_RST_N_SOFT,Reset register for I2SRX_FIFO_0" bitfld.long 0x54 0. " I2SRX_FIFO_0_RST_N_SOFT ,Reset for I2SRX_FIFO_0" "Reset,No reset" line.long 0x58 "I2SRX_IF_0_RST_N_SOFT,Reset register for I2SRX_IF_0" bitfld.long 0x58 0. " I2SRX_IF_0_RST_N_SOFT ,Reset for I2SRX_IF_0" "Reset,No reset" line.long 0x5c "I2SRX_FIFO_1_RST_N_SOFT,Reset register for I2SRX_FIFO_1" bitfld.long 0x5c 0. " I2SRX_FIFO_1_RST_N_SOFT ,Reset for I2SRX_FIFO_1" "Reset,No reset" line.long 0x60 "I2SRX_IF_1_RST_N_SOFT,Reset register for I2SRX_IF_1" bitfld.long 0x60 0. " I2SRX_IF_1_RST_N_SOFT ,Reset for I2SRX_IF_1" "Reset,No reset" group.long 0xb4++0x13 line.long 0x00 "LCD_PNRES_SOFT,Reset register for LCD Interface" bitfld.long 0x00 0. " LCD_PNRES_SOFT ,Reset for LCD Interface" "Reset,No reset" line.long 0x04 "SPI_PNRES_APB_SOFT,Reset register for apb_clk domain of SPI" bitfld.long 0x04 0. " SPI_PNRES_APB_SOFT ,Reset register for apb_clk domain of SPI" "Reset,No reset" line.long 0x08 "SPI_PNRES_IP_SOFT,Reset register for ip_clk domain of SPI" bitfld.long 0x08 0. " SPI_PNRES_IP_SOFT ,Reset for ip_clk domain of SPI" "Reset,No reset" line.long 0x0c "DMA_PNRES_SOFT,Reset register for DMA" bitfld.long 0x0c 0. " DMA_PNRES_SOFT ,Reset for DMA" "Reset,No reset" width 34. line.long 0x10 "NANDFLASH_CTRL_ECC_RESET_N_SOFT,Reset register for ECC clock domain of Nandflash Controller" bitfld.long 0x10 0. " NANDFLASH_CTRL_ECC_RESET_N_SOFT ,Reset for ECC clock domain of Nandflash Controller" "Reset,No reset" group.long 0xcc++0x27 line.long 0x00 "NANDFLASH_CTRL_NAND_RESET_N_SOFT,Reset register for of Nandflash Controller" bitfld.long 0x00 0. " NANDFLASH_CTRL_NAND_RESET_N_SOFT ,Reset for Nandflash Controller" "Reset,No reset" line.long 0x04 "SD_MMC_PNRES_SOFT,Reset register for MCI synchronous with AHB clock" bitfld.long 0x04 0. " SD_MMC_PNRES_SOFT ,Reset for MCI synchronous with AHB clock" "Reset,No reset" line.long 0x08 "SD_MMC_NRES_CCLK_IN_SOFT,Reset register for MCI synchronous with IP clock" bitfld.long 0x08 0. " SD_MMC_NRES_CCLK_IN_SOFT ,Reset register for MCI synchronous with IP clock" "Reset,No reset" line.long 0x0c "USB_OTG_AHB_RST_N_SOFT,Reset register for USB_OTG" bitfld.long 0x0c 0. " USB_OTG_AHB_RST_N_SOFT ,Reset for USB_OTG" "Reset,No reset" line.long 0x10 "RED_CTL_RESET_N_SOFT,Reset register for Redundancy Controller" bitfld.long 0x10 0. " RED_CTL_RESET_N_SOFT ,Reset for Redundancy Controller" "Reset,No reset" line.long 0x14 "AHB_MPMC_HRESTN_SOFT,Reset register for MPMC" bitfld.long 0x14 0. " AHB_MPMC_HRESTN_SOFT ,Reset for MPMC" "Reset,No reset" line.long 0x20 "AHB_MPMC_REFRESH_RESETN_SOFT,Reset register for refresh generator used for MPMC" bitfld.long 0x20 0. " AHB_MPMC_REFRESH_RESETN_SOFT ,Reset for refresh generator used for MPMC" "Reset,No reset" line.long 0x24 "INTC_RESERTN_SOFT,Reset register for Interrupt Controller" bitfld.long 0x24 0. " INTC_RESERTN_SOFT ,Reset for Interrupt Controller" "Reset,No reset" tree.end width 16. tree "PLL control 0 (audio PLL)" group.long 0xf0++0xf line.long 0x00 "HP1_FIN_SELECT,Register for selecting input to high HPPLL0" bitfld.long 0x00 0.--3. " HP1_FIN_SELECT ,Select input to high HPPLL0" "ffast (12 Mhz),I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,Reserved,HP1_FOUT,?..." line.long 0x04 "HP0_MDEC,M-divider register of HP0 PLL" hexmask.long.tbyte 0x04 0.--16. 1. " HP0_MDEC ,Decoded divider ratio code for feedback divider (M-divider)" line.long 0x08 "HP0_NDEC,N-divider register of HP0 PLL" hexmask.long.word 0x08 0.--9. 1. " HP0_NDEC ,Decoded divider ratio code for pre-divider (N-divider)" line.long 0x0c "HP0_PDEC,P-divider register of HP0 PLL" hexmask.long.byte 0x0C 0.--6. 1. " HP0_PDEC ,Decoded divider ratio code for post-divider (P-divider)" group.long 0x100++0x3 line.long 0x00 "HP0_MODE,Mode register of HP0 PLL" bitfld.long 0x00 8. " HP0_MODE_BYPASS ,Bypass mode" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HP0_MODE_LIMUP_OFF ,Up limiter" "Spread spectrum/Fractional,Others" textline " " bitfld.long 0x00 6. " HP0_MODE_BANDSEL ,Bandwidth adjustment pin" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " HP0_MODE_FRM ,Free Running Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " HP0_MODE_DIRECTI ,Normal operation with DIRECTO" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HP0_MODE_DIRECTO ,Normal operation with DIRECTI" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HP0_MODE_PD ,Power down mode" "No power down,Power Down" textline " " bitfld.long 0x00 1. " HP0_MODE_SKEW_EN ,Skew mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " HP0_MODE_CLKEN ,Enable mode" "Disabled,Enabled" rgroup.long 0x104++0x7 line.long 0x00 "HP0_STATUS,Status register of HP0 PLL" bitfld.long 0x00 1. " HP0_STATUS_FR ,Free running detector" "Not detected,Detected" textline " " bitfld.long 0x00 0. " HP0_STATUS_LOCK ,Lock detector" "Not detected,Detected" line.long 0x04 "HP0_ACK,Ratio change acknowledge register of HP0 PLL" bitfld.long 0x04 2. " HP0_ACK_P ,Post-divider ratio change acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x04 1. " HP0_ACK_N ,Pre-divider ratio change acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x04 0. " HP0_ACK_M ,Feedback divider ratio change acknowledge" "Not acknowledged,Acknowledged" group.long 0x10c++0x1b line.long 0x00 "HP0_REQ,Ratio change request register of HP0 PLL" bitfld.long 0x00 2. " HP0_REQ_P ,Post-divider ratio change request" "Not requested,Requested" textline " " bitfld.long 0x00 1. " HP0_REQ_N ,Pre-divider ratio change request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " HP0_REQ_M ,Feedback divider ratio change request" "Not requested,Requested" line.long 0x04 "HP0_INSELR,Bandwidth selection register of HP0 PLL" bitfld.long 0x04 0.--3. " HP0_INSELR ,Pins to select the bandwidth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HP0_INSELI,Bandwidth selection register of HP0 PLL" bitfld.long 0x08 0.--5. " HP0_INSELI ,Bandwidth selection register of HP0 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0c "HP0_INSELP,Bandwidth selection register of HP0 PLL" bitfld.long 0x0C 0.--4. " HP0_INSELP ,Bandwidth selection register of HP0 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "HP0_SELR,Bandwidth selection register of HP0 PLL" bitfld.long 0x10 0.--3. " HP0_SELR ,Bandwidth selection register of HP0 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "HP0_SELI,Bandwidth selection register of HP0 PLL" bitfld.long 0x14 0.--5. " HP0_SELI ,Bandwidth selection register of HP0 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "HP0_SELP,Bandwidth selection register of HP0 PLL" bitfld.long 0x18 0.--4. " HP0_SELP ,Bandwidth selection register of HP0 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "PLL control 1 (system PLL)" group.long 0x128++0xf line.long 0x00 "HP1_FIN_SELECT,Register for selecting input to high HPPLL0" bitfld.long 0x00 0.--3. " HP1_FIN_SELECT ,Select input to high HPPLL0" "ffast (12 Mhz),I2SRX_BCK0,I2SRX_WS0,I2SRX_BCK1,I2SRX_WS1,HP1_FOUT,?..." line.long 0x04 "HP1_MDEC,M-divider register of HP1 PLL" hexmask.long.tbyte 0x04 0.--16. 1. " HP1_MDEC ,Decoded divider ratio code for feedback divider (M-divider)" line.long 0x08 "HP1_NDEC,N-divider register of HP1 PLL" hexmask.long.word 0x08 0.--9. 1. " HP1_NDEC ,Decoded divider ratio code for pre-divider (N-divider)" line.long 0x0c "HP1_PDEC,P-divider register of HP1 PLL" hexmask.long.byte 0x0C 0.--6. 1. " HP1_PDEC ,Decoded divider ratio code for post-divider (P-divider)" group.long 0x138++0x3 line.long 0x00 "HP1_MODE,Mode register of HP1 PLL" bitfld.long 0x00 8. " HP1_MODE_BYPASS ,Bypass mode" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HP1_MODE_LIMUP_OFF ,Up limiter" "Spread spectrum/Fractional,Others" textline " " bitfld.long 0x00 6. " HP1_MODE_BANDSEL ,Bandwidth adjustment pin" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " HP1_MODE_FRM ,Free Running Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " HP1_MODE_DIRECTI ,Normal operation with DIRECTO" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HP1_MODE_DIRECTO ,Normal operation with DIRECTI" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HP1_MODE_PD ,Power down mode" "Not powered down,Powered Down" textline " " bitfld.long 0x00 1. " HP1_MODE_SKEW_EN ,Skew mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " HP1_MODE_CLKEN ,Enable mode" "Disabled,Enabled" rgroup.long 0x13C++0x7 line.long 0x00 "HP1_STATUS,Status register of HP1 PLL" bitfld.long 0x00 1. " HP1_STATUS_FR ,Free running detector" "Not detected,Detected" textline " " bitfld.long 0x00 0. " HP1_STATUS_LOCK ,Lock detector" "Not detected,Detected" line.long 0x04 "HP1_ACK,Ratio change acknowledge register of HP1 PLL" bitfld.long 0x04 2. " HP1_ACK_P ,Post-divider ratio change acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x04 1. " HP1_ACK_N ,Pre-divider ratio change acknowledge" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x04 0. " HP1_ACK_M ,Feedback divider ratio change acknowledge" "Not acknowledged,Acknowledged" group.long 0x144++0x1b line.long 0x00 "HP1_REQ,Ratio change request register of HP1 PLL" bitfld.long 0x00 2. " HP1_REQ_P ,Post-divider ratio change request" "Not requested,Requested" textline " " bitfld.long 0x00 1. " HP1_REQ_N ,Pre-divider ratio change request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " HP1_REQ_M ,Feedback divider ratio change request" "Not requested,Requested" line.long 0x04 "HP1_INSELR,Bandwidth selection register of HP1 PLL" bitfld.long 0x04 0.--3. " HP1_INSELR ,Pins to select the bandwidth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HP1_INSELI,Bandwidth selection register of HP1 PLL" bitfld.long 0x08 0.--5. " HP1_INSELI ,Bandwidth selection register of HP1 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0c "HP1_INSELP,Bandwidth selection register of HP1 PLL" bitfld.long 0x0C 0.--4. " HP1_INSELP ,Bandwidth selection register of HP1 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "HP1_SELR,Bandwidth selection register of HP1 PLL" bitfld.long 0x10 0.--3. " HP1_SELR ,Bandwidth selection register of HP1 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "HP1_SELI,Bandwidth selection register of HP1 PLL" bitfld.long 0x14 0.--5. " HP1_SELI ,Bandwidth selection register of HP1 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "HP1_SELP,Bandwidth selection register of HP1 PLL" bitfld.long 0x18 0.--4. " HP1_SELP ,Bandwidth selection register of HP1 PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 0x0B tree.end tree "WDT (Watchdog Timer)" base ad:0x13002400 width 5. group.long 0x00++0x0F line.long 0x00 "IR,Watchdog Status Register" eventfld.long 0x00 1. " INTR_M1 ,MR1 and TC match interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTR_M0 ,MR0 and TC match interrupt" "No interrupt,Interrupt" line.long 0x04 "TCR,Watchdog Timer Control Register" bitfld.long 0x04 0. " COUNTER_EN ,Timer Counter Enable" "Disabled,Enabled" bitfld.long 0x04 1. " COUNTER_RST ,Timer Counter Reset" "No reset,Reset" line.long 0x08 "TC,TimerCounter Register" line.long 0x0C "PR,Prescale Register" rgroup.long 0x10++0x3 line.long 0x00 "PC,Prescale Counter Register" group.long 0x14++0x0B line.long 0x00 "MCR,Watchdog Match Control Register" bitfld.long 0x00 5. " STOP_ON_MR1 ,Stop on MR1 and TC Match Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RESET_ON_MR1 ,MR1 and TC Match Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTERRUPT_ON_MR1 ,MR1 and TC Match Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " STOP_ON_MR0 ,Stop on MR0 and TC Match Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RESET_ON_MR0 ,MR0 and TC Match Reset Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INTERRUPT_ON_MR0 ,MR0 and TC Match Interrupt Enable" "Disabled,Enabled" line.long 0x04 "MR0,Watchdog Match Register 0" line.long 0x08 "MR1,Watchdog Match Register 1" group.long 0x3C++0x03 line.long 0x00 "EMR,Watchdog External Match Register" bitfld.long 0x00 6.--7. " EXT_MATCH_CTRL_1 ,External Match 1" "Do Nothing,Low,High,Toggle" bitfld.long 0x00 4.--5. " EXT_MATCH_CTRL_0 ,External Match 0" "Do Nothing,Low,High,Toggle" textline " " bitfld.long 0x00 1. " EXT_MATCH_1 ,External match pin 1" "Low,High" bitfld.long 0x00 0. " EXT_MATCH_0 ,External match pin 0" "Low,High" width 0x0B tree.end tree.open "GPIO (General Purpose Input/Output)" base ad:0x13003000 width 15. tree "EBI_MCI" rgroup.long 0x000++0x03 line.long 0x00 "EBI_MCI_PINS,Input Pin State Register" bitfld.long 0x00 31. " mGPIO10 ,Pin state" "Low,High" bitfld.long 0x00 30. " mGPIO8 ,Pin state" "Low,High" textline " " bitfld.long 0x00 29. " mGPIO7 ,Pin state" "Low,High" bitfld.long 0x00 28. " mGPIO5 ,Pin state" "Low,High" textline " " bitfld.long 0x00 27. " mLCD_DB_15 ,Pin state" "Low,High" bitfld.long 0x00 26. " mLCD_DB_14 ,Pin state" "Low,High" textline " " bitfld.long 0x00 25. " mLCD_DB_13 ,Pin state" "Low,High" bitfld.long 0x00 24. " mLCD_DB_12 ,Pin state" "Low,High" textline " " bitfld.long 0x00 23. " mLCD_DB_11 ,Pin state" "Low,High" bitfld.long 0x00 22. " mLCD_DB_10 ,Pin state" "Low,High" textline " " bitfld.long 0x00 21. " mLCD_DB_9 ,Pin state" "Low,High" bitfld.long 0x00 20. " mLCD_DB_8 ,Pin state" "Low,High" textline " " bitfld.long 0x00 19. " mLCD_DB_6 ,Pin state" "Low,High" bitfld.long 0x00 18. " mLCD_DB_5 ,Pin state" "Low,High" textline " " bitfld.long 0x00 17. " mLCD_DB_3 ,Pin state" "Low,High" bitfld.long 0x00 16. " mLCD_RW_WR ,Pin state" "Low,High" textline " " bitfld.long 0x00 15. " mLCD_RS ,Pin state" "Low,High" bitfld.long 0x00 14. " mLCD_E_RD ,Pin state" "Low,High" textline " " bitfld.long 0x00 13. " mLCD_DB_1 ,Pin state" "Low,High" bitfld.long 0x00 12. " mLCD_CSB ,Pin state" "Low,High" textline " " bitfld.long 0x00 11. " EBI_DQM_0_NOE ,Pin state" "Low,High" bitfld.long 0x00 10. " mLCD_DB_0 ,Pin state" "Low,High" textline " " bitfld.long 0x00 9. " EBI_NCAS_BLOUT_0 ,Pin state" "Low,High" bitfld.long 0x00 8. " EBI_A_1_CLE ,Pin state" "Low,High" textline " " bitfld.long 0x00 7. " mI2STX_BCK0 ,Pin state" "Low,High" bitfld.long 0x00 6. " mI2STX_CLK0 ,Pin state" "Low,High" textline " " bitfld.long 0x00 5. " mNAND_RYBN0 ,Pin state" "Low,High" bitfld.long 0x00 4. " mLCD_DB_2 ,Pin state" "Low,High" textline " " bitfld.long 0x00 3. " mLCD_DB_4 ,Pin state" "Low,High" bitfld.long 0x00 2. " mLCD_DB_7 ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " mGPIO6 ,Pin state" "Low,High" bitfld.long 0x00 0. " mGPIO9 ,Pin state" "Low,High" group.long 0x010++0x03 line.long 0x00 "EBI_MCI_MODE0,Mode 0 Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " mGPIO10_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " mGPIO8_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " mGPIO7_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " mGPIO5_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " mLCD_DB_15_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " mLCD_DB_14_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " mLCD_DB_13_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " mLCD_DB_12_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 23. 0x04 23. 0x08 23. " mLCD_DB_11_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " mLCD_DB_10_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " mLCD_DB_9_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " mLCD_DB_8_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " mLCD_DB_6_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " mLCD_DB_5_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " mLCD_DB_3_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " mLCD_RW_WR_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 15. 0x04 15. 0x08 15. " mLCD_RS_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " mLCD_E_RD_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " mLCD_DB_1_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " mLCD_CSB_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " EBI_DQM_0_NOE_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " mLCD_DB_0_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " EBI_NCAS_BLOUT_0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EBI_A_1_CLE_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " mI2STX_BCK0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " mI2STX_CLK0_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " mNAND_RYBN0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " mLCD_DB_2_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " mLCD_DB_4_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " mLCD_DB_7_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " mGPIO6_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " mGPIO9_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x020++0x03 line.long 0x00 "EBI_MCI_MODE1,Mode 1 Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " mGPIO10_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " mGPIO6_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " mGPIO7_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " mGPIO5_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " mLCD_DB_15_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " mLCD_DB_14_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " mLCD_DB_13_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " mLCD_DB_12_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 23. 0x04 23. 0x08 23. " mLCD_DB_11_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " mLCD_DB_10_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " mLCD_DB_9_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " mLCD_DB_8_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " mLCD_DB_6_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " mLCD_DB_5_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " mLCD_DB_3_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " mLCD_RW_WR_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 15. 0x04 15. 0x08 15. " mLCD_RS_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " mLCD_E_RD_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " mLCD_DB_1_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " mLCD_CSB_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " EBI_DQM_0_NOE_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " mLCD_DB_0_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " EBI_NCAS_BLOUT_0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EBI_A_1_CLE_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " mI2STX_BCK0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " mI2STX_CLK0_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " mNAND_RYBN0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " mLCD_DB_2_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " mLCD_DB_4_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " mLCD_DB_7_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " mGPIO6_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " mGPIO9_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 19. tree "EBI_I2STX_0" rgroup.long 0x040++0x03 line.long 0x00 "EBI_I2STX_0_PINS,Input Pin State Register" bitfld.long 0x00 9. " EBI_NWE ,Pin state" "Low,High" bitfld.long 0x00 8. " EBI_A_0_ALE ,Pin state" "Low,High" textline " " bitfld.long 0x00 7. " EBI_NRAS_BLOUT_1 ,Pin state" "Low,High" bitfld.long 0x00 6. " mI2STX_WS0 ,Pin state" "Low,High" textline " " bitfld.long 0x00 5. " mI2STX_DATA0 ,Pin state" "Low,High" bitfld.long 0x00 4. " mUART_RTS_N ,Pin state" "Low,High" textline " " bitfld.long 0x00 3. " mUART_CTS_N ,Pin state" "Low,High" bitfld.long 0x00 2. " mNAND_RYBN3 ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " mNAND_RYBN2 ,Pin state" "Low,High" bitfld.long 0x00 0. " mNAND_RYBN1 ,Pin state" "Low,High" group.long 0x050++0x03 line.long 0x00 "EBI_I2STX_0_MODE0,Mode 0 Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " EBI_NWE_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EBI_A_0_ALE_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EBI_NRAS_BLOUT_1_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " mI2STX_WS0_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " mI2STX_DATA0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " mUART_RTS_N_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " mUART_CTS_N_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " mNAND_RYBN3_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " mNAND_RYBN2_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " mNAND_RYBN1_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x060++0x03 line.long 0x00 "EBI_I2STX_0_MODE1,Mode 1 Register" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " EBI_NWE_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EBI_A_0_ALE_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EBI_NRAS_BLOUT_1_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " mI2STX_WS0_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " mI2STX_DATA0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " mUART_RTS_N_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " mUART_CTS_N_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " mNAND_RYBN3_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " mNAND_RYBN2_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " mNAND_RYBN1_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 11. tree "CGU" rgroup.long 0x080++0x03 line.long 0x00 "CGU_PINS,Input Pin State Register" bitfld.long 0x00 0. " CGU_SYSCLK_O ,Pin state" "Low,High" group.long 0x090++0x03 line.long 0x00 "CGU_MODE0,Mode 0 Register" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CGU_SYSCLK_O_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x0a0++0x03 line.long 0x00 "CGU_MODE1,Mode 1 Register" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CGU_SYSCLK_O_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 15. tree "I2SRX_0" rgroup.long 0x0c0++0x03 line.long 0x00 "I2SRX_0_PINS,Input Pin State Register" bitfld.long 0x00 2. " I2SRX_WS0 ,Pin state" "Low,High" bitfld.long 0x00 1. " I2SRX_DATA0 ,Pin state" "Low,High" textline " " bitfld.long 0x00 0. " I2SRX_BCK0 ,Pin state" "Low,High" group.long 0x0d0++0x03 line.long 0x00 "I2SRX_0_MODE0,Mode 0 Register" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " I2SRX_WS0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2SRX_DATA0_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2SRX_BCK0_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x0e0++0x03 line.long 0x00 "I2SRX_0_MODE1,Mode 1 Register" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " I2SRX_WS0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2SRX_DATA0_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2SRX_BCK0_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 15. tree "I2SRX_1" rgroup.long 0x100++0x03 line.long 0x00 "I2SRX_1_PINS,Input Pin State Register" bitfld.long 0x00 2. " I2SRX_WS1 ,Pin state" "Low,High" bitfld.long 0x00 1. " I2SRX_BCK1 ,Pin state" "Low,High" textline " " bitfld.long 0x00 0. " I2SRX_DATA1 ,Pin state" "Low,High" group.long 0x110++0x03 line.long 0x00 "I2SRX_1_MODE0,Mode 0 Register" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " I2SRX_WS1_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2SRX_BCK1_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2SRX_DATA1_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x120++0x03 line.long 0x00 "I2SRX_1_MODE1,Mode 1 Register" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " I2SRX_WS1_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2SRX_BCK1_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2SRX_DATA1_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 15. tree "I2STX_1" rgroup.long 0x140++0x03 line.long 0x00 "I2STX_1_PINS,Input Pin State Register" bitfld.long 0x00 3. " I2STX_256FS_O ,Pin state" "Low,High" bitfld.long 0x00 2. " I2STX_WS1 ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " I2STX_BCK1 ,Pin state" "Low,High" bitfld.long 0x00 0. " I2STX_DATA1 ,Pin state" "Low,High" group.long 0x150++0x03 line.long 0x00 "I2STX_1_MODE0,Mode 0 Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " I2STX_256FS_O_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " I2STX_WS1_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2STX_BCK1_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2STX_DATA1_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x160++0x03 line.long 0x00 "I2STX_1_MODE1,Mode 1 Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " I2STX_256FS_O_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " I2STX_WS1_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2STX_BCK1_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2STX_DATA1_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 11. tree "EBI" rgroup.long 0x180++0x03 line.long 0x00 "EBI_PINS,Input Pin State Register" bitfld.long 0x00 15. " EBI_D_15 ,Pin state" "Low,High" bitfld.long 0x00 14. " EBI_D_8 ,Pin state" "Low,High" textline " " bitfld.long 0x00 13. " EBI_D_7 ,Pin state" "Low,High" bitfld.long 0x00 12. " EBI_D_6 ,Pin state" "Low,High" textline " " bitfld.long 0x00 11. " EBI_D_5 ,Pin state" "Low,High" bitfld.long 0x00 10. " EBI_D_3 ,Pin state" "Low,High" textline " " bitfld.long 0x00 9. " EBI_D_2 ,Pin state" "Low,High" bitfld.long 0x00 8. " EBI_D_1 ,Pin state" "Low,High" textline " " bitfld.long 0x00 7. " EBI_D_0 ,Pin state" "Low,High" bitfld.long 0x00 6. " EBI_D_4 ,Pin state" "Low,High" textline " " bitfld.long 0x00 5. " EBI_D_14 ,Pin state" "Low,High" bitfld.long 0x00 4. " EBI_D_13 ,Pin state" "Low,High" textline " " bitfld.long 0x00 3. " EBI_D_12 ,Pin state" "Low,High" bitfld.long 0x00 2. " EBI_D_11 ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " EBI_D_10 ,Pin state" "Low,High" bitfld.long 0x00 0. " EBI_D_9 ,Pin state" "Low,High" group.long 0x190++0x03 line.long 0x00 "EBI_MODE0,Mode 0 Register" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " EBI_D_15_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " EBI_D_8_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " EBI_D_7_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " EBI_D_6_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " EBI_D_5_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " EBI_D_3_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " EBI_D_2_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EBI_D_1_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EBI_D_0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " EBI_D_4_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " EBI_D_14_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EBI_D_13_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EBI_D_12_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " EBI_D_11_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " EBI_D_10_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EBI_D_9_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x1a0++0x03 line.long 0x00 "EBI_MODE1,Mode 1 Register" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " EBI_D_15_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " EBI_D_8_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " EBI_D_7_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " EBI_D_6_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " EBI_D_5_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " EBI_D_3_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " EBI_D_2_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EBI_D_1_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " EBI_D_0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " EBI_D_4_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " EBI_D_14_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " EBI_D_13_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " EBI_D_12_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " EBI_D_11_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " EBI_D_10_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " EBI_D_9_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 12. tree "GPIO" rgroup.long 0x1c0++0x03 line.long 0x00 "GPIO_PINS,Input Pin State Register" bitfld.long 0x00 14. " GPIO_GPIO20 ,Pin state" "Low,High" textline " " bitfld.long 0x00 13. " GPIO_GPIO19 ,Pin state" "Low,High" bitfld.long 0x00 12. " GPIO_GPIO18 ,Pin state" "Low,High" textline " " bitfld.long 0x00 11. " GPIO_GPIO17 ,Pin state" "Low,High" bitfld.long 0x00 10. " GPIO_GPIO16 ,Pin state" "Low,High" textline " " bitfld.long 0x00 9. " GPIO_GPIO15 ,Pin state" "Low,High" bitfld.long 0x00 8. " GPIO_GPIO14 ,Pin state" "Low,High" textline " " bitfld.long 0x00 7. " GPIO_GPIO13 ,Pin state" "Low,High" bitfld.long 0x00 6. " GPIO_GPIO12 ,Pin state" "Low,High" textline " " bitfld.long 0x00 5. " GPIO_GPIO11 ,Pin state" "Low,High" bitfld.long 0x00 4. " GPIO_GPIO4 ,Pin state" "Low,High" textline " " bitfld.long 0x00 3. " GPIO_GPIO3 ,Pin state" "Low,High" bitfld.long 0x00 2. " GPIO_GPIO2 ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " GPIO_GPIO0 ,Pin state" "Low,High" bitfld.long 0x00 0. " GPIO_GPIO1 ,Pin state" "Low,High" group.long 0x1d0++0x03 line.long 0x00 "GPIO_MODE0,Mode 0 Register" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " GPIO_GPIO20_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " GPIO_GPIO19_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " GPIO_GPIO18_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " GPIO_GPIO17_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " GPIO_GPIO16_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " GPIO_GPIO15_0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " GPIO_GPIO14_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GPIO_GPIO13_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GPIO_GPIO12_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GPIO_GPIO11_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GPIO_GPIO4_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GPIO_GPIO3_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GPIO_GPIO2_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GPIO_GPIO0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GPIO_GPIO1_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x1e0++0x03 line.long 0x00 "GPIO_MODE1,Mode 1 Register" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " GPIO_GPIO20_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " GPIO_GPIO19_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " GPIO_GPIO18_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " GPIO_GPIO17_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " GPIO_GPIO16_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " GPIO_GPIO15_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " GPIO_GPIO14_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GPIO_GPIO13_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GPIO_GPIO12_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GPIO_GPIO11_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GPIO_GPIO4_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GPIO_GPIO3_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GPIO_GPIO2_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GPIO_GPIO0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GPIO_GPIO1_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 12. tree "I2C1" rgroup.long 0x200++0x03 line.long 0x00 "I2C1_PINS,Input Pin State Register" bitfld.long 0x00 1. " I2C_SCL1 ,Pin state" "Low,High" bitfld.long 0x00 0. " I2C_SDA1 ,Pin state" "Low,High" group.long 0x210++0x03 line.long 0x00 "I2C1_MODE0,Mode 0 Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2C_SCL1_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2C_SDA1_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x220++0x03 line.long 0x00 "I2C1_MODE1,Mode 1 Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2C_SCL1_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " I2C_SDA1_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 11. tree "SPI" rgroup.long 0x240++0x03 line.long 0x00 "SPI_PINS,Input Pin State Register" bitfld.long 0x00 4. " SPI_CS_OUT0 ,Pin state" "Low,High" textline " " bitfld.long 0x00 3. " SPI_SCK ,Pin state" "Low,High" bitfld.long 0x00 2. " SPI_CS_IN ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " SPI_MOSI ,Pin state" "Low,High" bitfld.long 0x00 0. " SPI_MISO ,Pin state" "Low,High" group.long 0x250++0x03 line.long 0x00 "SPI_MODE0,Mode 0 Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SPI_CS_OUT0_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SPI_SCK_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SPI_CS_IN_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SPI_MOSI_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SPI_MISO_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x260++0x03 line.long 0x00 "SPI_MODE1,Mode 1 Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SPI_CS_OUT0_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SPI_SCK_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SPI_CS_IN_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SPI_MOSI_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SPI_MISO_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 18. tree "NAND_FLASH" rgroup.long 0x280++0x03 line.long 0x00 "NAND_FLASH_PINS,Input Pin State Register" bitfld.long 0x00 3. " NAND_NCS_2 ,Pin state" "Low,High" bitfld.long 0x00 2. " NAND_NCS_1 ,Pin state" "Low,High" textline " " bitfld.long 0x00 1. " NAND_NCS_0 ,Pin state" "Low,High" bitfld.long 0x00 0. " NAND_NCS_3 ,Pin state" "Low,High" group.long 0x290++0x03 line.long 0x00 "NAND_FLASH_MODE0,Mode 0 Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAND_NCS_2_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " NAND_NCS_1_set/clr ,Mode 1 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " NAND_NCS_0_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " NAND_NCS_3_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x2a0++0x03 line.long 0x00 "NAND_FLASH_MODE1,Mode 1 Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAND_NCS_2_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " NAND_NCS_1_set/clr ,Mode 0 Pin state" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " NAND_NCS_0_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " NAND_NCS_3_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 11. tree "PWM" rgroup.long 0x2c0++0x03 line.long 0x00 "PWM_PINS,Input Pin State Register" bitfld.long 0x00 0. " PWM_DATA ,Pin state" "Low,High" group.long 0x2d0++0x03 line.long 0x00 "PWM_MODE0,Mode 0 Register" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PWM_DATA_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x2e0++0x03 line.long 0x00 "PWM_MODE1,Mode 1 Register" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PWM_DATA_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 12. tree "UART" rgroup.long 0x300++0x03 line.long 0x00 "UART_PINS,Input Pin State Register" bitfld.long 0x00 1. " UART_TXD ,Pin state" "Low,High" bitfld.long 0x00 0. " UART_RXD ,Pin state" "Low,High" group.long 0x310++0x03 line.long 0x00 "UART_MODE0,Mode 0 Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UART_TXD_set/clr ,Mode 1 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " UART_RXD_set/clr ,Mode 1 Pin state" "Low,High" group.long 0x320++0x03 line.long 0x00 "UART_MODE1,Mode 1 Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " UART_TXD_set/clr ,Mode 0 Pin state" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " UART_RXD_set/clr ,Mode 0 Pin state" "Low,High" tree.end width 0x0B tree.end tree "ADC (Analog/Digital Converter)" base ad:0x13002000 width 20. group.long 0x00++0xf line.long 0x00 "ADC_R0_REG,ADC Data Register Channel 0" hexmask.long.word 0x00 0.--9. 1. " ADC_R0_DATA ,Conversion data" line.long 0x04 "ADC_R1_REG,ADC Data Register Channel 1" hexmask.long.word 0x04 0.--9. 1. " ADC_R1_DATA ,Conversion data" line.long 0x08 "ADC_R2_REG,ADC Data Register Channel 2" hexmask.long.word 0x08 0.--9. 1. " ADC_R2_DATA ,Conversion data" line.long 0x0c "ADC_R3_REG,ADC Data Register Channel 3" hexmask.long.word 0x0c 0.--9. 1. " ADC_R3_DATA ,Conversion data" group.long 0x20++0x7 line.long 0x00 "ADC_CON_REG,ADC Control Register" bitfld.long 0x00 4. " ADC_STATUS ,ADC Status" "Idle,In progress" bitfld.long 0x00 3. " ADC_START ,Start command" "No effect,Started" textline " " bitfld.long 0x00 2. " ADC_CSCAN ,Continuous Scan" "Single,Continuous" bitfld.long 0x00 1. " ADC_ENABLE ,ADC enable" "Disabled,Enabled" line.long 0x04 "ADC_CSEL_RES_REG,ADC Channel Selection Register" bitfld.long 0x04 12.--15. " CSEL3 , Channel 3 bit-resolution" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x04 8.--11. " CSEL2 , Channel 2 bit-resolution" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,?..." textline " " bitfld.long 0x04 4.--7. " CSEL1 , Channel 1 bit-resolution" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x04 0.--3. " CSEL0 , Channel 0 bit-resolution" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,?..." group.long 0x2c++0x3 line.long 0x00 "ADC_INT_STATUS_REG,ADC Interrupt Status Register" setclrfld.long 0x00 0. -0x04 0. 0x04 0. " ADC_INT_STATUS ,Interrupt status" "No interrupt,Interrupt" width 0xb tree.end tree.open "Event Router" base ad:0x13000000 width 8. tree "Input" group.long 0xc00++0xf line.long 0x00 "PEND_0,Input Event Pending Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " PEND_EBI_D_6_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " PEND_EBI_D_5_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " PEND_EBI_D_4_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " PEND_EBI_D_3_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " PEND_EBI_D_2_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " PEND_EBI_D_1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " PEND_EBI_D_0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " PEND_mNAND_RYBN3_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " PEND_mNAND_RYBN2_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " PEND_mNAND_RYBN1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " PEND_mNAND_RYBN0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " PEND_mLCD_RW_WR_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " PEND_mLCD_E_RD_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " PEND_mLCD_CSB_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " PEND_mLCD_RS_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " PEND_mLCD_DB_15_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " PEND_mLCD_DB_14_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " PEND_mLCD_DB_13_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " PEND_mLCD_DB_12_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " PEND_mLCD_DB_11_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " PEND_mLCD_DB_10_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " PEND_mLCD_DB_9_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " PEND_mLCD_DB_8_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " PEND_mLCD_DB_7_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " PEND_mLCD_DB_6_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " PEND_mLCD_DB_5_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " PEND_mLCD_DB_4_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " PEND_mLCD_DB_3_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " PEND_mLCD_DB_2_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " PEND_mLCD_DB_1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " PEND_mLCD_DB_0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " PEND_pcm_int_set/clr ,Input Event From PCM" "No interrupt,Interrupt" line.long 0x04 "PEND_1,Input Event Pending Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " PEND_GPIO16_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " PEND_GPIO15_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " PEND_GPIO14_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " PEND_GPIO13_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " PEND_GPIO12_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " PEND_GPIO11_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " PEND_mGPIO10_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " PEND_mGPIO9_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " PEND_mGPIO8_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " PEND_mGPIO7_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " PEND_mGPIO6_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " PEND_mGPIO5_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " PEND_GPIO4_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " PEND_GPIO3_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " PEND_GPIO2_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " PEND_GPIO1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " PEND_GPIO0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " PEND_EBI_NRAS_BLOUT_1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " PEND_EBI_NCAS_BLOUT_0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " PEND_EBI_DQM_0_NOE_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " PEND_EBI_A_1_CLE_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " PEND_EBI_A_0_ALE_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " PEND_EBI_NWE_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " PEND_EBI_D_15_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " PEND_EBI_D_14_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " PEND_EBI_D_13_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " PEND_EBI_D_12_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " PEND_EBI_D_11_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " PEND_EBI_D_10_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " PEND_EBI_D_9_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " PEND_EBI_D_8_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " PEND_EBI_D_7_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" line.long 0x08 "PEND_2,Input Event Pending Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " PEND_PWM_DATA_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " PEND_I2C_SCL1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " PEND_I2C_SDA1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " PEND_CLK_256FS_O_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " PEND_I2STX_WS1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " PEND_I2STX_BCK1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " PEND_I2STX_DATA1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " PEND_I2SRX_WS1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " PEND_I2SRX_BCK1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " PEND_I2SRX_DATA1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " PEND_I2SRX_WS0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " PEND_I2SRX_DATA0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " PEND_I2SRX_BCK0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " PEND_mI2STX_WS0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " PEND_mI2STX_DATA0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " PEND_mI2STX_BCK0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " PEND_mI2STX_CLK0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " PEND_mUART_RTS_N_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " PEND_mUART_CTS_N_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " PEND_UART_TXD_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " PEND_UART_RXD_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " PEND_SPI_CS_OUT0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " PEND_SPI_SCK_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " PEND_SPI_CS_IN_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " PEND_SPI_MOSI_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " PEND_SPI_MISO_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " PEND_NAND_NCS_3_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " PEND_NAND_NCS_2_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " PEND_NAND_NCS_1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " PEND_NAND_NCS_0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " PEND_GPIO18_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " PEND_GPIO17_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" line.long 0x0c "PEND_3,Input Event Pending Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " PEND_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " PEND_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " PEND_USB_ID_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " PEND_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " PEND_usb_atx_pll_lock_set/clr ,USB PLL lock event" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " PEND_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " PEND_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " PEND_MCI_CLK_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " PEND_MCI_CMD_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " PEND_MCI_DAT_7_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " PEND_MCI_DAT_6_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " PEND_MCI_DAT_5_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " PEND_MCI_DAT_4_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " PEND_MCI_DAT_3_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " PEND_MCI_DAT_2_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " PEND_MCI_DAT_1_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " PEND_MCI_DAT_0_set/clr ,Input Event From GPIO pin" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " PEND_arm926_lp_nirq_set/clr ,Reflects nIRQ signal going to ARM core" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " PEND_arm926_lp_nfiq_set/clr ,Reflects nFIQ signal going to ARM core" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " PEND_I2c1_scl_n_set/clr ,Input Event From I2C1" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " PEND_I2c0_scl_n_set/clr ,Input Event From I2C0" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " PEND_uart_rxd_set/clr ,Input Event From UART" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " PEND_wdog_m0_set/clr ,Input Event From Watch Dog" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " PEND_adc_int_set/clr ,Input Event From ADC" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " PEND_timer3_intct1_set/clr ,Input Event From Timer 3" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " PEND_timer2_intct1_set/clr ,Input Event From Timer 2" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " PEND_timer1_intct1_set/clr ,Input Event From Timer 1" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " PEND_timer0_intct1_set/clr ,Input Event From Timer 0" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " PEND_GPIO20_set/clr ,Input Event From GPIO20" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " PEND_GPIO19_set/clr ,Input Event From GPIO19" "No interrupt,Interrupt" group.long 0xc60++0xf line.long 0x00 "MASK_0,Input Event Mask Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " MASK_EBI_D_6_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " MASK_EBI_D_5_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " MASK_EBI_D_4_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " MASK_EBI_D_3_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " MASK_EBI_D_2_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " MASK_EBI_D_1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " MASK_EBI_D_0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " MASK_mNAND_RYBN3_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " MASK_mNAND_RYBN2_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " MASK_mNAND_RYBN1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " MASK_mNAND_RYBN0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " MASK_mLCD_RW_WR_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " MASK_mLCD_E_RD_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " MASK_mLCD_CSB_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " MASK_mLCD_RS_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " MASK_mLCD_DB_15_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " MASK_mLCD_DB_14_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " MASK_mLCD_DB_13_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " MASK_mLCD_DB_12_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " MASK_mLCD_DB_11_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " MASK_mLCD_DB_10_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " MASK_mLCD_DB_9_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " MASK_mLCD_DB_8_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " MASK_mLCD_DB_7_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " MASK_mLCD_DB_6_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " MASK_mLCD_DB_5_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " MASK_mLCD_DB_4_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " MASK_mLCD_DB_3_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " MASK_mLCD_DB_2_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " MASK_mLCD_DB_1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " MASK_mLCD_DB_0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " MASK_pcm_int_set/clr ,Input Event From PCM" "Masked,Not masked" line.long 0x04 "MASK_1,Input Event Mask Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " MASK_GPIO16_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " MASK_GPIO15_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " MASK_GPIO14_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " MASK_GPIO13_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " MASK_GPIO12_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " MASK_GPIO11_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " MASK_mGPIO10_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " MASK_mGPIO9_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " MASK_mGPIO8_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " MASK_mGPIO7_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " MASK_mGPIO6_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " MASK_mGPIO5_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " MASK_GPIO4_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " MASK_GPIO3_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " MASK_GPIO2_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " MASK_GPIO1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " MASK_GPIO0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " MASK_EBI_NRAS_BLOUT_1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " MASK_EBI_NCAS_BLOUT_0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " MASK_EBI_DQM_0_NOE_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " MASK_EBI_A_1_CLE_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " MASK_EBI_A_0_ALE_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " MASK_EBI_NWE_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " MASK_EBI_D_15_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " MASK_EBI_D_14_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " MASK_EBI_D_13_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " MASK_EBI_D_12_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " MASK_EBI_D_11_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " MASK_EBI_D_10_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " MASK_EBI_D_9_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " MASK_EBI_D_8_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " MASK_EBI_D_7_set/clr ,Input Event From GPIO pin" "Masked,Not masked" line.long 0x08 "MASK_2,Input Event Mask Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " MASK_PWM_DATA_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " MASK_I2C_SCL1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " MASK_I2C_SDA1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " MASK_CLK_256FS_O_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " MASK_I2STX_WS1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " MASK_I2STX_BCK1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " MASK_I2STX_DATA1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " MASK_I2SRX_WS1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " MASK_I2SRX_BCK1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " MASK_I2SRX_DATA1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " MASK_I2SRX_WS0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " MASK_I2SRX_DATA0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " MASK_I2SRX_BCK0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " MASK_mI2STX_WS0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " MASK_mI2STX_DATA0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " MASK_mI2STX_BCK0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " MASK_mI2STX_CLK0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " MASK_mUART_RTS_N_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " MASK_mUART_CTS_N_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " MASK_UART_TXD_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " MASK_UART_RXD_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " MASK_SPI_CS_OUT0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " MASK_SPI_SCK_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " MASK_SPI_CS_IN_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " MASK_SPI_MOSI_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " MASK_SPI_MISO_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " MASK_NAND_NCS_3_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " MASK_NAND_NCS_2_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " MASK_NAND_NCS_1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " MASK_NAND_NCS_0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " MASK_GPIO18_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " MASK_GPIO17_set/clr ,Input Event From GPIO pin" "Masked,Not masked" line.long 0x0c "MASK_3,Input Event Mask Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " MASK_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " MASK_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " MASK_USB_ID_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " MASK_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " MASK_usb_atx_pll_lock_set/clr ,USB PLL lock event" "Masked,Not masked" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " MASK_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " MASK_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " MASK_MCI_CLK_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " MASK_MCI_CMD_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " MASK_MCI_DAT_7_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " MASK_MCI_DAT_6_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " MASK_MCI_DAT_5_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " MASK_MCI_DAT_4_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " MASK_MCI_DAT_3_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " MASK_MCI_DAT_2_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " MASK_MCI_DAT_1_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " MASK_MCI_DAT_0_set/clr ,Input Event From GPIO pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " MASK_arm926_lp_nirq_set/clr ,Reflects nIRQ signal going to ARM core" "Masked,Not masked" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " MASK_arm926_lp_nfiq_set/clr ,Reflects nFIQ signal going to ARM core" "Masked,Not masked" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " MASK_I2c1_scl_n_set/clr ,Input Event From I2C1" "Masked,Not masked" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " MASK_I2c0_scl_n_set/clr ,Input Event From I2C0" "Masked,Not masked" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " MASK_uart_rxd_set/clr ,Input Event From UART" "Masked,Not masked" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " MASK_wdog_m0_set/clr ,Input Event From Watch Dog" "Masked,Not masked" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " MASK_adc_int_set/clr ,Input Event From ADC" "Masked,Not masked" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " MASK_timer3_intct1_set/clr ,Input Event From Timer 3" "Masked,Not masked" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " MASK_timer2_intct1_set/clr ,Input Event From Timer 2" "Masked,Not masked" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " MASK_timer1_intct1_set/clr ,Input Event From Timer 1" "Masked,Not masked" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " MASK_timer0_intct1_set/clr ,Input Event From Timer 0" "Masked,Not masked" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " MASK_GPIO20_set/clr ,Input Event From GPIO20" "Masked,Not masked" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " MASK_GPIO19_set/clr ,Input Event From GPIO19" "Masked,Not masked" group.long 0xcc0++0xf line.long 0x00 "APR_0,Input Event Activation Polarity Register - Bank 0" bitfld.long 0x00 31. " APR_EBI_D_6 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 30. " APR_EBI_D_5 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 29. " APR_EBI_D_4 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 28. " APR_EBI_D_3 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 27. " APR_EBI_D_2 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 26. " APR_EBI_D_1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 25. " APR_EBI_D_0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 24. " APR_mNAND_RYBN3 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 23. " APR_mNAND_RYBN2 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 22. " APR_mNAND_RYBN1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 21. " APR_mNAND_RYBN0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 20. " APR_mLCD_RW_WR ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 19. " APR_mLCD_E_RD ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 18. " APR_mLCD_CSB ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 17. " APR_mLCD_RS ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 16. " APR_mLCD_DB_15 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 15. " APR_mLCD_DB_14 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 14. " APR_mLCD_DB_13 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 13. " APR_mLCD_DB_12 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 12. " APR_mLCD_DB_11 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 11. " APR_mLCD_DB_10 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 10. " APR_mLCD_DB_9 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 9. " APR_mLCD_DB_8 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 8. " APR_mLCD_DB_7 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 7. " APR_mLCD_DB_6 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 6. " APR_mLCD_DB_5 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 5. " APR_mLCD_DB_4 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 4. " APR_mLCD_DB_3 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 3. " APR_mLCD_DB_2 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 2. " APR_mLCD_DB_1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 1. " APR_mLCD_DB_0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x00 0. " APR_pcm_int ,Activation polarity" "Low sensitive,High sensitive" line.long 0x04 "APR_1,Input Event Activation Polarity Register - Bank 1" bitfld.long 0x04 31. " APR_GPIO16 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 30. " APR_GPIO15 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 29. " APR_GPIO14 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 28. " APR_GPIO13 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 27. " APR_GPIO12 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 26. " APR_GPIO11 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 25. " APR_mGPIO10 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 24. " APR_mGPIO9 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 23. " APR_mGPIO8 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 22. " APR_mGPIO7 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 21. " APR_mGPIO6 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 20. " APR_mGPIO5 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 19. " APR_GPIO4 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 18. " APR_GPIO3 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 17. " APR_GPIO2 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 16. " APR_GPIO1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 15. " APR_GPIO0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 14. " APR_EBI_NRAS_BLOUT_1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 13. " APR_EBI_NCAS_BLOUT_0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 12. " APR_EBI_DQM_0_NOE ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 11. " APR_EBI_A_1_CLE ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 10. " APR_EBI_A_0_ALE ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 9. " APR_EBI_NWE ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 8. " APR_EBI_D_15 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 7. " APR_EBI_D_14 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 6. " APR_EBI_D_13 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 5. " APR_EBI_D_12 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 4. " APR_EBI_D_11 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 3. " APR_EBI_D_10 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 2. " APR_EBI_D_9 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 1. " APR_EBI_D_8 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x04 0. " APR_EBI_D_7 ,Activation polarity" "Low sensitive,High sensitive" line.long 0x08 "APR_2,Input Event Activation Polarity Register - Bank 2" bitfld.long 0x08 31. " APR_PWM_DATA ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 30. " APR_I2C_SCL1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 29. " APR_I2C_SDA1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 28. " APR_CLK_256FS_O ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 27. " APR_I2STX_WS1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 26. " APR_I2STX_BCK1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 25. " APR_I2STX_DATA1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 24. " APR_I2SRX_WS1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 23. " APR_I2SRX_BCK1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 22. " APR_I2SRX_DATA1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 21. " APR_I2SRX_WS0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 20. " APR_I2SRX_DATA0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 19. " APR_I2SRX_BCK0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 18. " APR_mI2STX_WS0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 17. " APR_mI2STX_DATA0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 16. " APR_mI2STX_BCK0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 15. " APR_mI2STX_CLK0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 14. " APR_mUART_RTS_N ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 13. " APR_mUART_CTS_N ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 12. " APR_UART_TXD ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 11. " APR_UART_RXD ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 10. " APR_SPI_CS_OUT0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 9. " APR_SPI_SCK ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 8. " APR_SPI_CS_IN ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 7. " APR_SPI_MOSI ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 6. " APR_SPI_MISO ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 5. " APR_NAND_NCS_3 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 4. " APR_NAND_NCS_2 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 3. " APR_NAND_NCS_1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 2. " APR_NAND_NCS_0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 1. " APR_GPIO18 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x08 0. " APR_GPIO17 ,Activation polarity" "Low sensitive,High sensitive" line.long 0x0c "APR_3,Input Event Activation Polarity Register - Bank 3" bitfld.long 0x0c 29. " APR_isram1_mrc_finished ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 28. " APR_isram0_mrc_finished ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 27. " APR_USB_ID ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 26. " APR_usb_otg_vbus_pwr_en ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 25. " APR_usb_atx_pll_lock ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 24. " APR_usb_otg_ahb_needclk ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 23. " APR_USB_VBUS ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 22. " APR_MCI_CLK ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 21. " APR_MCI_CMD ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 20. " APR_MCI_DAT_7 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 19. " APR_MCI_DAT_6 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 18. " APR_MCI_DAT_5 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 17. " APR_MCI_DAT_4 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 16. " APR_MCI_DAT_3 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 15. " APR_MCI_DAT_2 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 14. " APR_MCI_DAT_1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 13. " APR_MCI_DAT_0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 12. " APR_arm926_lp_nirq ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 11. " APR_arm926_lp_nfiq ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 10. " APR_I2c1_scl_n ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 9. " APR_I2c0_scl_n ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 8. " APR_uart_rxd ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 7. " APR_wdog_m0 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 6. " APR_adc_int ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 5. " APR_timer3_intct1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 4. " APR_timer2_intct1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 3. " APR_timer1_intct1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 2. " APR_timer0_intct1 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 1. " APR_GPIO20 ,Activation polarity" "Low sensitive,High sensitive" textline " " bitfld.long 0x0c 0. " APR_GPIO19 ,Activation polarity" "Low sensitive,High sensitive" group.long 0xce0++0xf line.long 0x00 "ATR_0,Input Event Activation Type Register - Bank 0" bitfld.long 0x00 31. " ATR_EBI_D_6 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 30. " ATR_EBI_D_5 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 29. " ATR_EBI_D_4 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 28. " ATR_EBI_D_3 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 27. " ATR_EBI_D_2 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 26. " ATR_EBI_D_1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 25. " ATR_EBI_D_0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 24. " ATR_mNAND_RYBN3 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 23. " ATR_mNAND_RYBN2 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 22. " ATR_mNAND_RYBN1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 21. " ATR_mNAND_RYBN0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 20. " ATR_mLCD_RW_WR ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 19. " ATR_mLCD_E_RD ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 18. " ATR_mLCD_CSB ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 17. " ATR_mLCD_RS ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 16. " ATR_mLCD_DB_15 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 15. " ATR_mLCD_DB_14 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 14. " ATR_mLCD_DB_13 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 13. " ATR_mLCD_DB_12 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 12. " ATR_mLCD_DB_11 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 11. " ATR_mLCD_DB_10 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 10. " ATR_mLCD_DB_9 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 9. " ATR_mLCD_DB_8 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 8. " ATR_mLCD_DB_7 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 7. " ATR_mLCD_DB_6 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 6. " ATR_mLCD_DB_5 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 5. " ATR_mLCD_DB_4 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 4. " ATR_mLCD_DB_3 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 3. " ATR_mLCD_DB_2 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 2. " ATR_mLCD_DB_1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 1. " ATR_mLCD_DB_0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x00 0. " ATR_pcm_int ,Activation type" "Direct,Latched(edge)" line.long 0x04 "ATR_1,Input Event Activation Type Register - Bank 1" bitfld.long 0x04 31. " ATR_GPIO16 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 30. " ATR_GPIO15 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 29. " ATR_GPIO14 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 28. " ATR_GPIO13 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 27. " ATR_GPIO12 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 26. " ATR_GPIO11 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 25. " ATR_mGPIO10 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 24. " ATR_mGPIO9 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 23. " ATR_mGPIO8 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 22. " ATR_mGPIO7 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 21. " ATR_mGPIO6 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 20. " ATR_mGPIO5 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 19. " ATR_GPIO4 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 18. " ATR_GPIO3 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 17. " ATR_GPIO2 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 16. " ATR_GPIO1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 15. " ATR_GPIO0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 14. " ATR_EBI_NRAS_BLOUT_1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 13. " ATR_EBI_NCAS_BLOUT_0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 12. " ATR_EBI_DQM_0_NOE ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 11. " ATR_EBI_A_1_CLE ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 10. " ATR_EBI_A_0_ALE ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 9. " ATR_EBI_NWE ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 8. " ATR_EBI_D_15 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 7. " ATR_EBI_D_14 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 6. " ATR_EBI_D_13 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 5. " ATR_EBI_D_12 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 4. " ATR_EBI_D_11 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 3. " ATR_EBI_D_10 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 2. " ATR_EBI_D_9 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 1. " ATR_EBI_D_8 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x04 0. " ATR_EBI_D_7 ,Activation type" "Direct,Latched(edge)" line.long 0x08 "ATR_2,Input Event Activation Type Register - Bank 2" bitfld.long 0x08 31. " ATR_PWM_DATA ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 30. " ATR_I2C_SCL1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 29. " ATR_I2C_SDA1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 28. " ATR_CLK_256FS_O ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 27. " ATR_I2STX_WS1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 26. " ATR_I2STX_BCK1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 25. " ATR_I2STX_DATA1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 24. " ATR_I2SRX_WS1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 23. " ATR_I2SRX_BCK1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 22. " ATR_I2SRX_DATA1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 21. " ATR_I2SRX_WS0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 20. " ATR_I2SRX_DATA0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 19. " ATR_I2SRX_BCK0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 18. " ATR_mI2STX_WS0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 17. " ATR_mI2STX_DATA0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 16. " ATR_mI2STX_BCK0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 15. " ATR_mI2STX_CLK0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 14. " ATR_mUART_RTS_N ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 13. " ATR_mUART_CTS_N ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 12. " ATR_UART_TXD ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 11. " ATR_UART_RXD ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 10. " ATR_SPI_CS_OUT0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 9. " ATR_SPI_SCK ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 8. " ATR_SPI_CS_IN ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 7. " ATR_SPI_MOSI ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 6. " ATR_SPI_MISO ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 5. " ATR_NAND_NCS_3 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 4. " ATR_NAND_NCS_2 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 3. " ATR_NAND_NCS_1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 2. " ATR_NAND_NCS_0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 1. " ATR_GPIO18 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x08 0. " ATR_GPIO17 ,Activation type" "Direct,Latched(edge)" line.long 0x0c "ATR_3,Input Event Activation Type Register - Bank 3" bitfld.long 0x0c 29. " ATR_isram1_mrc_finished ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 28. " ATR_isram0_mrc_finished ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 27. " ATR_USB_ID ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 26. " ATR_usb_otg_vbus_pwr_en ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 25. " ATR_usb_atx_pll_lock ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 24. " ATR_usb_otg_ahb_needclk ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 23. " ATR_USB_VBUS ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 22. " ATR_MCI_CLK ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 21. " ATR_MCI_CMD ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 20. " ATR_MCI_DAT_7 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 19. " ATR_MCI_DAT_6 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 18. " ATR_MCI_DAT_5 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 17. " ATR_MCI_DAT_4 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 16. " ATR_MCI_DAT_3 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 15. " ATR_MCI_DAT_2 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 14. " ATR_MCI_DAT_1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 13. " ATR_MCI_DAT_0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 12. " ATR_arm926_lp_nirq ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 11. " ATR_arm926_lp_nfiq ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 10. " ATR_I2c1_scl_n ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 9. " ATR_I2c0_scl_n ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 8. " ATR_uart_rxd ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 7. " ATR_wdog_m0 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 6. " ATR_adc_int ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 5. " ATR_timer3_intct1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 4. " ATR_timer2_intct1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 3. " ATR_timer1_intct1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 2. " ATR_timer0_intct1 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 1. " ATR_GPIO20 ,Activation type" "Direct,Latched(edge)" textline " " bitfld.long 0x0c 0. " ATR_GPIO19 ,Activation type" "Direct,Latched(edge)" rgroup.long 0xd20++0xf line.long 0x00 "RSR_0,Raw Status Register - Bank 0" bitfld.long 0x00 31. " RSR_EBI_D_6 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 30. " RSR_EBI_D_5 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " RSR_EBI_D_4 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 28. " RSR_EBI_D_3 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " RSR_EBI_D_2 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 26. " RSR_EBI_D_1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " RSR_EBI_D_0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " RSR_mNAND_RYBN3 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " RSR_mNAND_RYBN2 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 22. " RSR_mNAND_RYBN1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " RSR_mNAND_RYBN0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " RSR_mLCD_RW_WR ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " RSR_mLCD_E_RD ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " RSR_mLCD_CSB ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " RSR_mLCD_RS ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " RSR_mLCD_DB_15 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " RSR_mLCD_DB_14 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " RSR_mLCD_DB_13 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " RSR_mLCD_DB_12 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " RSR_mLCD_DB_11 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " RSR_mLCD_DB_10 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " RSR_mLCD_DB_9 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " RSR_mLCD_DB_8 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " RSR_mLCD_DB_7 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " RSR_mLCD_DB_6 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " RSR_mLCD_DB_5 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " RSR_mLCD_DB_4 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " RSR_mLCD_DB_3 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " RSR_mLCD_DB_2 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " RSR_mLCD_DB_1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " RSR_mLCD_DB_0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " RSR_pcm_int ,Raw status" "No interrupt,Interrupt" line.long 0x04 "RSR_1,Raw Status Register - Bank 1" bitfld.long 0x04 31. " RSR_GPIO16 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 30. " RSR_GPIO15 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 29. " RSR_GPIO14 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 28. " RSR_GPIO13 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 27. " RSR_GPIO12 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 26. " RSR_GPIO11 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 25. " RSR_mGPIO10 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 24. " RSR_mGPIO9 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 23. " RSR_mGPIO8 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 22. " RSR_mGPIO7 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 21. " RSR_mGPIO6 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 20. " RSR_mGPIO5 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 19. " RSR_GPIO4 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 18. " RSR_GPIO3 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 17. " RSR_GPIO2 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 16. " RSR_GPIO1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 15. " RSR_GPIO0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 14. " RSR_EBI_NRAS_BLOUT_1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 13. " RSR_EBI_NCAS_BLOUT_0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 12. " RSR_EBI_DQM_0_NOE ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 11. " RSR_EBI_A_1_CLE ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 10. " RSR_EBI_A_0_ALE ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 9. " RSR_EBI_NWE ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 8. " RSR_EBI_D_15 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 7. " RSR_EBI_D_14 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 6. " RSR_EBI_D_13 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 5. " RSR_EBI_D_12 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 4. " RSR_EBI_D_11 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 3. " RSR_EBI_D_10 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 2. " RSR_EBI_D_9 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 1. " RSR_EBI_D_8 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x04 0. " RSR_EBI_D_7 ,Raw status" "No interrupt,Interrupt" line.long 0x08 "RSR_2,Raw Status Register - Bank 2" bitfld.long 0x08 31. " RSR_PWM_DATA ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 30. " RSR_I2C_SCL1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 29. " RSR_I2C_SDA1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 28. " RSR_CLK_256FS_O ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 27. " RSR_I2STX_WS1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 26. " RSR_I2STX_BCK1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 25. " RSR_I2STX_DATA1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 24. " RSR_I2SRX_WS1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 23. " RSR_I2SRX_BCK1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 22. " RSR_I2SRX_DATA1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 21. " RSR_I2SRX_WS0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 20. " RSR_I2SRX_DATA0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 19. " RSR_I2SRX_BCK0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 18. " RSR_mI2STX_WS0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 17. " RSR_mI2STX_DATA0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 16. " RSR_mI2STX_BCK0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 15. " RSR_mI2STX_CLK0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 14. " RSR_mUART_RTS_N ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 13. " RSR_mUART_CTS_N ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 12. " RSR_UART_TXD ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 11. " RSR_UART_RXD ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 10. " RSR_SPI_CS_OUT0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 9. " RSR_SPI_SCK ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 8. " RSR_SPI_CS_IN ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 7. " RSR_SPI_MOSI ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 6. " RSR_SPI_MISO ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 5. " RSR_NAND_NCS_3 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 4. " RSR_NAND_NCS_2 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 3. " RSR_NAND_NCS_1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 2. " RSR_NAND_NCS_0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 1. " RSR_GPIO18 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x08 0. " RSR_GPIO17 ,Raw status" "No interrupt,Interrupt" line.long 0x0c "RSR_3,Raw Status Register - Bank 3" bitfld.long 0x0c 29. " RSR_isram1_mrc_finished ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 28. " RSR_isram0_mrc_finished ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 27. " RSR_USB_ID ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 26. " RSR_usb_otg_vbus_pwr_en ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 25. " RSR_usb_atx_pll_lock ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 24. " RSR_usb_otg_ahb_needclk ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 23. " RSR_USB_VBUS ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 22. " RSR_MCI_CLK ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 21. " RSR_MCI_CMD ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 20. " RSR_MCI_DAT_7 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 19. " RSR_MCI_DAT_6 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 18. " RSR_MCI_DAT_5 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 17. " RSR_MCI_DAT_4 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 16. " RSR_MCI_DAT_3 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 15. " RSR_MCI_DAT_2 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 14. " RSR_MCI_DAT_1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 13. " RSR_MCI_DAT_0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 12. " RSR_arm926_lp_nirq ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 11. " RSR_arm926_lp_nfiq ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 10. " RSR_I2c1_scl_n ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 9. " RSR_I2c0_scl_n ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 8. " RSR_uart_rxd ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 7. " RSR_wdog_m0 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 6. " RSR_adc_int ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 5. " RSR_timer3_intct1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 4. " RSR_timer2_intct1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 3. " RSR_timer1_intct1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 2. " RSR_timer0_intct1 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 1. " RSR_GPIO20 ,Raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x0c 0. " RSR_GPIO19 ,Raw status" "No interrupt,Interrupt" tree.end tree "Interrupt Outputs Status" group.long 0xd40++0x3 line.long 0x00 "INTOUT,Status of interrupt output pins" bitfld.long 0x00 4. " CGU_WAKEUP ,Current state of cgu_wakeup output" "Low,High" bitfld.long 0x00 3. " INTOUT3 ,Current state of interrupt output 3" "Low,High" bitfld.long 0x00 2. " INTOUT2 ,Current state of interrupt output 2" "Low,High" bitfld.long 0x00 1. " INTOUT1 ,Current state of interrupt output 1" "Low,High" textline " " bitfld.long 0x00 0. " INTOUT0 ,Current state of interrupt output 0" "Low,High" tree.end width 15. tree "Interrupt Output 0" group.long (0x1000+0x0)++0xf line.long 0x00 "INTOUTPEND_00,Interrupt Output Pending Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTPEND_EBI_D_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTPEND_EBI_D_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTPEND_EBI_D_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTPEND_EBI_D_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTPEND_EBI_D_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTPEND_EBI_D_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTPEND_EBI_D_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTPEND_mNAND_RYBN3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTPEND_mNAND_RYBN2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTPEND_mNAND_RYBN1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTPEND_mNAND_RYBN0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTPEND_mLCD_RW_WR_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTPEND_mLCD_E_RD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTPEND_mLCD_CSB_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTPEND_mLCD_RS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTPEND_mLCD_DB_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTPEND_mLCD_DB_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTPEND_mLCD_DB_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTPEND_mLCD_DB_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTPEND_mLCD_DB_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTPEND_mLCD_DB_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTPEND_mLCD_DB_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTPEND_mLCD_DB_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTPEND_mLCD_DB_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTPEND_mLCD_DB_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTPEND_mLCD_DB_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTPEND_mLCD_DB_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTPEND_mLCD_DB_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTPEND_mLCD_DB_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTPEND_mLCD_DB_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTPEND_mLCD_DB_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTPEND_pcm_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x04 "INTOUTPEND_01,Interrupt Output Pending Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTPEND_GPIO16_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTPEND_GPIO15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTPEND_GPIO14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTPEND_GPIO13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTPEND_GPIO12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTPEND_GPIO11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTPEND_mGPIO10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTPEND_mGPIO9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTPEND_mGPIO8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTPEND_mGPIO7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTPEND_mGPIO6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTPEND_mGPIO5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTPEND_GPIO4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTPEND_GPIO3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTPEND_GPIO2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTPEND_GPIO1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTPEND_GPIO0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTPEND_EBI_NRAS_BLOUT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTPEND_EBI_NCAS_BLOUT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTPEND_EBI_DQM_0_NOE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTPEND_EBI_A_1_CLE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTPEND_EBI_A_0_ALE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTPEND_EBI_NWE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTPEND_EBI_D_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTPEND_EBI_D_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTPEND_EBI_D_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTPEND_EBI_D_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTPEND_EBI_D_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTPEND_EBI_D_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTPEND_EBI_D_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTPEND_EBI_D_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTPEND_EBI_D_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x08 "INTOUTPEND_02,Interrupt Output Pending Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTPEND_PWM_DATA_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTPEND_I2C_SCL1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTPEND_I2C_SDA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTPEND_CLK_256FS_O_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTPEND_I2STX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTPEND_I2STX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTPEND_I2STX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTPEND_I2SRX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTPEND_I2SRX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTPEND_I2SRX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTPEND_I2SRX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTPEND_I2SRX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTPEND_I2SRX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTPEND_mI2STX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTPEND_mI2STX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTPEND_mI2STX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTPEND_mI2STX_CLK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTPEND_mUART_RTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTPEND_mUART_CTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTPEND_UART_TXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTPEND_UART_RXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTPEND_SPI_CS_OUT0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTPEND_SPI_SCK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTPEND_SPI_CS_IN_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTPEND_SPI_MOSI_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTPEND_SPI_MISO_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTPEND_NAND_NCS_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTPEND_NAND_NCS_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTPEND_NAND_NCS_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTPEND_NAND_NCS_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTPEND_GPIO18_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTPEND_GPIO17_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x0c "INTOUTPEND_03,Interrupt Output Pending Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTPEND_isram1_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTPEND_isram0_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTPEND_USB_ID_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTPEND_usb_otg_vbus_pwr_en_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTPEND_usb_atx_pll_lock_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTPEND_usb_otg_ahb_needclk_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTPEND_USB_VBUS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTPEND_MCI_CLK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTPEND_MCI_CMD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTPEND_MCI_DAT_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTPEND_MCI_DAT_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTPEND_MCI_DAT_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTPEND_MCI_DAT_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTPEND_MCI_DAT_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTPEND_MCI_DAT_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTPEND_MCI_DAT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTPEND_MCI_DAT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTPEND_arm926_lp_nirq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTPEND_arm926_lp_nfiq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTPEND_I2c1_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTPEND_I2c0_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTPEND_uart_rxd_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTPEND_wdog_m0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTPEND_adc_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTPEND_timer3_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTPEND_timer2_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTPEND_timer1_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTPEND_timer0_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTPEND_GPIO20_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTPEND_GPIO19_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" group.long (0x1400+0x0)++0xf line.long 0x00 "INTOUTMASK_00,Interrupt Output Mask Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTMASK_EBI_D_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTMASK_EBI_D_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTMASK_EBI_D_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTMASK_EBI_D_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTMASK_EBI_D_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTMASK_EBI_D_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTMASK_EBI_D_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTMASK_mNAND_RYBN3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTMASK_mNAND_RYBN2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTMASK_mNAND_RYBN1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTMASK_mNAND_RYBN0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTMASK_mLCD_RW_WR_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTMASK_mLCD_E_RD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTMASK_mLCD_CSB_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTMASK_mLCD_RS_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTMASK_mLCD_DB_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTMASK_mLCD_DB_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTMASK_mLCD_DB_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTMASK_mLCD_DB_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTMASK_mLCD_DB_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTMASK_mLCD_DB_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTMASK_mLCD_DB_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTMASK_mLCD_DB_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTMASK_mLCD_DB_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTMASK_mLCD_DB_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTMASK_mLCD_DB_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTMASK_mLCD_DB_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTMASK_mLCD_DB_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTMASK_mLCD_DB_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTMASK_mLCD_DB_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTMASK_mLCD_DB_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTMASK_pcm_int_set/clr ,Input Event From PCM" "Masked,Not masked" line.long 0x04 "INTOUTMASK_01,Interrupt Output Mask Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTMASK_GPIO16_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTMASK_GPIO15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTMASK_GPIO14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTMASK_GPIO13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTMASK_GPIO12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTMASK_GPIO11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTMASK_mGPIO10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTMASK_mGPIO9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTMASK_mGPIO8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTMASK_mGPIO7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTMASK_mGPIO6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTMASK_mGPIO5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTMASK_GPIO4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTMASK_GPIO3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTMASK_GPIO2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTMASK_GPIO1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTMASK_GPIO0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTMASK_EBI_NRAS_BLOUT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTMASK_EBI_NCAS_BLOUT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTMASK_EBI_DQM_0_NOE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTMASK_EBI_A_1_CLE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTMASK_EBI_A_0_ALE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTMASK_EBI_NWE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTMASK_EBI_D_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTMASK_EBI_D_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTMASK_EBI_D_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTMASK_EBI_D_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTMASK_EBI_D_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTMASK_EBI_D_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTMASK_EBI_D_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTMASK_EBI_D_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTMASK_EBI_D_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x08 "INTOUTMASK_02,Interrupt Output Mask Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTMASK_PWM_DATA_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTMASK_I2C_SCL1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTMASK_I2C_SDA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTMASK_CLK_256FS_O_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTMASK_I2STX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTMASK_I2STX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTMASK_I2STX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTMASK_I2SRX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTMASK_I2SRX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTMASK_I2SRX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTMASK_I2SRX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTMASK_I2SRX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTMASK_I2SRX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTMASK_mI2STX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTMASK_mI2STX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTMASK_mI2STX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTMASK_mI2STX_CLK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTMASK_mUART_RTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTMASK_mUART_CTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTMASK_UART_TXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTMASK_UART_RXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTMASK_SPI_CS_OUT0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTMASK_SPI_SCK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTMASK_SPI_CS_IN_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTMASK_SPI_MOSI_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTMASK_SPI_MISO_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTMASK_NAND_NCS_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTMASK_NAND_NCS_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTMASK_NAND_NCS_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTMASK_NAND_NCS_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTMASK_GPIO18_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTMASK_GPIO17_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x0c "INTOUTMASK_03,Interrupt Output Mask Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTMASK_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTMASK_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTMASK_USB_ID_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTMASK_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTMASK_usb_atx_pll_lock_set/clr ,USB PLL lock event" "Masked,Not masked" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTMASK_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTMASK_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTMASK_MCI_CLK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTMASK_MCI_CMD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTMASK_MCI_DAT_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTMASK_MCI_DAT_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTMASK_MCI_DAT_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTMASK_MCI_DAT_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTMASK_MCI_DAT_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTMASK_MCI_DAT_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTMASK_MCI_DAT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTMASK_MCI_DAT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTMASK_arm926_lp_nirq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTMASK_arm926_lp_nfiq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTMASK_I2c1_scl_n_set/clr , Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTMASK_I2c0_scl_n_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTMASK_uart_rxd_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTMASK_wdog_m0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTMASK_adc_int_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTMASK_timer3_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTMASK_timer2_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTMASK_timer1_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTMASK_timer0_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTMASK_GPIO20_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTMASK_GPIO19_set/clr ,Interrupt Output Mask" "Masked,Not masked" tree.end width 15. tree "Interrupt Output 1" group.long (0x1000+0x20)++0xf line.long 0x00 "INTOUTPEND_10,Interrupt Output Pending Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTPEND_EBI_D_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTPEND_EBI_D_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTPEND_EBI_D_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTPEND_EBI_D_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTPEND_EBI_D_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTPEND_EBI_D_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTPEND_EBI_D_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTPEND_mNAND_RYBN3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTPEND_mNAND_RYBN2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTPEND_mNAND_RYBN1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTPEND_mNAND_RYBN0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTPEND_mLCD_RW_WR_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTPEND_mLCD_E_RD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTPEND_mLCD_CSB_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTPEND_mLCD_RS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTPEND_mLCD_DB_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTPEND_mLCD_DB_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTPEND_mLCD_DB_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTPEND_mLCD_DB_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTPEND_mLCD_DB_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTPEND_mLCD_DB_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTPEND_mLCD_DB_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTPEND_mLCD_DB_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTPEND_mLCD_DB_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTPEND_mLCD_DB_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTPEND_mLCD_DB_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTPEND_mLCD_DB_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTPEND_mLCD_DB_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTPEND_mLCD_DB_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTPEND_mLCD_DB_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTPEND_mLCD_DB_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTPEND_pcm_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x04 "INTOUTPEND_11,Interrupt Output Pending Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTPEND_GPIO16_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTPEND_GPIO15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTPEND_GPIO14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTPEND_GPIO13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTPEND_GPIO12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTPEND_GPIO11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTPEND_mGPIO10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTPEND_mGPIO9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTPEND_mGPIO8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTPEND_mGPIO7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTPEND_mGPIO6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTPEND_mGPIO5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTPEND_GPIO4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTPEND_GPIO3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTPEND_GPIO2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTPEND_GPIO1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTPEND_GPIO0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTPEND_EBI_NRAS_BLOUT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTPEND_EBI_NCAS_BLOUT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTPEND_EBI_DQM_0_NOE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTPEND_EBI_A_1_CLE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTPEND_EBI_A_0_ALE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTPEND_EBI_NWE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTPEND_EBI_D_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTPEND_EBI_D_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTPEND_EBI_D_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTPEND_EBI_D_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTPEND_EBI_D_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTPEND_EBI_D_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTPEND_EBI_D_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTPEND_EBI_D_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTPEND_EBI_D_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x08 "INTOUTPEND_12,Interrupt Output Pending Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTPEND_PWM_DATA_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTPEND_I2C_SCL1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTPEND_I2C_SDA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTPEND_CLK_256FS_O_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTPEND_I2STX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTPEND_I2STX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTPEND_I2STX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTPEND_I2SRX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTPEND_I2SRX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTPEND_I2SRX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTPEND_I2SRX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTPEND_I2SRX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTPEND_I2SRX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTPEND_mI2STX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTPEND_mI2STX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTPEND_mI2STX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTPEND_mI2STX_CLK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTPEND_mUART_RTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTPEND_mUART_CTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTPEND_UART_TXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTPEND_UART_RXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTPEND_SPI_CS_OUT0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTPEND_SPI_SCK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTPEND_SPI_CS_IN_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTPEND_SPI_MOSI_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTPEND_SPI_MISO_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTPEND_NAND_NCS_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTPEND_NAND_NCS_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTPEND_NAND_NCS_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTPEND_NAND_NCS_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTPEND_GPIO18_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTPEND_GPIO17_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x0c "INTOUTPEND_13,Interrupt Output Pending Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTPEND_isram1_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTPEND_isram0_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTPEND_USB_ID_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTPEND_usb_otg_vbus_pwr_en_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTPEND_usb_atx_pll_lock_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTPEND_usb_otg_ahb_needclk_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTPEND_USB_VBUS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTPEND_MCI_CLK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTPEND_MCI_CMD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTPEND_MCI_DAT_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTPEND_MCI_DAT_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTPEND_MCI_DAT_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTPEND_MCI_DAT_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTPEND_MCI_DAT_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTPEND_MCI_DAT_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTPEND_MCI_DAT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTPEND_MCI_DAT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTPEND_arm926_lp_nirq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTPEND_arm926_lp_nfiq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTPEND_I2c1_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTPEND_I2c0_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTPEND_uart_rxd_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTPEND_wdog_m0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTPEND_adc_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTPEND_timer3_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTPEND_timer2_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTPEND_timer1_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTPEND_timer0_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTPEND_GPIO20_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTPEND_GPIO19_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" group.long (0x1400+0x20)++0xf line.long 0x00 "INTOUTMASK_10,Interrupt Output Mask Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTMASK_EBI_D_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTMASK_EBI_D_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTMASK_EBI_D_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTMASK_EBI_D_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTMASK_EBI_D_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTMASK_EBI_D_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTMASK_EBI_D_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTMASK_mNAND_RYBN3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTMASK_mNAND_RYBN2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTMASK_mNAND_RYBN1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTMASK_mNAND_RYBN0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTMASK_mLCD_RW_WR_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTMASK_mLCD_E_RD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTMASK_mLCD_CSB_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTMASK_mLCD_RS_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTMASK_mLCD_DB_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTMASK_mLCD_DB_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTMASK_mLCD_DB_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTMASK_mLCD_DB_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTMASK_mLCD_DB_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTMASK_mLCD_DB_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTMASK_mLCD_DB_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTMASK_mLCD_DB_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTMASK_mLCD_DB_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTMASK_mLCD_DB_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTMASK_mLCD_DB_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTMASK_mLCD_DB_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTMASK_mLCD_DB_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTMASK_mLCD_DB_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTMASK_mLCD_DB_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTMASK_mLCD_DB_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTMASK_pcm_int_set/clr ,Input Event From PCM" "Masked,Not masked" line.long 0x04 "INTOUTMASK_11,Interrupt Output Mask Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTMASK_GPIO16_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTMASK_GPIO15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTMASK_GPIO14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTMASK_GPIO13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTMASK_GPIO12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTMASK_GPIO11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTMASK_mGPIO10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTMASK_mGPIO9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTMASK_mGPIO8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTMASK_mGPIO7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTMASK_mGPIO6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTMASK_mGPIO5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTMASK_GPIO4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTMASK_GPIO3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTMASK_GPIO2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTMASK_GPIO1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTMASK_GPIO0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTMASK_EBI_NRAS_BLOUT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTMASK_EBI_NCAS_BLOUT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTMASK_EBI_DQM_0_NOE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTMASK_EBI_A_1_CLE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTMASK_EBI_A_0_ALE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTMASK_EBI_NWE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTMASK_EBI_D_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTMASK_EBI_D_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTMASK_EBI_D_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTMASK_EBI_D_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTMASK_EBI_D_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTMASK_EBI_D_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTMASK_EBI_D_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTMASK_EBI_D_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTMASK_EBI_D_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x08 "INTOUTMASK_12,Interrupt Output Mask Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTMASK_PWM_DATA_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTMASK_I2C_SCL1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTMASK_I2C_SDA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTMASK_CLK_256FS_O_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTMASK_I2STX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTMASK_I2STX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTMASK_I2STX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTMASK_I2SRX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTMASK_I2SRX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTMASK_I2SRX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTMASK_I2SRX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTMASK_I2SRX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTMASK_I2SRX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTMASK_mI2STX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTMASK_mI2STX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTMASK_mI2STX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTMASK_mI2STX_CLK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTMASK_mUART_RTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTMASK_mUART_CTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTMASK_UART_TXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTMASK_UART_RXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTMASK_SPI_CS_OUT0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTMASK_SPI_SCK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTMASK_SPI_CS_IN_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTMASK_SPI_MOSI_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTMASK_SPI_MISO_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTMASK_NAND_NCS_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTMASK_NAND_NCS_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTMASK_NAND_NCS_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTMASK_NAND_NCS_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTMASK_GPIO18_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTMASK_GPIO17_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x0c "INTOUTMASK_13,Interrupt Output Mask Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTMASK_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTMASK_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTMASK_USB_ID_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTMASK_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTMASK_usb_atx_pll_lock_set/clr ,USB PLL lock event" "Masked,Not masked" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTMASK_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTMASK_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTMASK_MCI_CLK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTMASK_MCI_CMD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTMASK_MCI_DAT_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTMASK_MCI_DAT_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTMASK_MCI_DAT_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTMASK_MCI_DAT_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTMASK_MCI_DAT_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTMASK_MCI_DAT_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTMASK_MCI_DAT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTMASK_MCI_DAT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTMASK_arm926_lp_nirq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTMASK_arm926_lp_nfiq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTMASK_I2c1_scl_n_set/clr , Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTMASK_I2c0_scl_n_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTMASK_uart_rxd_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTMASK_wdog_m0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTMASK_adc_int_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTMASK_timer3_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTMASK_timer2_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTMASK_timer1_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTMASK_timer0_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTMASK_GPIO20_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTMASK_GPIO19_set/clr ,Interrupt Output Mask" "Masked,Not masked" tree.end width 15. tree "Interrupt Output 2" group.long (0x1000+0x40)++0xf line.long 0x00 "INTOUTPEND_20,Interrupt Output Pending Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTPEND_EBI_D_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTPEND_EBI_D_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTPEND_EBI_D_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTPEND_EBI_D_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTPEND_EBI_D_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTPEND_EBI_D_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTPEND_EBI_D_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTPEND_mNAND_RYBN3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTPEND_mNAND_RYBN2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTPEND_mNAND_RYBN1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTPEND_mNAND_RYBN0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTPEND_mLCD_RW_WR_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTPEND_mLCD_E_RD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTPEND_mLCD_CSB_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTPEND_mLCD_RS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTPEND_mLCD_DB_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTPEND_mLCD_DB_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTPEND_mLCD_DB_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTPEND_mLCD_DB_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTPEND_mLCD_DB_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTPEND_mLCD_DB_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTPEND_mLCD_DB_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTPEND_mLCD_DB_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTPEND_mLCD_DB_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTPEND_mLCD_DB_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTPEND_mLCD_DB_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTPEND_mLCD_DB_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTPEND_mLCD_DB_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTPEND_mLCD_DB_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTPEND_mLCD_DB_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTPEND_mLCD_DB_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTPEND_pcm_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x04 "INTOUTPEND_21,Interrupt Output Pending Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTPEND_GPIO16_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTPEND_GPIO15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTPEND_GPIO14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTPEND_GPIO13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTPEND_GPIO12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTPEND_GPIO11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTPEND_mGPIO10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTPEND_mGPIO9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTPEND_mGPIO8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTPEND_mGPIO7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTPEND_mGPIO6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTPEND_mGPIO5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTPEND_GPIO4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTPEND_GPIO3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTPEND_GPIO2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTPEND_GPIO1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTPEND_GPIO0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTPEND_EBI_NRAS_BLOUT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTPEND_EBI_NCAS_BLOUT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTPEND_EBI_DQM_0_NOE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTPEND_EBI_A_1_CLE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTPEND_EBI_A_0_ALE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTPEND_EBI_NWE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTPEND_EBI_D_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTPEND_EBI_D_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTPEND_EBI_D_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTPEND_EBI_D_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTPEND_EBI_D_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTPEND_EBI_D_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTPEND_EBI_D_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTPEND_EBI_D_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTPEND_EBI_D_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x08 "INTOUTPEND_22,Interrupt Output Pending Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTPEND_PWM_DATA_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTPEND_I2C_SCL1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTPEND_I2C_SDA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTPEND_CLK_256FS_O_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTPEND_I2STX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTPEND_I2STX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTPEND_I2STX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTPEND_I2SRX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTPEND_I2SRX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTPEND_I2SRX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTPEND_I2SRX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTPEND_I2SRX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTPEND_I2SRX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTPEND_mI2STX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTPEND_mI2STX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTPEND_mI2STX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTPEND_mI2STX_CLK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTPEND_mUART_RTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTPEND_mUART_CTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTPEND_UART_TXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTPEND_UART_RXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTPEND_SPI_CS_OUT0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTPEND_SPI_SCK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTPEND_SPI_CS_IN_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTPEND_SPI_MOSI_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTPEND_SPI_MISO_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTPEND_NAND_NCS_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTPEND_NAND_NCS_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTPEND_NAND_NCS_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTPEND_NAND_NCS_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTPEND_GPIO18_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTPEND_GPIO17_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x0c "INTOUTPEND_23,Interrupt Output Pending Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTPEND_isram1_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTPEND_isram0_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTPEND_USB_ID_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTPEND_usb_otg_vbus_pwr_en_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTPEND_usb_atx_pll_lock_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTPEND_usb_otg_ahb_needclk_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTPEND_USB_VBUS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTPEND_MCI_CLK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTPEND_MCI_CMD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTPEND_MCI_DAT_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTPEND_MCI_DAT_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTPEND_MCI_DAT_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTPEND_MCI_DAT_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTPEND_MCI_DAT_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTPEND_MCI_DAT_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTPEND_MCI_DAT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTPEND_MCI_DAT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTPEND_arm926_lp_nirq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTPEND_arm926_lp_nfiq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTPEND_I2c1_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTPEND_I2c0_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTPEND_uart_rxd_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTPEND_wdog_m0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTPEND_adc_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTPEND_timer3_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTPEND_timer2_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTPEND_timer1_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTPEND_timer0_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTPEND_GPIO20_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTPEND_GPIO19_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" group.long (0x1400+0x40)++0xf line.long 0x00 "INTOUTMASK_20,Interrupt Output Mask Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTMASK_EBI_D_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTMASK_EBI_D_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTMASK_EBI_D_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTMASK_EBI_D_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTMASK_EBI_D_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTMASK_EBI_D_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTMASK_EBI_D_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTMASK_mNAND_RYBN3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTMASK_mNAND_RYBN2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTMASK_mNAND_RYBN1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTMASK_mNAND_RYBN0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTMASK_mLCD_RW_WR_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTMASK_mLCD_E_RD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTMASK_mLCD_CSB_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTMASK_mLCD_RS_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTMASK_mLCD_DB_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTMASK_mLCD_DB_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTMASK_mLCD_DB_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTMASK_mLCD_DB_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTMASK_mLCD_DB_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTMASK_mLCD_DB_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTMASK_mLCD_DB_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTMASK_mLCD_DB_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTMASK_mLCD_DB_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTMASK_mLCD_DB_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTMASK_mLCD_DB_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTMASK_mLCD_DB_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTMASK_mLCD_DB_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTMASK_mLCD_DB_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTMASK_mLCD_DB_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTMASK_mLCD_DB_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTMASK_pcm_int_set/clr ,Input Event From PCM" "Masked,Not masked" line.long 0x04 "INTOUTMASK_21,Interrupt Output Mask Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTMASK_GPIO16_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTMASK_GPIO15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTMASK_GPIO14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTMASK_GPIO13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTMASK_GPIO12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTMASK_GPIO11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTMASK_mGPIO10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTMASK_mGPIO9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTMASK_mGPIO8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTMASK_mGPIO7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTMASK_mGPIO6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTMASK_mGPIO5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTMASK_GPIO4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTMASK_GPIO3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTMASK_GPIO2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTMASK_GPIO1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTMASK_GPIO0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTMASK_EBI_NRAS_BLOUT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTMASK_EBI_NCAS_BLOUT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTMASK_EBI_DQM_0_NOE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTMASK_EBI_A_1_CLE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTMASK_EBI_A_0_ALE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTMASK_EBI_NWE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTMASK_EBI_D_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTMASK_EBI_D_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTMASK_EBI_D_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTMASK_EBI_D_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTMASK_EBI_D_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTMASK_EBI_D_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTMASK_EBI_D_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTMASK_EBI_D_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTMASK_EBI_D_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x08 "INTOUTMASK_22,Interrupt Output Mask Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTMASK_PWM_DATA_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTMASK_I2C_SCL1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTMASK_I2C_SDA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTMASK_CLK_256FS_O_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTMASK_I2STX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTMASK_I2STX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTMASK_I2STX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTMASK_I2SRX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTMASK_I2SRX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTMASK_I2SRX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTMASK_I2SRX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTMASK_I2SRX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTMASK_I2SRX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTMASK_mI2STX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTMASK_mI2STX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTMASK_mI2STX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTMASK_mI2STX_CLK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTMASK_mUART_RTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTMASK_mUART_CTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTMASK_UART_TXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTMASK_UART_RXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTMASK_SPI_CS_OUT0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTMASK_SPI_SCK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTMASK_SPI_CS_IN_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTMASK_SPI_MOSI_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTMASK_SPI_MISO_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTMASK_NAND_NCS_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTMASK_NAND_NCS_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTMASK_NAND_NCS_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTMASK_NAND_NCS_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTMASK_GPIO18_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTMASK_GPIO17_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x0c "INTOUTMASK_23,Interrupt Output Mask Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTMASK_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTMASK_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTMASK_USB_ID_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTMASK_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTMASK_usb_atx_pll_lock_set/clr ,USB PLL lock event" "Masked,Not masked" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTMASK_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTMASK_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTMASK_MCI_CLK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTMASK_MCI_CMD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTMASK_MCI_DAT_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTMASK_MCI_DAT_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTMASK_MCI_DAT_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTMASK_MCI_DAT_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTMASK_MCI_DAT_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTMASK_MCI_DAT_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTMASK_MCI_DAT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTMASK_MCI_DAT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTMASK_arm926_lp_nirq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTMASK_arm926_lp_nfiq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTMASK_I2c1_scl_n_set/clr , Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTMASK_I2c0_scl_n_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTMASK_uart_rxd_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTMASK_wdog_m0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTMASK_adc_int_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTMASK_timer3_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTMASK_timer2_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTMASK_timer1_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTMASK_timer0_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTMASK_GPIO20_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTMASK_GPIO19_set/clr ,Interrupt Output Mask" "Masked,Not masked" tree.end width 15. tree "Interrupt Output 3" group.long (0x1000+0x60)++0xf line.long 0x00 "INTOUTPEND_30,Interrupt Output Pending Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTPEND_EBI_D_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTPEND_EBI_D_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTPEND_EBI_D_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTPEND_EBI_D_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTPEND_EBI_D_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTPEND_EBI_D_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTPEND_EBI_D_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTPEND_mNAND_RYBN3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTPEND_mNAND_RYBN2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTPEND_mNAND_RYBN1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTPEND_mNAND_RYBN0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTPEND_mLCD_RW_WR_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTPEND_mLCD_E_RD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTPEND_mLCD_CSB_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTPEND_mLCD_RS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTPEND_mLCD_DB_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTPEND_mLCD_DB_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTPEND_mLCD_DB_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTPEND_mLCD_DB_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTPEND_mLCD_DB_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTPEND_mLCD_DB_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTPEND_mLCD_DB_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTPEND_mLCD_DB_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTPEND_mLCD_DB_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTPEND_mLCD_DB_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTPEND_mLCD_DB_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTPEND_mLCD_DB_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTPEND_mLCD_DB_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTPEND_mLCD_DB_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTPEND_mLCD_DB_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTPEND_mLCD_DB_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTPEND_pcm_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x04 "INTOUTPEND_31,Interrupt Output Pending Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTPEND_GPIO16_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTPEND_GPIO15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTPEND_GPIO14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTPEND_GPIO13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTPEND_GPIO12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTPEND_GPIO11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTPEND_mGPIO10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTPEND_mGPIO9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTPEND_mGPIO8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTPEND_mGPIO7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTPEND_mGPIO6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTPEND_mGPIO5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTPEND_GPIO4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTPEND_GPIO3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTPEND_GPIO2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTPEND_GPIO1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTPEND_GPIO0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTPEND_EBI_NRAS_BLOUT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTPEND_EBI_NCAS_BLOUT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTPEND_EBI_DQM_0_NOE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTPEND_EBI_A_1_CLE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTPEND_EBI_A_0_ALE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTPEND_EBI_NWE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTPEND_EBI_D_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTPEND_EBI_D_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTPEND_EBI_D_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTPEND_EBI_D_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTPEND_EBI_D_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTPEND_EBI_D_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTPEND_EBI_D_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTPEND_EBI_D_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTPEND_EBI_D_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x08 "INTOUTPEND_32,Interrupt Output Pending Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTPEND_PWM_DATA_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTPEND_I2C_SCL1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTPEND_I2C_SDA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTPEND_CLK_256FS_O_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTPEND_I2STX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTPEND_I2STX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTPEND_I2STX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTPEND_I2SRX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTPEND_I2SRX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTPEND_I2SRX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTPEND_I2SRX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTPEND_I2SRX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTPEND_I2SRX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTPEND_mI2STX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTPEND_mI2STX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTPEND_mI2STX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTPEND_mI2STX_CLK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTPEND_mUART_RTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTPEND_mUART_CTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTPEND_UART_TXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTPEND_UART_RXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTPEND_SPI_CS_OUT0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTPEND_SPI_SCK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTPEND_SPI_CS_IN_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTPEND_SPI_MOSI_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTPEND_SPI_MISO_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTPEND_NAND_NCS_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTPEND_NAND_NCS_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTPEND_NAND_NCS_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTPEND_NAND_NCS_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTPEND_GPIO18_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTPEND_GPIO17_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x0c "INTOUTPEND_33,Interrupt Output Pending Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTPEND_isram1_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTPEND_isram0_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTPEND_USB_ID_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTPEND_usb_otg_vbus_pwr_en_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTPEND_usb_atx_pll_lock_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTPEND_usb_otg_ahb_needclk_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTPEND_USB_VBUS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTPEND_MCI_CLK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTPEND_MCI_CMD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTPEND_MCI_DAT_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTPEND_MCI_DAT_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTPEND_MCI_DAT_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTPEND_MCI_DAT_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTPEND_MCI_DAT_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTPEND_MCI_DAT_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTPEND_MCI_DAT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTPEND_MCI_DAT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTPEND_arm926_lp_nirq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTPEND_arm926_lp_nfiq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTPEND_I2c1_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTPEND_I2c0_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTPEND_uart_rxd_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTPEND_wdog_m0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTPEND_adc_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTPEND_timer3_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTPEND_timer2_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTPEND_timer1_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTPEND_timer0_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTPEND_GPIO20_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTPEND_GPIO19_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" group.long (0x1400+0x60)++0xf line.long 0x00 "INTOUTMASK_30,Interrupt Output Mask Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTMASK_EBI_D_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTMASK_EBI_D_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTMASK_EBI_D_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTMASK_EBI_D_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTMASK_EBI_D_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTMASK_EBI_D_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTMASK_EBI_D_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTMASK_mNAND_RYBN3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTMASK_mNAND_RYBN2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTMASK_mNAND_RYBN1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTMASK_mNAND_RYBN0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTMASK_mLCD_RW_WR_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTMASK_mLCD_E_RD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTMASK_mLCD_CSB_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTMASK_mLCD_RS_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTMASK_mLCD_DB_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTMASK_mLCD_DB_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTMASK_mLCD_DB_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTMASK_mLCD_DB_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTMASK_mLCD_DB_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTMASK_mLCD_DB_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTMASK_mLCD_DB_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTMASK_mLCD_DB_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTMASK_mLCD_DB_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTMASK_mLCD_DB_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTMASK_mLCD_DB_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTMASK_mLCD_DB_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTMASK_mLCD_DB_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTMASK_mLCD_DB_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTMASK_mLCD_DB_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTMASK_mLCD_DB_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTMASK_pcm_int_set/clr ,Input Event From PCM" "Masked,Not masked" line.long 0x04 "INTOUTMASK_31,Interrupt Output Mask Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTMASK_GPIO16_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTMASK_GPIO15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTMASK_GPIO14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTMASK_GPIO13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTMASK_GPIO12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTMASK_GPIO11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTMASK_mGPIO10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTMASK_mGPIO9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTMASK_mGPIO8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTMASK_mGPIO7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTMASK_mGPIO6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTMASK_mGPIO5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTMASK_GPIO4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTMASK_GPIO3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTMASK_GPIO2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTMASK_GPIO1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTMASK_GPIO0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTMASK_EBI_NRAS_BLOUT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTMASK_EBI_NCAS_BLOUT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTMASK_EBI_DQM_0_NOE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTMASK_EBI_A_1_CLE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTMASK_EBI_A_0_ALE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTMASK_EBI_NWE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTMASK_EBI_D_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTMASK_EBI_D_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTMASK_EBI_D_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTMASK_EBI_D_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTMASK_EBI_D_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTMASK_EBI_D_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTMASK_EBI_D_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTMASK_EBI_D_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTMASK_EBI_D_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x08 "INTOUTMASK_32,Interrupt Output Mask Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTMASK_PWM_DATA_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTMASK_I2C_SCL1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTMASK_I2C_SDA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTMASK_CLK_256FS_O_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTMASK_I2STX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTMASK_I2STX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTMASK_I2STX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTMASK_I2SRX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTMASK_I2SRX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTMASK_I2SRX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTMASK_I2SRX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTMASK_I2SRX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTMASK_I2SRX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTMASK_mI2STX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTMASK_mI2STX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTMASK_mI2STX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTMASK_mI2STX_CLK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTMASK_mUART_RTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTMASK_mUART_CTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTMASK_UART_TXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTMASK_UART_RXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTMASK_SPI_CS_OUT0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTMASK_SPI_SCK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTMASK_SPI_CS_IN_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTMASK_SPI_MOSI_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTMASK_SPI_MISO_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTMASK_NAND_NCS_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTMASK_NAND_NCS_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTMASK_NAND_NCS_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTMASK_NAND_NCS_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTMASK_GPIO18_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTMASK_GPIO17_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x0c "INTOUTMASK_33,Interrupt Output Mask Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTMASK_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTMASK_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTMASK_USB_ID_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTMASK_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTMASK_usb_atx_pll_lock_set/clr ,USB PLL lock event" "Masked,Not masked" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTMASK_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTMASK_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTMASK_MCI_CLK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTMASK_MCI_CMD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTMASK_MCI_DAT_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTMASK_MCI_DAT_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTMASK_MCI_DAT_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTMASK_MCI_DAT_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTMASK_MCI_DAT_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTMASK_MCI_DAT_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTMASK_MCI_DAT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTMASK_MCI_DAT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTMASK_arm926_lp_nirq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTMASK_arm926_lp_nfiq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTMASK_I2c1_scl_n_set/clr , Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTMASK_I2c0_scl_n_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTMASK_uart_rxd_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTMASK_wdog_m0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTMASK_adc_int_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTMASK_timer3_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTMASK_timer2_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTMASK_timer1_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTMASK_timer0_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTMASK_GPIO20_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTMASK_GPIO19_set/clr ,Interrupt Output Mask" "Masked,Not masked" tree.end width 15. tree "CGU Wakeup Output" group.long (0x1000+0x80)++0xf line.long 0x00 "INTOUTPEND_40,Interrupt Output Pending Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTPEND_EBI_D_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTPEND_EBI_D_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTPEND_EBI_D_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTPEND_EBI_D_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTPEND_EBI_D_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTPEND_EBI_D_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTPEND_EBI_D_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTPEND_mNAND_RYBN3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTPEND_mNAND_RYBN2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTPEND_mNAND_RYBN1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTPEND_mNAND_RYBN0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTPEND_mLCD_RW_WR_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTPEND_mLCD_E_RD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTPEND_mLCD_CSB_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTPEND_mLCD_RS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTPEND_mLCD_DB_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTPEND_mLCD_DB_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTPEND_mLCD_DB_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTPEND_mLCD_DB_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTPEND_mLCD_DB_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTPEND_mLCD_DB_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTPEND_mLCD_DB_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTPEND_mLCD_DB_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTPEND_mLCD_DB_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTPEND_mLCD_DB_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTPEND_mLCD_DB_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTPEND_mLCD_DB_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTPEND_mLCD_DB_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTPEND_mLCD_DB_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTPEND_mLCD_DB_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTPEND_mLCD_DB_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTPEND_pcm_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x04 "INTOUTPEND_41,Interrupt Output Pending Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTPEND_GPIO16_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTPEND_GPIO15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTPEND_GPIO14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTPEND_GPIO13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTPEND_GPIO12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTPEND_GPIO11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTPEND_mGPIO10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTPEND_mGPIO9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTPEND_mGPIO8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTPEND_mGPIO7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTPEND_mGPIO6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTPEND_mGPIO5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTPEND_GPIO4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTPEND_GPIO3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTPEND_GPIO2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTPEND_GPIO1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTPEND_GPIO0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTPEND_EBI_NRAS_BLOUT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTPEND_EBI_NCAS_BLOUT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTPEND_EBI_DQM_0_NOE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTPEND_EBI_A_1_CLE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTPEND_EBI_A_0_ALE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTPEND_EBI_NWE_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTPEND_EBI_D_15_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTPEND_EBI_D_14_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTPEND_EBI_D_13_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTPEND_EBI_D_12_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTPEND_EBI_D_11_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTPEND_EBI_D_10_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTPEND_EBI_D_9_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTPEND_EBI_D_8_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTPEND_EBI_D_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x08 "INTOUTPEND_42,Interrupt Output Pending Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTPEND_PWM_DATA_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTPEND_I2C_SCL1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTPEND_I2C_SDA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTPEND_CLK_256FS_O_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTPEND_I2STX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTPEND_I2STX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTPEND_I2STX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTPEND_I2SRX_WS1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTPEND_I2SRX_BCK1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTPEND_I2SRX_DATA1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTPEND_I2SRX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTPEND_I2SRX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTPEND_I2SRX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTPEND_mI2STX_WS0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTPEND_mI2STX_DATA0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTPEND_mI2STX_BCK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTPEND_mI2STX_CLK0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTPEND_mUART_RTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTPEND_mUART_CTS_N_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTPEND_UART_TXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTPEND_UART_RXD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTPEND_SPI_CS_OUT0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTPEND_SPI_SCK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTPEND_SPI_CS_IN_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTPEND_SPI_MOSI_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTPEND_SPI_MISO_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTPEND_NAND_NCS_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTPEND_NAND_NCS_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTPEND_NAND_NCS_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTPEND_NAND_NCS_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTPEND_GPIO18_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTPEND_GPIO17_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" line.long 0x0c "INTOUTPEND_43,Interrupt Output Pending Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTPEND_isram1_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTPEND_isram0_mrc_finished_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTPEND_USB_ID_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTPEND_usb_otg_vbus_pwr_en_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTPEND_usb_atx_pll_lock_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTPEND_usb_otg_ahb_needclk_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTPEND_USB_VBUS_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTPEND_MCI_CLK_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTPEND_MCI_CMD_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTPEND_MCI_DAT_7_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTPEND_MCI_DAT_6_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTPEND_MCI_DAT_5_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTPEND_MCI_DAT_4_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTPEND_MCI_DAT_3_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTPEND_MCI_DAT_2_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTPEND_MCI_DAT_1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTPEND_MCI_DAT_0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTPEND_arm926_lp_nirq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTPEND_arm926_lp_nfiq_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTPEND_I2c1_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTPEND_I2c0_scl_n_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTPEND_uart_rxd_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTPEND_wdog_m0_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTPEND_adc_int_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTPEND_timer3_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTPEND_timer2_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTPEND_timer1_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTPEND_timer0_intct1_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTPEND_GPIO20_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTPEND_GPIO19_set/clr ,Event For Interrupt Output" "No interrupt,Interrupt" group.long (0x1400+0x80)++0xf line.long 0x00 "INTOUTMASK_40,Interrupt Output Mask Register - Bank 0" setclrfld.long 0x00 31. 0x40 31. 0x20 31. " INTOUTMASK_EBI_D_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 30. 0x40 30. 0x20 30. " INTOUTMASK_EBI_D_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 29. 0x40 29. 0x20 29. " INTOUTMASK_EBI_D_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 28. 0x40 28. 0x20 28. " INTOUTMASK_EBI_D_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 27. 0x40 27. 0x20 27. " INTOUTMASK_EBI_D_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 26. 0x40 26. 0x20 26. " INTOUTMASK_EBI_D_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 25. 0x40 25. 0x20 25. " INTOUTMASK_EBI_D_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 24. 0x40 24. 0x20 24. " INTOUTMASK_mNAND_RYBN3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 23. 0x40 23. 0x20 23. " INTOUTMASK_mNAND_RYBN2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 22. 0x40 22. 0x20 22. " INTOUTMASK_mNAND_RYBN1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 21. 0x40 21. 0x20 21. " INTOUTMASK_mNAND_RYBN0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 20. 0x40 20. 0x20 20. " INTOUTMASK_mLCD_RW_WR_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 19. 0x40 19. 0x20 19. " INTOUTMASK_mLCD_E_RD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 18. 0x40 18. 0x20 18. " INTOUTMASK_mLCD_CSB_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 17. 0x40 17. 0x20 17. " INTOUTMASK_mLCD_RS_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 16. 0x40 16. 0x20 16. " INTOUTMASK_mLCD_DB_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 15. 0x40 15. 0x20 15. " INTOUTMASK_mLCD_DB_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 14. 0x40 14. 0x20 14. " INTOUTMASK_mLCD_DB_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 13. 0x40 13. 0x20 13. " INTOUTMASK_mLCD_DB_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 12. 0x40 12. 0x20 12. " INTOUTMASK_mLCD_DB_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 11. 0x40 11. 0x20 11. " INTOUTMASK_mLCD_DB_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 10. 0x40 10. 0x20 10. " INTOUTMASK_mLCD_DB_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 9. 0x40 9. 0x20 9. " INTOUTMASK_mLCD_DB_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 8. 0x40 8. 0x20 8. " INTOUTMASK_mLCD_DB_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 7. 0x40 7. 0x20 7. " INTOUTMASK_mLCD_DB_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 6. 0x40 6. 0x20 6. " INTOUTMASK_mLCD_DB_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 5. 0x40 5. 0x20 5. " INTOUTMASK_mLCD_DB_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 4. 0x40 4. 0x20 4. " INTOUTMASK_mLCD_DB_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 3. 0x40 3. 0x20 3. " INTOUTMASK_mLCD_DB_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 2. 0x40 2. 0x20 2. " INTOUTMASK_mLCD_DB_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 1. 0x40 1. 0x20 1. " INTOUTMASK_mLCD_DB_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x00 0. 0x40 0. 0x20 0. " INTOUTMASK_pcm_int_set/clr ,Input Event From PCM" "Masked,Not masked" line.long 0x04 "INTOUTMASK_41,Interrupt Output Mask Register - Bank 1" setclrfld.long 0x04 31. 0x44 31. 0x24 31. " INTOUTMASK_GPIO16_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 30. 0x44 30. 0x24 30. " INTOUTMASK_GPIO15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 29. 0x44 29. 0x24 29. " INTOUTMASK_GPIO14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 28. 0x44 28. 0x24 28. " INTOUTMASK_GPIO13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 27. 0x44 27. 0x24 27. " INTOUTMASK_GPIO12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 26. 0x44 26. 0x24 26. " INTOUTMASK_GPIO11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 25. 0x44 25. 0x24 25. " INTOUTMASK_mGPIO10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 24. 0x44 24. 0x24 24. " INTOUTMASK_mGPIO9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 23. 0x44 23. 0x24 23. " INTOUTMASK_mGPIO8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 22. 0x44 22. 0x24 22. " INTOUTMASK_mGPIO7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 21. 0x44 21. 0x24 21. " INTOUTMASK_mGPIO6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 20. 0x44 20. 0x24 20. " INTOUTMASK_mGPIO5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 19. 0x44 19. 0x24 19. " INTOUTMASK_GPIO4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 18. 0x44 18. 0x24 18. " INTOUTMASK_GPIO3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 17. 0x44 17. 0x24 17. " INTOUTMASK_GPIO2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 16. 0x44 16. 0x24 16. " INTOUTMASK_GPIO1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 15. 0x44 15. 0x24 15. " INTOUTMASK_GPIO0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 14. 0x44 14. 0x24 14. " INTOUTMASK_EBI_NRAS_BLOUT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 13. 0x44 13. 0x24 13. " INTOUTMASK_EBI_NCAS_BLOUT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 12. 0x44 12. 0x24 12. " INTOUTMASK_EBI_DQM_0_NOE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 11. 0x44 11. 0x24 11. " INTOUTMASK_EBI_A_1_CLE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 10. 0x44 10. 0x24 10. " INTOUTMASK_EBI_A_0_ALE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 9. 0x44 9. 0x24 9. " INTOUTMASK_EBI_NWE_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 8. 0x44 8. 0x24 8. " INTOUTMASK_EBI_D_15_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 7. 0x44 7. 0x24 7. " INTOUTMASK_EBI_D_14_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 6. 0x44 6. 0x24 6. " INTOUTMASK_EBI_D_13_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 5. 0x44 5. 0x24 5. " INTOUTMASK_EBI_D_12_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 4. 0x44 4. 0x24 4. " INTOUTMASK_EBI_D_11_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 3. 0x44 3. 0x24 3. " INTOUTMASK_EBI_D_10_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 2. 0x44 2. 0x24 2. " INTOUTMASK_EBI_D_9_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 1. 0x44 1. 0x24 1. " INTOUTMASK_EBI_D_8_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x04 0. 0x44 0. 0x24 0. " INTOUTMASK_EBI_D_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x08 "INTOUTMASK_42,Interrupt Output Mask Register - Bank 2" setclrfld.long 0x08 31. 0x48 31. 0x28 31. " INTOUTMASK_PWM_DATA_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 30. 0x48 30. 0x28 30. " INTOUTMASK_I2C_SCL1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 29. 0x48 29. 0x28 29. " INTOUTMASK_I2C_SDA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 28. 0x48 28. 0x28 28. " INTOUTMASK_CLK_256FS_O_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 27. 0x48 27. 0x28 27. " INTOUTMASK_I2STX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 26. 0x48 26. 0x28 26. " INTOUTMASK_I2STX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 25. 0x48 25. 0x28 25. " INTOUTMASK_I2STX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 24. 0x48 24. 0x28 24. " INTOUTMASK_I2SRX_WS1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 23. 0x48 23. 0x28 23. " INTOUTMASK_I2SRX_BCK1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 22. 0x48 22. 0x28 22. " INTOUTMASK_I2SRX_DATA1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 21. 0x48 21. 0x28 21. " INTOUTMASK_I2SRX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 20. 0x48 20. 0x28 20. " INTOUTMASK_I2SRX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 19. 0x48 19. 0x28 19. " INTOUTMASK_I2SRX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 18. 0x48 18. 0x28 18. " INTOUTMASK_mI2STX_WS0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 17. 0x48 17. 0x28 17. " INTOUTMASK_mI2STX_DATA0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 16. 0x48 16. 0x28 16. " INTOUTMASK_mI2STX_BCK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 15. 0x48 15. 0x28 15. " INTOUTMASK_mI2STX_CLK0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 14. 0x48 14. 0x28 14. " INTOUTMASK_mUART_RTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 13. 0x48 13. 0x28 13. " INTOUTMASK_mUART_CTS_N_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 12. 0x48 12. 0x28 12. " INTOUTMASK_UART_TXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 11. 0x48 11. 0x28 11. " INTOUTMASK_UART_RXD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 10. 0x48 10. 0x28 10. " INTOUTMASK_SPI_CS_OUT0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 9. 0x48 9. 0x28 9. " INTOUTMASK_SPI_SCK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 8. 0x48 8. 0x28 8. " INTOUTMASK_SPI_CS_IN_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 7. 0x48 7. 0x28 7. " INTOUTMASK_SPI_MOSI_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 6. 0x48 6. 0x28 6. " INTOUTMASK_SPI_MISO_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 5. 0x48 5. 0x28 5. " INTOUTMASK_NAND_NCS_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 4. 0x48 4. 0x28 4. " INTOUTMASK_NAND_NCS_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 3. 0x48 3. 0x28 3. " INTOUTMASK_NAND_NCS_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 2. 0x48 2. 0x28 2. " INTOUTMASK_NAND_NCS_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 1. 0x48 1. 0x28 1. " INTOUTMASK_GPIO18_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x08 0. 0x48 0. 0x28 0. " INTOUTMASK_GPIO17_set/clr ,Interrupt Output Mask" "Masked,Not masked" line.long 0x0c "INTOUTMASK_43,Interrupt Output Mask Register - Bank 3" setclrfld.long 0x0c 29. 0x4c 29. 0x2c 29. " INTOUTMASK_isram1_mrc_finished_set/clr ,ISRAM1 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 28. 0x4c 28. 0x2c 28. " INTOUTMASK_isram0_mrc_finished_set/clr ,ISRAM0 redundancy controller event" "Masked,Not masked" textline " " setclrfld.long 0x0c 27. 0x4c 27. 0x2c 27. " INTOUTMASK_USB_ID_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 26. 0x4c 26. 0x2c 26. " INTOUTMASK_usb_otg_vbus_pwr_en_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 25. 0x4c 25. 0x2c 25. " INTOUTMASK_usb_atx_pll_lock_set/clr ,USB PLL lock event" "Masked,Not masked" textline " " setclrfld.long 0x0c 24. 0x4c 24. 0x2c 24. " INTOUTMASK_usb_otg_ahb_needclk_set/clr ,Input Event From USB" "Masked,Not masked" textline " " setclrfld.long 0x0c 23. 0x4c 23. 0x2c 23. " INTOUTMASK_USB_VBUS_set/clr ,Input Event From USB_VBUS pin" "Masked,Not masked" textline " " setclrfld.long 0x0c 22. 0x4c 22. 0x2c 22. " INTOUTMASK_MCI_CLK_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 21. 0x4c 21. 0x2c 21. " INTOUTMASK_MCI_CMD_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 20. 0x4c 20. 0x2c 20. " INTOUTMASK_MCI_DAT_7_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 19. 0x4c 19. 0x2c 19. " INTOUTMASK_MCI_DAT_6_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 18. 0x4c 18. 0x2c 18. " INTOUTMASK_MCI_DAT_5_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 17. 0x4c 17. 0x2c 17. " INTOUTMASK_MCI_DAT_4_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 16. 0x4c 16. 0x2c 16. " INTOUTMASK_MCI_DAT_3_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 15. 0x4c 15. 0x2c 15. " INTOUTMASK_MCI_DAT_2_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 14. 0x4c 14. 0x2c 14. " INTOUTMASK_MCI_DAT_1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 13. 0x4c 13. 0x2c 13. " INTOUTMASK_MCI_DAT_0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 12. 0x4c 12. 0x2c 12. " INTOUTMASK_arm926_lp_nirq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 11. 0x4c 11. 0x2c 11. " INTOUTMASK_arm926_lp_nfiq_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 10. 0x4c 10. 0x2c 10. " INTOUTMASK_I2c1_scl_n_set/clr , Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 9. 0x4c 9. 0x2c 9. " INTOUTMASK_I2c0_scl_n_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 8. 0x4c 8. 0x2c 8. " INTOUTMASK_uart_rxd_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 7. 0x4c 7. 0x2c 7. " INTOUTMASK_wdog_m0_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 6. 0x4c 6. 0x2c 6. " INTOUTMASK_adc_int_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 5. 0x4c 5. 0x2c 5. " INTOUTMASK_timer3_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 4. 0x4c 4. 0x2c 4. " INTOUTMASK_timer2_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 3. 0x4c 3. 0x2c 3. " INTOUTMASK_timer1_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 2. 0x4c 2. 0x2c 2. " INTOUTMASK_timer0_intct1_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 1. 0x4c 1. 0x2c 1. " INTOUTMASK_GPIO20_set/clr ,Interrupt Output Mask" "Masked,Not masked" textline " " setclrfld.long 0x0c 0. 0x4c 0. 0x2c 0. " INTOUTMASK_GPIO19_set/clr ,Interrupt Output Mask" "Masked,Not masked" tree.end width 0xb tree.end tree "Random Number Generator (RNG)" base ad:0x13006000 width 15. hgroup.long 0x00++0x3 hide.long 0x00 "RANDOM_NUMBER,Random number" in group.long 0xff4++0x3 line.long 0x00 "POWERDOWN,Power-down mode" bitfld.long 0x00 2. " POWER_DOWN ,Blocks access to standard registers" "Not powered down,Powered down" bitfld.long 0x00 1. " FORCE_SOFT_RESET ,Forces RNG reset" "Not forced,Forced" textline " " bitfld.long 0x00 0. " SOFT_RESET ,Software Reset" "No reset,Reset" width 0xb tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x15002000 width 12. if ((d.l(ad:0x15002000)&0xA)==0xA) group.long 0x00++0x3 line.long 0x00 "SPI_CONFIG,Configuration register" hexmask.long.word 0x00 16.--31. 1. " INTER_SLAVE_DLY ,The minimum delay between two transfers to different slaves (value 1 is minimum)" bitfld.long 0x00 7. " UPDATE_ENABLE ,Update enable bit (usage of the value in the SLV_ENABLE)" "Presently,Waiting" textline " " bitfld.long 0x00 6. " SOFTWARE_RESET ,Software reset bit" "No effect,Reset" bitfld.long 0x00 5. " TIMER_TRIGGER ,Timer trigger-block bit" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SLAVE_DISABLE ,Slave-output disable" "No,Yes" bitfld.long 0x00 3. " TRANSMIT_MODE ,Transmit mode" "Normal,Sequential-slave" textline " " bitfld.long 0x00 2. " LOOPBACK_MODE ,Loopback-mode bit" "Normal,Looped-back" bitfld.long 0x00 1. " MS_MODE ,Master/slave mode" "Master,Slave" textline " " bitfld.long 0x00 0. " SPI_ENABLE ,SPI enable bit" "Disabled,Enabled" elif ((d.l(ad:0x15002000)&0xA)==0x8) group.long 0x00++0x3 line.long 0x00 "SPI_CONFIG,Configuration register" hexmask.long.word 0x00 16.--31. 1. " INTER_SLAVE_DLY ,The minimum delay between two transfers to different slaves (value 1 is minimum)" bitfld.long 0x00 7. " UPDATE_ENABLE ,Update enable bit (usage of the value in the SLV_ENABLE)" "Presently,Waiting" textline " " bitfld.long 0x00 6. " SOFTWARE_RESET ,Software reset bit" "No effect,Reset" bitfld.long 0x00 5. " TIMER_TRIGGER ,Timer trigger-block bit" "Disabled,Disabled" textline " " bitfld.long 0x00 3. " TRANSMIT_MODE ,Transmit mode" "Normal,Sequential-slave" textline " " bitfld.long 0x00 2. " LOOPBACK_MODE ,Loopback-mode bit" "Normal,Looped-back" bitfld.long 0x00 1. " MS_MODE ,Master/slave mode" "Master,Slave" textline " " bitfld.long 0x00 0. " SPI_ENABLE ,SPI enable bit" "Disabled,Enabled" elif ((d.l(ad:0x15002000)&0xA)==0x2) group.long 0x00++0x3 line.long 0x00 "SPI_CONFIG,Configuration register" hexmask.long.word 0x00 16.--31. 1. " INTER_SLAVE_DLY ,The minimum delay between two transfers to different slaves (value 1 is minimum)" bitfld.long 0x00 7. " UPDATE_ENABLE ,Update enable bit (usage of the value in the SLV_ENABLE)" "Presently,Waiting" textline " " bitfld.long 0x00 6. " SOFTWARE_RESET ,Software reset bit" "No effect,Reset" textline " " bitfld.long 0x00 4. " SLAVE_DISABLE ,Slave-output disable" "No,Yes" bitfld.long 0x00 3. " TRANSMIT_MODE ,Transmit mode" "Normal,Sequential-slave" textline " " bitfld.long 0x00 2. " LOOPBACK_MODE ,Loopback-mode bit" "Normal,Looped-back" bitfld.long 0x00 1. " MS_MODE ,Master/slave mode" "Master,Slave" textline " " bitfld.long 0x00 0. " SPI_ENABLE ,SPI enable bit" "Disabled,Enabled" else group.long 0x00++0x3 line.long 0x00 "SPI_CONFIG,Configuration register" hexmask.long.word 0x00 16.--31. 1. " INTER_SLAVE_DLY ,The minimum delay between two transfers to different slaves (value 1 is minimum)" bitfld.long 0x00 7. " UPDATE_ENABLE ,Update enable bit (usage of the value in the SLV_ENABLE)" "Presently,Waiting" textline " " bitfld.long 0x00 6. " SOFTWARE_RESET ,Software reset bit" "No effect,Reset" textline " " bitfld.long 0x00 3. " TRANSMIT_MODE ,Transmit mode" "Normal,Sequential-slave" textline " " bitfld.long 0x00 2. " LOOPBACK_MODE ,Loopback-mode bit" "Normal,Looped-back" bitfld.long 0x00 1. " MS_MODE ,Master/slave mode" "Master,Slave" textline " " bitfld.long 0x00 0. " SPI_ENABLE ,SPI enable bit" "Disabled,Enabled" endif group.long 0x04++0x3 line.long 0x00 "SLV_ENABLE,Slave-enable register" bitfld.long 0x00 6.--7. " SLV_ENABLE_3 ,Slave enable slave 3" "Disabled,Enabled,Reserved,Suspended" bitfld.long 0x00 4.--5. " SLV_ENABLE_2 ,Slave enable slave 2" "Disabled,Enabled,Reserved,Suspended" textline " " bitfld.long 0x00 2.--3. " SLV_ENABLE_1 ,Slave enable slave 1" "Disabled,Enabled,Reserved,Suspended" bitfld.long 0x00 0.--1. " SLV_ENABLE_0 ,Slave enable slave 0" "Disabled,Enabled,Reserved,Suspended" width 18. wgroup.long 0x08++0x3 line.long 0x00 "TX_FIFO_FLUSH,Tx FIFO flush register" bitfld.long 0x00 0. " TX_FIFO_FLUSH ,Flush transmit FIFO" "No effect,Flush" hgroup.long 0x0C++0x3 hide.long 0x00 "FIFO_DATA,FIFO data register" in wgroup.long 0x10++0x3 line.long 0x00 "RX_FIFO_POP,Rx FIFO pop register" bitfld.long 0x00 0. " RX_FIFO_POP ,Pops the first element from the receive FIFO" "Not pop,Pop" group.long 0x14++0x7 line.long 0x00 "RX_FIFO_READMODE,Rx FIFO read-mode selection register" bitfld.long 0x00 0. " RX_FIFO_PROTECT ,Receive-FIFO protect-mode" "Disabled,Enabled" line.long 0x04 "DMA_SETTINGS,DMA settings and enable register" bitfld.long 0x04 5.--7. " TX_DMA_BURST ,Number of free spaces when Tx DMA burst will be requested" "1,4,8,16,32,64,128,256" bitfld.long 0x04 2.--4. " RX_DMA_BURST ,Number of free spaces when Rx DMA burst will be requested" "1,4,8,16,32,64,128,256" textline " " bitfld.long 0x04 1. " TX_DMA_ENABLE ,Tx DMA enable" "Disabled,Enabled" bitfld.long 0x04 0. " RX_DMA-ENABLE ,Rx DMA enable" "Disabled,Enabled" rgroup.long 0x1C++0x3 line.long 0x00 "STATUS,Status register" bitfld.long 0x00 5. " SMS_MODE_BUSY ,Sequential-slave mode busy" "Not busy,Busy" bitfld.long 0x00 4. " SPI_BUSY ,SPI busy" "Idle,Busy" textline " " bitfld.long 0x00 3. " RX_FIFO_FULL ,Receive FIFO full" "Not full,Full" bitfld.long 0x00 2. " RX_FIFO_EMPTY ,Receive FIFO empty" "Not empty,Empty" textline " " bitfld.long 0x00 1. " TX_FIFO_FULL ,Transmit FIFO full" "Not full,Full" bitfld.long 0x00 0. " TX_FIFO_EMPTY ,Transmit FIFO empty" "Not empty,Empty" if ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x24+0x04))&0x80)==0x80) group.long 0x24++0x3 line.long 0x00 "SLV0_SETTINGS1,Slave-settings register 1 for slave 0" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x24+0x04)++0x3 line.long 0x00 "SLV0_SETTINGS2,Slave-settings register 2 for slave 0" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x24+0x04))&0x80)==0x0) group.long 0x24++0x3 line.long 0x00 "SLV0_SETTINGS1,Slave-settings register 1 for slave 0" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x24+0x04)++0x3 line.long 0x00 "SLV0_SETTINGS2,Slave-settings register 2 for slave 0" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x2)&&((d.l(ad:(0x15002000+0x24+0x04))&0x80)==0x80) group.long (0x24+0x04)++0x3 line.long 0x00 "SLV0_SETTINGS2,Slave-settings register 2 for slave 0" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." else group.long (0x24+0x04)++0x3 line.long 0x00 "SLV0_SETTINGS2,Slave-settings register 2 for slave 0" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." endif if ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x2C+0x04))&0x80)==0x80) group.long 0x2C++0x3 line.long 0x00 "SLV1_SETTINGS1,Slave-settings register 1 for slave 1" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x2C+0x04)++0x3 line.long 0x00 "SLV1_SETTINGS2,Slave-settings register 2 for slave 1" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x2C+0x04))&0x80)==0x0) group.long 0x2C++0x3 line.long 0x00 "SLV1_SETTINGS1,Slave-settings register 1 for slave 1" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x2C+0x04)++0x3 line.long 0x00 "SLV1_SETTINGS2,Slave-settings register 2 for slave 1" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x2)&&((d.l(ad:(0x15002000+0x2C+0x04))&0x80)==0x80) group.long (0x2C+0x04)++0x3 line.long 0x00 "SLV1_SETTINGS2,Slave-settings register 2 for slave 1" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." else group.long (0x2C+0x04)++0x3 line.long 0x00 "SLV1_SETTINGS2,Slave-settings register 2 for slave 1" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." endif if ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x34+0x04))&0x80)==0x80) group.long 0x34++0x3 line.long 0x00 "SLV2_SETTINGS1,Slave-settings register 1 for slave 2" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x34+0x04)++0x3 line.long 0x00 "SLV2_SETTINGS2,Slave-settings register 2 for slave 2" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x34+0x04))&0x80)==0x0) group.long 0x34++0x3 line.long 0x00 "SLV2_SETTINGS1,Slave-settings register 1 for slave 2" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x34+0x04)++0x3 line.long 0x00 "SLV2_SETTINGS2,Slave-settings register 2 for slave 2" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x2)&&((d.l(ad:(0x15002000+0x34+0x04))&0x80)==0x80) group.long (0x34+0x04)++0x3 line.long 0x00 "SLV2_SETTINGS2,Slave-settings register 2 for slave 2" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." else group.long (0x34+0x04)++0x3 line.long 0x00 "SLV2_SETTINGS2,Slave-settings register 2 for slave 2" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." endif if ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x3C+0x04))&0x80)==0x80) group.long 0x3C++0x3 line.long 0x00 "SLV3_SETTINGS1,Slave-settings register 1 for slave 3" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x3C+0x04)++0x3 line.long 0x00 "SLV3_SETTINGS2,Slave-settings register 2 for slave 3" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x0)&&((d.l(ad:(0x15002000+0x3C+0x04))&0x80)==0x0) group.long 0x3C++0x3 line.long 0x00 "SLV3_SETTINGS1,Slave-settings register 1 for slave 3" hexmask.long.byte 0x00 24.--31. 1. " INTER_TRANSFER_DLY ,The delay between transfers to this slave" hexmask.long.byte 0x00 16.--23. 1. " NUMBER_WORDS ,Number of words to send in sequential slave mode (minus 1 encoded)" textline " " hexmask.long.byte 0x00 8.--15. 1. " CLK_DIVISOR2 ,Serial clock-rate divisor 2 (2-254)" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVISOR1 ,Serial clock-rate divisor 1 (0-255)" group.long (0x3C+0x04)++0x3 line.long 0x00 "SLV3_SETTINGS2,Slave-settings register 2 for slave 3" hexmask.long.byte 0x00 9.--16. 1. " PRE_POST_CS_DLY ,Programmable delay that occurs twice in a transfer" bitfld.long 0x00 8. " CS_VALUE ,Chip-select value between back-to-back transfers selection" "Low,High" textline " " bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." elif ((d.l(ad:0x15002000)&0x2)==0x2)&&((d.l(ad:(0x15002000+0x3C+0x04))&0x80)==0x80) group.long (0x3C+0x04)++0x3 line.long 0x00 "SLV3_SETTINGS2,Slave-settings register 2 for slave 3" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,4 bits,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." else group.long (0x3C+0x04)++0x3 line.long 0x00 "SLV3_SETTINGS2,Slave-settings register 2 for slave 3" bitfld.long 0x00 7. " TRANSFER_FORMAT ,Format of transfer" "Motorola SPI,Texas Sync serial" bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Low,High" textline " " bitfld.long 0x00 5. " SPH ,Serial clock phase" "First edge,Second edge" bitfld.long 0x00 0.--4. " WORDSIZE ,Word size of transfers to this slave" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8 bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16 bits,?..." endif group.long 0xFD4++0x3 line.long 0x00 "INT_THRESHOLD,Tx/Rx FIFO threshold interrupt levels" hexmask.long.byte 0x00 8.--15. 1. " TX_THRESHOLD ,When number of Tx FIFO elements is less then this value interrupt is requested" hexmask.long.byte 0x00 0.--7. 1. " RX_THRESHOLD ,When number of Rx FIFO elements is greater then this value interrupt is requested" group.long 0xFE0++0x7 line.long 0x00 "INT_STATUS,Interrupt status register" setclrfld.long 0x00 4. 0x0C 4. 0x08 4. " SMS_set/clr ,Sequential-slave mode ready" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x0C 3. 0x08 3. " TX_set/clr ,Transmit threshold level" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x0C 2. 0x08 2. " RX_set/clr ,Receive threshold level" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x0C 1. 0x08 1. " TO_set/clr ,Receive time-out" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x0C 0. 0x08 0. " OV_set/clr ,Receive overrun" "No interrupt,Interrupt" line.long 0x04 "INT_ENABLE,Interrupt enable register" setclrfld.long 0x04 4. -0x04 4. -0x08 4. " SMS_set/clr ,Sequential-slave mode ready" "Disabled,Enabled" setclrfld.long 0x04 3. -0x04 3. -0x08 3. " TX_set/clr ,Transmit threshold level" "Disabled,Enabled" textline " " setclrfld.long 0x04 2. -0x04 2. -0x08 2. " RX_set/clr ,Receive threshold level" "Disabled,Enabled" setclrfld.long 0x04 1. -0x04 1. -0x08 1. " TO_set/clr ,Receive time-out" "Disabled,Enabled" textline " " setclrfld.long 0x04 0. -0x04 0. -0x08 0. " OV_set/clr ,Receive overrun" "Disabled,Enabled" width 0xb tree.end tree "MCI (Memory Card Interface)" base ad:0x18000000 width 9. group.long 0x00++0x3 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 11. " CEATA_DEVICE_INTERRUPT_STATUS ,Interrupts in CE-ATA Device Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEND_AUTO_STOP_CCSD ,Sends internally generated STOP command" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " SEND_CCSD ,Sends Command Completion Signal Disable" "No,Yes" bitfld.long 0x00 8. " ABORT_READ_DATA ,Resets data state-machine" "No effect,Reset" textline " " bitfld.long 0x00 7. " SEND_IRQ_RESPONSE ,Sends CMD40 response" "No effect,Send" bitfld.long 0x00 6. " READ_WAIT ,Sends read-wait to SDIO cards" "Cleared,Asserted" textline " " bitfld.long 0x00 5. " DMA_ENABLE ,DMA Enable" "Disabled,Enable" bitfld.long 0x00 4. " INT_ENABLE ,Global interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DMA_RESET ,DMA interface Reset" "No effect,Reset" bitfld.long 0x00 1. " FIFO_RESET ,FIFO Reset" "No effect,Reset" textline " " bitfld.long 0x00 0. " CONTROLLER_RESET ,Conrtoller Reset" "No effect,Reset" group.long 0x08++0x27 line.long 0x00 "CLKDIV,Clock-divider Register" hexmask.long.byte 0x00 0.--7. 1. " CLK_DIVIDER ,Clock divider-0 value" line.long 0x04 "CLKSRC,Clock-source Register" bitfld.long 0x04 0.--1. " CLK_SOURCE ,Clk source" "0,?..." line.long 0x08 "CLKENA,Clock-enable Register" bitfld.long 0x08 16. " CCLK_LOW_POWER ,Low-power control for the output card clock" "Disabled,Enabled" bitfld.long 0x08 0. " CCLK_ENABLE ,Clock-enable control for the output card clock" "Disabled,Enabled" line.long 0x0c "TMOUT,Time-out Register" hexmask.long.tbyte 0x0C 8.--31. 1. " Data_timeout ,Card Data Read Timeout" hexmask.long.byte 0x0C 0.--7. 1. " Response_timeout ,Response timeout value" line.long 0x10 "CTYPE,Card-type Register" bitfld.long 0x10 16. " CARD_WIDTH ,This bit indicates if the card is 8-bit" "Non 8-bit,8-bit" bitfld.long 0x10 0. " CARD_WIDTH ,This bit indicates if the card is 1-bit or 4-bi" "1-bit,4-bit" line.long 0x14 "BLKSIZ,Block-size Register" hexmask.long.word 0x14 0.--15. 1. " Block_size ,Block size" line.long 0x18 "BYTCNT,Byte-count Register" line.long 0x1c "INTMASK,Interrupt-mask Register" bitfld.long 0x1c 16. " SDIO ,Mask SDIO interrupt" "Disabled,Enabled" bitfld.long 0x1c 15. " EBE ,End-bit error" "Disabled,Enabled" bitfld.long 0x1c 14. " ACD ,Auto command done" "Disabled,Enabled" textline " " bitfld.long 0x1c 13. " SBE ,Start-bit error" "Disabled,Enabled" bitfld.long 0x1c 12. " HLE ,Hardware locked write error" "Disabled,Enabled" bitfld.long 0x1c 11. " FRUN ,FIFO underrun/overrun error" "Disabled,Enabled" textline " " bitfld.long 0x1c 10. " HTO ,Data starvation-by-cpu timeout" "Disabled,Enabled" bitfld.long 0x1c 9. " DRTO ,Data read timeout" "Disabled,Enabled" bitfld.long 0x1c 8. " RTO ,Response timeout" "Disabled,Enabled" textline " " bitfld.long 0x1c 7. " DCRC ,Data CRC error" "Disabled,Enabled" bitfld.long 0x1c 6. " RCRC ,Response CRC error" "Disabled,Enabled" bitfld.long 0x1c 5. " RXDR ,Receive FIFO data request" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " TXDR ,Transmit FIFO data request" "Disabled,Enabled" bitfld.long 0x1c 3. " DTO ,Data transfer over" "Disabled,Enabled" bitfld.long 0x1c 2. " CD ,Command done" "Disabled,Enabled" textline " " bitfld.long 0x1c 1. " RE ,Response error" "Disabled,Enabled" bitfld.long 0x1c 0. " CD ,Card detect" "Disabled,Enabled" line.long 0x20 "CMDARG,Command-argument Register" line.long 0x24 "CMD,Command Register" bitfld.long 0x24 31. " START_CMD ,Start command" "Not started,Started" bitfld.long 0x24 23. " CCS_EXPECTED ,RW_BLK command expects command completion signal from CE-ATA device" "Disabled,Enabled" textline " " bitfld.long 0x24 22. " READ_CEATA_DEVICE ,Cpu read access" "Idle,In progress" bitfld.long 0x24 21. " UPDATE_CLOCK_REGISTERS_ONLY ,Command sequence" "Normal,Update only" textline " " bitfld.long 0x24 15. " SEND_INITIALIZATION ,Sends initialization sequence" "Not sent,Sent" bitfld.long 0x24 14. " STOP_ABORT_CMD ,Stop or abort command used to stop current data transfer in progress" "Disabled,Enabled" textline " " bitfld.long 0x24 13. " WAIT_PRVDATA_COMPLETE ,Wait for previous data transfer completion before sending command" "No wait,Wait" bitfld.long 0x24 12. " SEND_AUTO_STOP ,Stop command sent at end of data transfer" "Disabled,Enabled" textline " " bitfld.long 0x24 11. " TRANSFER_MODE ,Transfer mode" "Block,Stream" bitfld.long 0x24 10. " READ_WRITE ,Read from card or write to card" "Read,Write" textline " " bitfld.long 0x24 9. " DATA_TRANSFER_EXPECTED ,Data transfer expected" "Not expected,Expected" bitfld.long 0x24 8. " CHECK_RESPONSE_CRC ,Command responses CRC check" "Disabled,Enabled" textline " " bitfld.long 0x24 7. " RESPONSE_LENGTH ,Response length" "Short,Long" bitfld.long 0x24 6. " RESPONSE_EXPECT ,Response expect" "Not expected,Expected" textline " " bitfld.long 0x24 0.--5. " CMD_INDEX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x30++0xf line.long 0x00 "RESP0,Response-0 Register" line.long 0x04 "RESP1,Response-1 Register" line.long 0x08 "RESP2,Response-2 Register" line.long 0x0c "RESP3,Response-3 Register" group.long 0x40++03 line.long 0x00 "MINTSTS,Masked interrupt-status Register" bitfld.long 0x00 16. " sdio_interrupt ,Interrupt from SDIO card" "No interrupt,Interrupt" bitfld.long 0x00 15. " EBE ,End-bit error" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " ACD ,Auto command done" "No interrupt,Interrupt" bitfld.long 0x00 13. " SBE ,Start-bit error" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " HLE ,Hardware locked write error" "No interrupt,Interrupt" bitfld.long 0x00 11. " FRUN ,FIFO underrun/overrun error" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " HTO ,Data starvation-by-cpu timeout" "No interrupt,Interrupt" bitfld.long 0x00 9. " DRTO ,Data read timeout" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " RTO ,Response timeout" "No interrupt,Interrupt" bitfld.long 0x00 7. " DCRC ,Data CRC error" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " RCRC ,Response CRC error" "No interrupt,Interrupt" bitfld.long 0x00 5. " RXDR ,Receive FIFO data request" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " TXDR ,Transmit FIFO data request" "No interrupt,Interrupt" bitfld.long 0x00 3. " DTO ,Data transfer over" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " CD ,Command done" "No interrupt,Interrupt" bitfld.long 0x00 1. " RE ,Response error" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " CD ,Card detect" "No interrupt,Interrupt" group.long 0x44++0x3 line.long 0x00 "RINTSTS,Raw interrupt-status Register" eventfld.long 0x00 16. " sdio_interrupt ,Interrupt from SDIO card" "No interrupt,Interrupt" eventfld.long 0x00 15. " EBE ,End-bit error" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " ACD ,Auto command done" "No interrupt,Interrupt" eventfld.long 0x00 13. " SBE ,Start-bit error" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " HLE ,Hardware locked write error" "No interrupt,Interrupt" eventfld.long 0x00 11. " FRUN ,FIFO underrun/overrun error" "No interrupt,Interrupt" textline " " eventfld.long 0x00 10. " HTO ,Data starvation-by-cpu timeout" "No interrupt,Interrupt" eventfld.long 0x00 9. " DRTO ,Data read timeout" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " RTO ,Response timeout" "No interrupt,Interrupt" eventfld.long 0x00 7. " DCRC ,Data CRC error" "No interrupt,Interrupt" textline " " eventfld.long 0x00 6. " RCRC ,Response CRC error" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXDR ,Receive FIFO data request" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " TXDR ,Transmit FIFO data request" "No interrupt,Interrupt" eventfld.long 0x00 3. " DTO ,Data transfer over" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " CD ,Command done" "No interrupt,Interrupt" eventfld.long 0x00 1. " RE ,Response error" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " CD ,Card detect" "No interrupt,Interrupt" rgroup.long 0x48++0x3 line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 31. " DMA_REQ ,DMA request signal state" "Not requested,Requested" bitfld.long 0x00 30. " DMA_ACK ,DMA acknowledge signal state" "Not acknowledged,Acknowledged" textline " " hexmask.long.word 0x00 17.--29. 1. " FIFO_COUNT ,Number of filled locations in FIFO" bitfld.long 0x00 11.--16. " RESPONSE_INDEX ,Index of previous response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 10. " DATA_STATE_MC_BUSY ,Data transmit or receive state-machine is busy" "Idle,Busy" bitfld.long 0x00 9. " DATA_BUSY ,Inverted version of MCI_DATA_0 pin" "Idle,Busy" textline " " bitfld.long 0x00 8. " DATA_3_STATUS ,Raw state of MCI_DATA_3 pin" "Not present,Present" bitfld.long 0x00 4.--7. " COMMAND_FSM_STATES ,Command FSM states" "Idle,Send init sequence,Tx cmd start bit,Tx cmd tx bit,Tx cmd index + arg,Tx cmd crc7,Tx cmd end bit,Rx resp start bit,Rx resp IRQ response,Rx resp tx bit,Rx resp cmd idx,Rx resp data,Rx resp crc7,Rx resp end bit,Cmd path wait NCC,Wait; CMD-to-response" textline " " bitfld.long 0x00 3. " FIFO_FULL ,FIFO is full status" "Not full,Full" bitfld.long 0x00 2. " FIFO_EMPTY ,FIFO is empty status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " FIFO_TX_WATERMARK ,FIFO reached Transmit" "Not reached,Reached" bitfld.long 0x00 0. " FIFO_RX_WATERMARK ,FIFO reached Receive" "Not reached,Reached" group.long 0x4c++0x3 line.long 0x00 "FIFOTH,FIFO Threshold Register" bitfld.long 0x00 28.--30. " DMA_MULTIPLE_TRANSACTION_SIZE ,Burst size of multiple transaction" "1 transfer,4 transfers,8 transfers,16 transfers,32 transfers,64 transfers,128 transfers,256 transfers" textline " " hexmask.long.word 0x00 16.--27. 1. " RX_WMARK ,FIFO threshold watermark level when receiving data to card" hexmask.long.word 0x00 0.--11. 1. " TX_WMARK ,FIFO threshold watermark level when transmitting data to card" group.long 0x50++0x7 line.long 0x00 "CDETECT,Card-detect Register" bitfld.long 0x00 0. " CARD_DETECT_N ,Presence of card" "Present,Not present" line.long 0x04 "WRTPRT,Write-protect Register" bitfld.long 0x04 0. " WRITE_PROTECT ,Write protection" "Not protected,Protected" rgroup.long 0x5c++7 line.long 0x00 "TCBCNT,Transferred CIU Card Byte Count" line.long 0x04 "TBBCNT,Transferred cpu/DMA to/from BIU-FIFO Byte Count" width 0xb tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x15001000 width 8. if (((d.l(ad:(0x15001000+0x0C)))&0x80)==0x0) hgroup.long 0x00++0x03 hide.long 0x00 "RBR/THR,Receiver Buffer Register/Transmit Holding Register" in group.long 0x04++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 9. " ABTOIntEn ,Auto-Baud Timeout interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " ABEOIntEn ,Auto-Baud End Operation interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CTSIntEn ,Interrupts on transitions of the CTS pin" "Disabled,Enabled" bitfld.long 0x00 3. " MSIntEn ,Interrupt transitions on transitions of the CTS pin" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RLSIntEn ,RX line status interrupts" "Disabled,Enabled" bitfld.long 0x00 1. " THREIntEn ,THRE interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RDAIntEn ,Receive Data Available interrupt" "Disabled,Enabled" else group.long 0x00++0x07 line.long 0x00 "DLL,Divisor Latch LSB Register" hexmask.long.byte 0x00 0.--7. 1. " DLL ,Divisor Latch LSB" line.long 0x04 "DLM,Divisor Latch MSB Register" hexmask.long.byte 0x04 0.--7. 1. " DLM ,Divisor Latch MSB" endif rgroup.long 0x08++0x03 line.long 0x00 "IIR,Interrupt Identification Register" bitfld.long 0x00 9. " ABTOInt ,Auto-baud time-out interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " ABEOInt ,End of auto-baud interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " FIFOEn ,FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 6. " FIFOEn ,FIFO Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--3. " IntId ,Interrupt Identification" "Modem status,THR register empty,Rx Data Available,Receiver line status,?..." bitfld.long 0x00 0. " IntStatus ,Interrupt Status" "Interrupt,No interrupt" wgroup.long 0x08++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 6.--7. " RxTrigLevel ,Receiver trigger level selection" "1 character,16 characters,32 characters ,56 characters" textline " " bitfld.long 0x00 3. " DMAMode ,DMA mode select" "Mode 0,Mode 1" textline " " bitfld.long 0x00 2. " TxFIFORst ,Transmitter FIFO reset" "No reset,Reset" textline " " bitfld.long 0x00 1. " RxFIFORst ,Receiver FIFO reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " FIFOEnable ,Transmit and receive FIFO enable" "Disabled,Enabled" if (((d.l(ad:(0x15001000+0x0C)))&0x3)==0x0) group.long 0x0C++0x07 line.long 0x00 "LCR,Line Control Register" bitfld.long 0x00 7. " DLAB ,Divisor Latch Access enable" "Disabled,Enabled" bitfld.long 0x00 6. " BrkCnt ,Break Transmission Control" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ParStick ,Stick parity mode" "Disabled,Enabled" bitfld.long 0x00 4. " ParEven ,Parity Even Select" "Even,Odd" textline " " bitfld.long 0x00 3. " ParEn ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " StopBitNum ,Number of stop bits select" "1 bit,1.5 bits" bitfld.long 0x00 0.--1. " WdLenSel ,Word Length Select" "5 bit,6 bit,7 bit,8 bit" else group.long 0x0C++0x07 line.long 0x00 "LCR,Line Control Register" bitfld.long 0x00 7. " DLAB ,Divisor Latch Access enable" "Disabled,Enabled" bitfld.long 0x00 6. " BrkCnt ,Break Transmission Control" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ParStick ,Stick parity mode" "Disabled,Enabled" bitfld.long 0x00 4. " ParEven ,Parity Even Select" "Even,Odd" textline " " bitfld.long 0x00 3. " ParEn ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 2. " StopBitNum ,Number of stop bits select" "1 bit,2 bits" textline " " bitfld.long 0x00 0.--1. " WdLenSel ,Word Length Select" "5 bit,6 bit,7 bit,8 bit" endif group.long 0x10++0x03 line.long 0x0 "MCR,Modem Control Register" bitfld.long 0x0 7. " AutoCTSEn ,Automatic CTS flow control" "Disabled,Enabled" bitfld.long 0x0 6. " AutoRTSEn ,Automatic RTS flow control" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " LoopEn ,Loopback Testing Mode" "Disabled,Enabled" bitfld.long 0x0 3. " OUT2 ,Inverse control for the out2_n output" "High,Low" textline " " bitfld.long 0x0 3. " OUT1 ,Inverse control for the out1_n output" "High,Low" bitfld.long 0x0 1. " RTS ,Request To Send" "High,Low" textline " " bitfld.long 0x0 0. " DTR ,Inverse control for the Data Terminal Ready output" "High,Low" hgroup.long 0x14++0x03 hide.long 0x00 "LSR,Line Status Register" in hgroup.long 0x18++0x03 hide.long 0x00 "MSR,Modem Status Register" in group.long 0x1C++0x03 line.long 0x00 "SCR,Scratch Pad Register" hexmask.long 0x00 0.--7. 1. " SCRVal ,Scratch Value" wgroup.long 0x20++0x3 line.long 0x00 "ACR,Auto-baud Control Register" bitfld.long 0x00 9. " ABTOIntClr ,Auto-baud time-out interrupt clear" "No effect,Cleared" bitfld.long 0x00 8. " ABEOIntClr ,End of auto-baud interrupt clear" "No effect,Cleared" if (((d.l(ad:(0x15001000+0x24)))&0x4)==0x4) group.long 0x24++0x3 line.long 0x0 "ICR,IrDA Control Register" bitfld.long 0x00 2. " FixPulseEn ,IrDA fixed-pulse-width mode" "Disabled,Enabled" bitfld.long 0x00 3.--5. " PulseDiv ,IrDA transmitter pulse width [us]" "2 * Tpclk,4 * Tpclk,8 * Tpclk,16 * Tpclk,32 * Tpclk,64 * Tpclk,128 * Tpclk,256 * Tpclk" textline " " bitfld.long 0x00 1. " IrDAInv ,IrDA Serial Input Invert" "Not inverted,Inverted" bitfld.long 0x00 0. " IrDAEn ,IrDA Enable" "Disabled,Enabled" else group.long 0x24++0x3 line.long 0x0 "ICR,IrDA Control Register" bitfld.long 0x00 2. " FixPulseEn ,IrDA fixed-pulse-width mode" "Disabled,Enabled" bitfld.long 0x00 1. " IrDAInv ,IrDA Serial Input Invert" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " IrDAEn ,IrDA Enable" "Disabled,Enabled" endif group.long 0x28++0x3 line.long 0x0 "FDR,Fractional Divider Register" hexmask.long.byte 0x0 4.--7. 1. " MulVal ,Baud rate pre-scaler multiplier value" hexmask.long.byte 0x0 0.--3. 1. " DivAddVal ,Baud rate generation pre-scaler divisor value" wgroup.long 0x30++0x3 line.long 0x00 "POP,NHP POP Register" bitfld.long 0x00 0. " PopRBR ,pop the first item from the Receiver Buffer Register's FIFO" "No effect,Pop" group.long 0x34++0x03 line.long 0x00 "MODE,NHP Mode Register" bitfld.long 0x00 0. " NHP ,Nexperia Home Platform Mode" "x50,NHP" rgroup.long 0xFD4++0x3 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 12. " HasIrDA ,IrDA module" "Not included,Included" bitfld.long 0x00 9. " HasLevel ,FIFO level interface" "Not included,Included" textline " " bitfld.long 0x00 8. " HasDMA ,ARM DMA interface" "Not included,Included" bitfld.long 0x00 4.--5. " Modem ,Modem interface" "Not included,cts and rts included,All signals included,?..." textline " " bitfld.long 0x00 0.--1. " Type ,UART Type" "450,550,650,750" group.long 0xFE0++0x03 line.long 0x00 "INTS,Interrupt Status Register" setclrfld.long 0x00 15. 0x0C 15. 0x08 15. " OEInt_set/clr ,Overrun Error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 14. " PEInt ,Parity Error Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " FEInt ,Frame Error Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BIInt ,Break Indication Interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x0C 9. 0x08 9. " ABTOInt_set/clr ,Auto-Baud Time-Out Interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x0C 8. 0x08 8. " ABEOInt_set/clr ,End of Auto-Baud Interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " RxDAInt ,Receiver Data Available Interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " RxTOInt_set/clr ,Rx Time Out interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x0C 4. 0x08 4. " THREInt_set/clr ,Transmit Holding Register Empty interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x0C 3. 0x08 3. " DDCDInt_set/clr ,Delta Data Carrier Detect Interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x0C 2. 0x08 2. " TERIInt_set/clr ,Trailing Edge Ring Indicator Interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x0C 1. 0x08 1. " DDSRInt_set/clr ,Delta Data Set Ready Interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x0C 0. 0x08 0. " DCTSInt_set/clr ,CTS pin state change interrupt" "No interrupt,Interrupt" group.long 0xFE4++0x03 line.long 0x00 "INTE,Interrupt Enable Register" setclrfld.long 0x00 15. -0x08 15. -0x0c 15. " OEIntEn_set/clr ,Overrun Error Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x0c 14. " PEIntEn_set/clr ,Parity Error Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x0c 13. " FEIntEn_set/clr ,Frame Error Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x0c 12. " BIIntEn_set/clr ,Break Indication Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x0c 9. " ABTOIntEn_set/clr ,Auto-Baud Time-Out Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x0c 8. " ABEOIntEn_set/clr ,End of Auto-Baud Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. -0x08 6. -0x0c 6. " RxDAIntEn_set/clr , Receiver Data Available Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 5. -0x08 5. -0x0c 5. " RxTOIntEn_set/clr , Receiver Time-Out Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. -0x08 4. -0x0c 4. " THREIntEn_set/clr ,Transmitter Holding Register Empty Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 3. -0x08 3. -0x0c 3. " DDCDIntEn_set/clr ,Delta Data Carrier Detect Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. -0x08 2. -0x0c 2. " TERIIntEn_set/clr ,Trailing Edge Ring Indicator Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 1. -0x08 1. -0x0c 1. " DDSRIntEn_set/clr ,Delta Data Set Ready Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. -0x08 0. -0x0c 0. " DCTSIE_set/clr ,Delta Clear To Send Interrupt Enable" "Disabled,Enabled" width 0x0B tree.end tree "LCD (Liquid Crystal Display)" base ad:0x15000400 width 15. rgroup.long 0x00++0x3 line.long 0x00 "LCD_STATUS,tatus register" bitfld.long 0x00 5.--9. " LCD_COUNTER ,Current value of the FIFO counter" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " LCD_INTERFACE_BUSY ,LCD interface is reading the value from the controller" "Idle,Busy" textline " " bitfld.long 0x00 3. " LCD_INT_READ_VALID ,Value read from the LCD controller is valid and not masked in the LCD_INT_MASK register" "Invalid,Valid" bitfld.long 0x00 2. " LCD_INT_FIFO_OVERRUN ,Value written is larger that the FIFO can hold and not masked in the LCD_INT_MASK register" "No overflow,Overflow" textline " " bitfld.long 0x00 1. " LCD_INT_FIFO_HALF_EMPTY ,FIFO is less then half full and not masked in the LCD_INT_MASK register" "Not half empty,Half empty" bitfld.long 0x00 0. " LCD_INT_FIFO_EMPTY ,FIFO is empty and not masked in the LCD_INT_MASK register" "Not empty,Empty" if ((d.l(ad:(0x15000400+0x4))&0x6)==0x6) group.long 0x04++0x3 line.long 0x00 "LCD_CONTROL,Control register" bitfld.long 0x00 20. " BYASYNC_RELCLK ,Bypass the logic which assumes asynchronous relation between PCLK & LCDCLK" "Not bypassed,Bybass" bitfld.long 0x00 19. " IF_16 ,Interface to 16 bit LCD-Controller" "Non 16-bit,16-bit" textline " " bitfld.long 0x00 18. " LOOPBACK ,Operation mode" "Normal,Loopback" bitfld.long 0x00 17. " MSB_FIRST ,Transmission mode" "bit 0 first,bit 7 first" textline " " bitfld.long 0x00 16. " INVERT_E_RD ,E_RD output pin" "Active high,Active low" bitfld.long 0x00 15. " INVERT_CS ,Chip select output" "Active high,Active low" textline " " bitfld.long 0x00 14. " BUSY_RS_VALUE ,busy check condition" "0,1" bitfld.long 0x00 10.--13. " BUSY_BIT_NR ,4 bit value of the 6800/8080 bus which represents the busy flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 9. " BUSY_VALUE ,LCD controller busy" "Idle,Busy" bitfld.long 0x00 8. " BUSY_FLAG_CHECK ,Busy-flag checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " SERIAL_READ_POS ,Sampling timing" "beginning of the cycle,0.25 * cycle,0.5 * cycle,0.75 * cycle" bitfld.long 0x00 4.--5. " SERIAL_CLK_SHIFT ,Clock mode" "0,1,2,3" textline " " bitfld.long 0x00 3. " IF ,LCD interface (4-bit/8-bit) mode" "8-bit,4-bit" bitfld.long 0x00 2. " MI ,LCD interface (Motorola 6800/Intel 8080) mode" "8080,6800" textline " " bitfld.long 0x00 1. " PS ,LCD interface (Parallel/Serial) mode" "Parallel,Serial" elif ((d.l(ad:(0x15000400+0x4))&0x4)==0x4) group.long 0x04++0x3 line.long 0x00 "LCD_CONTROL,Control register" bitfld.long 0x00 20. " BYASYNC_RELCLK ,Bypass the logic which assumes asynchronous relation between PCLK & LCDCLK" "Not bypassed,Bybass" bitfld.long 0x00 19. " IF_16 ,Interface to 16 bit LCD-Controller" "Non 16-bit,16-bit" textline " " bitfld.long 0x00 18. " LOOPBACK ,Operation mode" "Normal,Loopback" bitfld.long 0x00 17. " MSB_FIRST ,Transmission mode" "bits 3-0 first,bits 7-4 first" textline " " bitfld.long 0x00 16. " INVERT_E_RD ,E_RD output pin" "Active high,Active low" bitfld.long 0x00 15. " INVERT_CS ,Chip select output" "Active high,Active low" textline " " bitfld.long 0x00 14. " BUSY_RS_VALUE ,busy check condition" "0,1" bitfld.long 0x00 10.--13. " BUSY_BIT_NR ,4 bit value of the 6800/8080 bus which represents the busy flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 9. " BUSY_VALUE ,LCD controller busy" "Idle,Busy" bitfld.long 0x00 8. " BUSY_FLAG_CHECK ,Busy-flag checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " SERIAL_READ_POS ,Sampling timing" "beginning of the cycle,0.25 * cycle,0.5 * cycle,0.75 * cycle" bitfld.long 0x00 4.--5. " SERIAL_CLK_SHIFT ,Clock mode" "0,1,2,3" textline " " bitfld.long 0x00 3. " IF ,LCD interface (4-bit/8-bit) mode" "8-bit,4-bit" bitfld.long 0x00 2. " MI ,LCD interface (Motorola 6800/Intel 8080) mode" "8080,6800" textline " " bitfld.long 0x00 1. " PS ,LCD interface (Parallel/Serial) mode" "Parallel,Serial" elif ((d.l(ad:(0x15000400+0x4))&0x2)==0x2) group.long 0x04++0x3 line.long 0x00 "LCD_CONTROL,Control register" bitfld.long 0x00 20. " BYASYNC_RELCLK ,Bypass the logic which assumes asynchronous relation between PCLK & LCDCLK" "Not bypassed,Bybass" bitfld.long 0x00 19. " IF_16 ,Interface to 16 bit LCD-Controller" "Non 16-bit,16-bit" textline " " bitfld.long 0x00 18. " LOOPBACK ,Operation mode" "Normal,Loopback" bitfld.long 0x00 17. " MSB_FIRST ,Transmission mode" "bit 0 first,bit 7 first" textline " " bitfld.long 0x00 16. " INVERT_E_RD ,E_RD output pin" "Active low,Active high" bitfld.long 0x00 15. " INVERT_CS ,Chip select output" "Active high,Active low" textline " " bitfld.long 0x00 14. " BUSY_RS_VALUE ,busy check condition" "0,1" bitfld.long 0x00 10.--13. " BUSY_BIT_NR ,4 bit value of the 6800/8080 bus which represents the busy flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 9. " BUSY_VALUE ,LCD controller busy" "Idle,Busy" bitfld.long 0x00 8. " BUSY_FLAG_CHECK ,Busy-flag checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " SERIAL_READ_POS ,Sampling timing" "beginning of the cycle,0.25 * cycle,0.5 * cycle,0.75 * cycle" bitfld.long 0x00 4.--5. " SERIAL_CLK_SHIFT ,Clock mode" "0,1,2,3" textline " " bitfld.long 0x00 3. " IF ,LCD interface (4-bit/8-bit) mode" "8-bit,4-bit" bitfld.long 0x00 2. " MI ,LCD interface (Motorola 6800/Intel 8080) mode" "8080,6800" textline " " bitfld.long 0x00 1. " PS ,LCD interface (Parallel/Serial) mode" "Parallel,Serial" else group.long 0x04++0x3 line.long 0x00 "LCD_CONTROL,Control register" bitfld.long 0x00 20. " BYASYNC_RELCLK ,Bypass the logic which assumes asynchronous relation between PCLK & LCDCLK" "Not bypassed,Bybass" bitfld.long 0x00 19. " IF_16 ,Interface to 16 bit LCD-Controller" "Non 16-bit,16-bit" textline " " bitfld.long 0x00 18. " LOOPBACK ,Operation mode" "Normal,Loopback" bitfld.long 0x00 17. " MSB_FIRST ,Transmission mode" "bits 3-0 first,bits 7-4 first" textline " " bitfld.long 0x00 16. " INVERT_E_RD ,E_RD output pin" "Active low,Active high" bitfld.long 0x00 15. " INVERT_CS ,Chip select output" "Active high,Active low" textline " " bitfld.long 0x00 14. " BUSY_RS_VALUE ,busy check condition" "0,1" bitfld.long 0x00 10.--13. " BUSY_BIT_NR ,4 bit value of the 6800/8080 bus which represents the busy flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 9. " BUSY_VALUE ,LCD controller busy" "Idle,Busy" bitfld.long 0x00 8. " BUSY_FLAG_CHECK ,Busy-flag checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " SERIAL_READ_POS ,Sampling timing" "beginning of the cycle,0.25 * cycle,0.5 * cycle,0.75 * cycle" bitfld.long 0x00 4.--5. " SERIAL_CLK_SHIFT ,Clock mode" "0,1,2,3" textline " " bitfld.long 0x00 3. " IF ,LCD interface (4-bit/8-bit) mode" "8-bit,4-bit" bitfld.long 0x00 2. " MI ,LCD interface (Motorola 6800/Intel 8080) mode" "8080,6800" textline " " bitfld.long 0x00 1. " PS ,LCD interface (Parallel/Serial) mode" "Parallel,Serial" endif rgroup.long 0x08++0x3 line.long 0x00 "LCD_INT_RAW,Interrupt Raw register" bitfld.long 0x00 3. " LCD_INT_READ_VALID_RAW ,Value read from the LCD controller valid" "No interrupt,Interrupt" bitfld.long 0x00 2. " LCD_INT_OVERRUN_RAW ,FIFO overrun" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " LCD_INT_FIFO_HALF_EMPTY_RAW ,FIFO is less then half full" "No interrupt,Interrupt" bitfld.long 0x00 0. " LCD_INT_FIFO_EMPTY_RAW ,FIFO is empty" "No interrupt,Interrupt" wgroup.long 0x0c++0x3 line.long 0x00 "LCD_INT_CLEAR,Interrupt Clear register" bitfld.long 0x00 3. " LCD_INT_READ_VALID_RAW_CLR ,Value read from the LCD controller valid interrupt clear" "No effect,Clear" bitfld.long 0x00 2. " LCD_INT_OVERRUN_RAW_CLR ,FIFO overrun interrupt clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " LCD_INT_FIFO_HALF_EMPTY_RAW_CLR ,FIFO is less then half full interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " LCD_INT_FIFO_EMPTY_RAW_CLR ,FIFO is empty interrupt clear" "No effect,Clear" group.long 0x10++0x3 line.long 0x00 "LCD_INT_MASK,Interrupt Mask Register" bitfld.long 0x00 3. " LCD_INT_READ_VALID_RAW_MASK ,Value read from the LCD controller valid interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " LCD_INT_OVERRUN_RAW_MASK ,FIFO overrun interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " LCD_INT_FIFO_HALF_EMPTY_RAW_MASK ,FIFO is less then half full interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " LCD_INT_FIFO_EMPTY_RAW_MASK ,FIFO is empty interrupt mask" "Not masked,Masked" wgroup.long 0x14++0x3 line.long 0x00 "LCD_READ_CMD,Read Command Register" bitfld.long 0x00 0. " LCD_READ_COMMAND ,Read operation on the LCD Interface bus" "DATA_BYTE,INST_BYTE" if ((d.l(ad:(0x15000400+0x4))&0x80000)==0x80000) group.long 0x20++0x3 line.long 0x00 "LCD_INST_BYTE,Instruction Byte Register" hexmask.long.word 0x00 0.--15. 1. " INST_BYTE ,Instruction" elif (((d.l(ad:(0x15000400+0x4))&0x80000)==0x0)&&((d.l(ad:(0x15000400+0x4))&0x8)==0x0)) group.long 0x20++0x3 line.long 0x00 "LCD_INST_BYTE,Instruction Byte Register" hexmask.long.byte 0x00 0.--7. 1. " INST_BYTE ,Instruction" else hgroup.long 0x20++0x3 hide.long 0x00 "LCD_INST_BYTE,Instruction Byte Register" endif if ((d.l(ad:(0x15000400+0x4))&0x80000)==0x80000) group.long 0x30++0x3 line.long 0x00 "LCD_DATA_BYTE,Data Byte Register" hexmask.long.word 0x00 0.--15. 1. " DATA_BYTE ,Data" elif (((d.l(ad:(0x15000400+0x4))&0x80000)==0x0)&&((d.l(ad:(0x15000400+0x4))&0x8)==0x0)) group.long 0x30++0x3 line.long 0x00 "LCD_DATA_BYTE,Data Byte Register" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Data" else group.long 0x30++0x3 line.long 0x00 "LCD_DATA_BYTE,Data Byte Register" endif wgroup.long 0x40++0x3 line.long 0x00 "LCD_INST_WORD, Instruction Word Register" wgroup.long 0x80++0x3 line.long 0x00 "LCD_DATA_WORD,Data Word Register" width 0xb tree.end tree.open "I2C (Inter-Integrated Circuit)" tree "I2C 1" base ad:0x1300A000 width 13. hgroup.long 0x00++0x3 hide.long 0x0 "I2C1_RX/TX,I2C 1 RX/TX Data FIFO" in group.long 0x04++0x13 line.long 0x0 "I2C1_STAT,I2C 1 Status Register" bitfld.long 0x00 13. " TFES ,Slave Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 12. " TFFS ,Slave Transmit FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 10. " TFF ,Transmit FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 9. " RFE ,Receive FIFO Empty" "Not empty,Empty" bitfld.long 0x00 8. " RFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 7. " SDA ,The current value of the SDA signal" "Low,High" bitfld.long 0x00 6. " SCL ,The current value of the SCL signal" "Low,High" textline " " bitfld.long 0x00 5. " ACTIVE ,Bus activity" "Idle,Busy" bitfld.long 0x00 4. " DRSI ,Slave Data Request Interrupt" "Not requested,Requested" textline " " bitfld.long 0x00 3. " DRMI ,Master Data Request Interrupt" "Not requested,Requested" bitfld.long 0x00 2. " NAI ,No Acknowledge Interrupt" "Acknowledged,Not acknowledged" textline " " eventfld.long 0x00 1. " AFI ,Arbitration Failure Interrupt" "Not failed,Failed" eventfld.long 0x00 0. " TDI ,Transaction Done Interrupt" "Not completed,Completed" line.long 0x04 "I2C1_CTRL,I2C 1 Control Register" bitfld.long 0x04 10. " TFFSIE ,Slave Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " SEVEN ,Seven-bit slave address" "7-bit,10-bit" textline " " sif (cpuis("LPC313*")) bitfld.long 0x04 8. " RESET ,Soft Reset" "No effect,Reset" else bitfld.long 0x04 8. " RFF ,Soft Reset" "No effect,Reset" endif bitfld.long 0x04 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " RFDAIE ,Receive FIFO Data Available Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " RFFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " DRSIE ,Data Request Slave Transmitter Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 3. " DRMIE ,Data Request Master Transmitter Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " AFIE ,Transmitter Arbitration Failure Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled" line.long 0x08 "I2C1_CLK_HI,I2C 1 Clock Divider High Register" hexmask.long.word 0x08 0.--9. 1. " CLK_DIV_HI ,Clock Divisor High" line.long 0x0C "I2C1_CLK_LO,I2C 1 Clock Divider Low Register" hexmask.long.word 0x0C 0.--9. 1. " CLK_DIV_LO ,Clock Divisor Low" line.long 0x10 "I2C1_ADR, I2C 1 Slave Address" hexmask.long.word 0x10 0.--9. 1. " ADR ,ADR is the I2C bus slave address" group.long 0x18++0xF line.long 0x00 "I2C1_RXFL,I2C 1 Receive FIFO level" bitfld.long 0x00 0.--1. " RXFL , Receive FIFO level" "0,1,2,3" line.long 0x04 "I2C1_TXFL,I2C 1 Transmit FIFO level" bitfld.long 0x04 0.--1. " TXFL , Transmit FIFO level" "0,1,2,3" line.long 0x08 "I2C1_RXB,I2Cn Receive byte count" hexmask.long.word 0x08 0.--15. 1. " RXB ,Number of bytes received" line.long 0x0C "I2C1_TXB,I2Cn Transmit byte count" hexmask.long.word 0x0C 0.--15. 1. " TXB ,Number of bytes transmit" wgroup.long 0x28++0x3 line.long 0x00 "I2C1_S_TX,Slave Transmit FIFO" hexmask.long.byte 0x00 0.--7. 1. " TXS ,Slave Transmit FIFO data bits 7:0" rgroup.long 0x2C++0x3 line.long 0x00 "I2C1_S_TXFL, Slave Transmit FIFO level" bitfld.long 0x00 0.--1. " TXFL , Slave Transmit FIFO level" "0,1,2,3" width 0xB tree.end tree "I2C 2" base ad:0x1300A400 width 13. hgroup.long 0x00++0x3 hide.long 0x0 "I2C2_RX/TX,I2C 2 RX/TX Data FIFO" in group.long 0x04++0x13 line.long 0x0 "I2C2_STAT,I2C 2 Status Register" bitfld.long 0x00 13. " TFES ,Slave Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 12. " TFFS ,Slave Transmit FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 10. " TFF ,Transmit FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 9. " RFE ,Receive FIFO Empty" "Not empty,Empty" bitfld.long 0x00 8. " RFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 7. " SDA ,The current value of the SDA signal" "Low,High" bitfld.long 0x00 6. " SCL ,The current value of the SCL signal" "Low,High" textline " " bitfld.long 0x00 5. " ACTIVE ,Bus activity" "Idle,Busy" bitfld.long 0x00 4. " DRSI ,Slave Data Request Interrupt" "Not requested,Requested" textline " " bitfld.long 0x00 3. " DRMI ,Master Data Request Interrupt" "Not requested,Requested" bitfld.long 0x00 2. " NAI ,No Acknowledge Interrupt" "Acknowledged,Not acknowledged" textline " " eventfld.long 0x00 1. " AFI ,Arbitration Failure Interrupt" "Not failed,Failed" eventfld.long 0x00 0. " TDI ,Transaction Done Interrupt" "Not completed,Completed" line.long 0x04 "I2C2_CTRL,I2C 2 Control Register" bitfld.long 0x04 10. " TFFSIE ,Slave Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " SEVEN ,Seven-bit slave address" "7-bit,10-bit" textline " " sif (cpuis("LPC313*")) bitfld.long 0x04 8. " RESET ,Soft Reset" "No effect,Reset" else bitfld.long 0x04 8. " RFF ,Soft Reset" "No effect,Reset" endif bitfld.long 0x04 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " RFDAIE ,Receive FIFO Data Available Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " RFFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " DRSIE ,Data Request Slave Transmitter Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 3. " DRMIE ,Data Request Master Transmitter Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " AFIE ,Transmitter Arbitration Failure Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled" line.long 0x08 "I2C2_CLK_HI,I2C 2 Clock Divider High Register" hexmask.long.word 0x08 0.--9. 1. " CLK_DIV_HI ,Clock Divisor High" line.long 0x0C "I2C2_CLK_LO,I2C 2 Clock Divider Low Register" hexmask.long.word 0x0C 0.--9. 1. " CLK_DIV_LO ,Clock Divisor Low" line.long 0x10 "I2C2_ADR, I2C 2 Slave Address" hexmask.long.word 0x10 0.--9. 1. " ADR ,ADR is the I2C bus slave address" group.long 0x18++0xF line.long 0x00 "I2C2_RXFL,I2C 2 Receive FIFO level" bitfld.long 0x00 0.--1. " RXFL , Receive FIFO level" "0,1,2,3" line.long 0x04 "I2C2_TXFL,I2C 2 Transmit FIFO level" bitfld.long 0x04 0.--1. " TXFL , Transmit FIFO level" "0,1,2,3" line.long 0x08 "I2C2_RXB,I2Cn Receive byte count" hexmask.long.word 0x08 0.--15. 1. " RXB ,Number of bytes received" line.long 0x0C "I2C2_TXB,I2Cn Transmit byte count" hexmask.long.word 0x0C 0.--15. 1. " TXB ,Number of bytes transmit" wgroup.long 0x28++0x3 line.long 0x00 "I2C2_S_TX,Slave Transmit FIFO" hexmask.long.byte 0x00 0.--7. 1. " TXS ,Slave Transmit FIFO data bits 7:0" rgroup.long 0x2C++0x3 line.long 0x00 "I2C2_S_TXFL, Slave Transmit FIFO level" bitfld.long 0x00 0.--1. " TXFL , Slave Transmit FIFO level" "0,1,2,3" width 0xB tree.end tree.end tree.open "Timers" tree "Timer 0" base ad:0x13008000 width 12. group.long 0x00++0x3 line.long 0x00 "TIMERLOAD,Timer Load Register" rgroup.long 0x04++0x3 line.long 0x00 "TIMERVALUE,Timer Value Register" group.long 0x08++0x3 line.long 0x00 "TIMERCTRL,Timer Control Register" bitfld.long 0x00 7. " Enable ,Timer Enable" "Disabled,Enabled" bitfld.long 0x00 6. " Mode ,Timer Mode" "Free running,Periodic Timer" textline " " bitfld.long 0x00 2.--3. " PreScale ,Clock divider/Stages of Pre-Scale" "Div by 1/ 0 stages,Div by 16 / 4 stages,Div by 256 / 8 stages,?..." wgroup.long 0x0c++0x3 line.long 0x00 "TIMERCLEAR,Timer Clear Register" width 0xb tree.end tree "Timer 1" base ad:0x13008400 width 12. group.long 0x00++0x3 line.long 0x00 "TIMERLOAD,Timer Load Register" rgroup.long 0x04++0x3 line.long 0x00 "TIMERVALUE,Timer Value Register" group.long 0x08++0x3 line.long 0x00 "TIMERCTRL,Timer Control Register" bitfld.long 0x00 7. " Enable ,Timer Enable" "Disabled,Enabled" bitfld.long 0x00 6. " Mode ,Timer Mode" "Free running,Periodic Timer" textline " " bitfld.long 0x00 2.--3. " PreScale ,Clock divider/Stages of Pre-Scale" "Div by 1/ 0 stages,Div by 16 / 4 stages,Div by 256 / 8 stages,?..." wgroup.long 0x0c++0x3 line.long 0x00 "TIMERCLEAR,Timer Clear Register" width 0xb tree.end tree "Timer 2" base ad:0x13008800 width 12. group.long 0x00++0x3 line.long 0x00 "TIMERLOAD,Timer Load Register" rgroup.long 0x04++0x3 line.long 0x00 "TIMERVALUE,Timer Value Register" group.long 0x08++0x3 line.long 0x00 "TIMERCTRL,Timer Control Register" bitfld.long 0x00 7. " Enable ,Timer Enable" "Disabled,Enabled" bitfld.long 0x00 6. " Mode ,Timer Mode" "Free running,Periodic Timer" textline " " bitfld.long 0x00 2.--3. " PreScale ,Clock divider/Stages of Pre-Scale" "Div by 1/ 0 stages,Div by 16 / 4 stages,Div by 256 / 8 stages,?..." wgroup.long 0x0c++0x3 line.long 0x00 "TIMERCLEAR,Timer Clear Register" width 0xb tree.end tree "Timer 3" base ad:0x13008C00 width 12. group.long 0x00++0x3 line.long 0x00 "TIMERLOAD,Timer Load Register" rgroup.long 0x04++0x3 line.long 0x00 "TIMERVALUE,Timer Value Register" group.long 0x08++0x3 line.long 0x00 "TIMERCTRL,Timer Control Register" bitfld.long 0x00 7. " Enable ,Timer Enable" "Disabled,Enabled" bitfld.long 0x00 6. " Mode ,Timer Mode" "Free running,Periodic Timer" textline " " bitfld.long 0x00 2.--3. " PreScale ,Clock divider/Stages of Pre-Scale" "Div by 1/ 0 stages,Div by 16 / 4 stages,Div by 256 / 8 stages,?..." wgroup.long 0x0c++0x3 line.long 0x00 "TIMERCLEAR,Timer Clear Register" width 0xb tree.end tree.end tree "PWM (Pulse Width Modulator)" base ad:0x13009000 width 5. group.long 0x00++0x7 line.long 0x00 "TMR,Timer Register" hexmask.long.word 0x00 0.--11. 1. " MR ,Timer used for PWM and PDM" line.long 0x04 "CNTL,Control Register" bitfld.long 0x04 7. " PDM ,PDM mode" "Disabled,Enabled" bitfld.long 0x04 6. " LOOP ,Output inverted with a repetition of the top4 tmr bits" "Disabled,Enabled" bitfld.long 0x04 4. " HI ,Pwm output forced high" "Not forced,Forced" bitfld.long 0x04 0.--1. " CLK ,pwm_clk used for generating the output pulses:" "pwm_clk,pwm_clk/2,pwm_clk/4,pwm_clk/8" width 0xb tree.end tree.open "System Control" base ad:0x13002800 width 31. tree "Miscellaneous System Configuration" group.long 0x08++0x13 line.long 0x00 "SYSCREG_EBI_MPMC_PRIO,Priority of MPMC channel for EBI interface" hexmask.long.word 0x00 0.--9. 1. " TIMEOUTVALUE ,Time out value of the MPMC channel" line.long 0x04 "SYSCREG_EBI_NANDC_PRIO, Priority of NAND controller channel for EBI interface" hexmask.long.word 0x04 0.--9. 1. " TIMEOUTVALUE ,Time out value of the NAND controller channel" line.long 0x08 "SYSCREG_EBI_UNUSED_PRIO,Priority of unused channel" hexmask.long.word 0x08 0.--9. 1. " TIMEOUTVALUE ,Time out value of unused channel" line.long 0x0c "SYSCREG_RING_OSC_CFG,RING oscillator configuration register" bitfld.long 0x0c 1. " RING_OSC_CFG_OSC1_EN ,Enable of the ring oscillator 1" "Disabled,Enabled" textline " " bitfld.long 0x0c 0. " RING_OSC_CFG_OSC0_EN ,Enable of the ring oscillator 0" "Disabled,Enabled" line.long 0x10 "SYSCREG_ADC_PD_ADC10BITS,Powerdown register of ADC 10bits" bitfld.long 0x10 0. " ADC_PD_ADC10BITS ,Powerdown bit 10 bits ADC" "Disabled,Enabled" hgroup.long 0x1c++0x7 hide.long 0x00 "SYSCREG_CGU_DYN_HP0,SYSCREG_CGU_DYN_HP0" hide.long 0x04 "SYSCREG_CGU_DYN_HP1,SYSCREG_CGU_DYN_HP1" group.long 0x24++0xb line.long 0x00 "SYSCREG_ABC_CFG,AHB burst control register" bitfld.long 0x00 9.--11. " USB_OTG ,AHB master USB_OTG to control its AHB bus bandwidth" "Normal mode,Make any burst a non-sequential access,SPlit to 4-beat,SPlit to 8-beat,eXTend to 8-beat,eXTend to 16-beat,SPlit to 4-beat,eXTend to 32-beat" textline " " bitfld.long 0x00 6.--8. " ARM926EJS_I ,AHB master ARM926EJS instruction port to control its AHB bus bandwidth" "Normal mode,Make any burst a non-sequential access,SPlit to 4-beat,SPlit to 8-beat,eXTend to 8-beat,eXTend to 16-beat,SPlit to 4-beat,eXTend to 32-beat" textline " " bitfld.long 0x00 3.--5. " ARM926EJS_D ,AHB master ARM926EJS data port to control its AHB bus bandwidth" "Normal mode,Make any burst a non-sequential access,SPlit to 4-beat,SPlit to 8-beat,eXTend to 8-beat,eXTend to 16-beat,SPlit to 4-beat,eXTend to 32-beat" textline " " bitfld.long 0x00 0.--2. " SIMPLE_DMA ,AHB master dma to control its AHB bus bandwidth" "Normal mode,Make any burst a non-sequential access,SPlit to 4-beat,SPlit to 8-beat,eXTend to 8-beat,eXTend to 16-beat,SPlit to 4-beat,eXTend to 32-beat" line.long 0x04 "SYSCREG_SD_MMC_CFG,SD_MMC (MCI) configuration register" bitfld.long 0x04 1. " CARD_DETECT_N ,Card detect signal" "Present,Not present" textline " " bitfld.long 0x04 0. " CARD_WRITE_PRT ,Card write protect signal for SD cards" "Not protected,Protected" line.long 0x08 "SYSCREG_MCI_DELAYMODES,Delay register for the SD_MMC (MCI) clocks" bitfld.long 0x08 4. " DELAY_ENABLE ,Enable delay cells" "Disabled,Enabled" textline " " bitfld.long 0x08 0.--3. " DELAY_CELLS ,Number of delay cells to obtain the needed delay for cclk_in_drv" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x7 line.long 0x00 "SYSCREG_AHB0_EXTPRIO,Priority of the AHB masters" bitfld.long 0x00 3. " USB_OTG ,USB OTG higher priority" "Normal,Higher" textline " " bitfld.long 0x00 2. " ARM926_DATA_BUS ,ARM926 Data higher priority" "Normal,Higher" textline " " bitfld.long 0x00 1. " ARM926_INSTRUCTION_BUS ,ARM926 Instruction higher priority" "Normal,Higher" textline " " bitfld.long 0x00 0. " DMA ,DMA HIGHER PRIORITY" "Normal,Higher" line.long 0x04 "SYSCREG_ARM926_SHADOW_POINTER,Memory mapping" tree.end width 30. tree "USB Configuration" group.long 0x30++0x7 line.long 0x00 "SYSCREG_USB_ATX_PLL_PD_REG,Power down register of USB ATX PLL" bitfld.long 0x00 0. " USB_ATX_PLL_PD_REG ,Powerdown bit of the USB pll" "Powered down,Active" line.long 0x04 "SYSCREG_USB_OTG_CFG,USB OTG configuration register" bitfld.long 0x04 3. " USB_OTG_VBUS_PWR_FAULT ,Indication of the charge pump overcurrent" "Not detected,Detected" textline " " bitfld.long 0x04 2. " USB_OTG_DEV_WAKEUP_N ,External wakeup signal for device mode" "Not detected,Detected" textline " " bitfld.long 0x04 1. " USB_OTG_HOST_WAKEUP_N ,External wake-up signal for host mode" "Not detected,Detected" rgroup.long 0x38++0x3 line.long 0x00 "SYSCREG_USB_OTG_PORT_IND_CTL,USB OTG port indicator LED control outputs" bitfld.long 0x00 0.--1. " USB_OTG_PORT_IND_CTL ,Status bits for USB connector LEDs" "Off,Amber,Green,?..." group.long 0x40++0x17 line.long 0x00 "SYSCREG_USB_PLL_NDEC,USB OTG PLL configuration register NOEC" hexmask.long.word 0x00 0.--9. 1. " USB_PLL_NDEC , Pre-divider for the USB pll" line.long 0x04 "SYSCREG_USB_PLL_MDEC,USB OTG PLL configuration register MDEC" hexmask.long.tbyte 0x04 0.--16. 1. " USB_PLL_MDEC ,Feedback-divider for the USB pll" line.long 0x08 "SYSCREG_USB_PLL_PDEC,USB OTG PLL configuration register PDEC" bitfld.long 0x08 0.--3. " USB_PLL_PDEC ,Feedback-divider for the USB pll" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0c "SYSCREG_USB_PLL_SELR,USB OTG PLL configuration register SELR" bitfld.long 0x0c 0.--3. " USB_PLL_SELR ,Bandwidth selection selr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYSCREG_USB_PLL_SELI,USB OTG PLL configuration register SELI" bitfld.long 0x10 0.--3. " USB_PLL_SELI ,Bandwidth selection seli" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYSCREG_USB_PLL_SELP,USB OTG PLL configuration register SELP" bitfld.long 0x14 0.--3. " USB_PLL_SELP ,Bandwidth selection selp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 28. tree "ISRAM/ISROM Configuration" group.long 0x58++0x3 line.long 0x00 "SYSCREG_ISRAM0_LATENCY_CFG,Internal SRAM 0 latency configuration register" bitfld.long 0x00 0.--1. " ISRAM0_LATENCY_CFG ,Number of waitstates" "0 wait states,1 wait state,Reserved,2 wait state" sif (cpu()=="LPC3131") group.long 0x5c++0x3 line.long 0x00 "SYSCREG_ISRAM1_LATENCY_CFG,Internal SRAM 1 latency configuration register" bitfld.long 0x00 0.--1. " ISRAM1_LATENCY_CFG ,Number of waitstates" "0 wait states,1 wait state,Reserved,2 wait state" endif group.long 0x60++0x3 line.long 0x00 "SYSCREG_ISROM_LATENCY_CFG,Internal SROM latency configuration register" bitfld.long 0x00 0.--1. " ISROM_LATENCY_CFG ,Number of waitstates" "0 wait states,1 wait state,Reserved,2 wait state" tree.end width 30. tree "MPMC Configuration" group.long 0x64++0x1B line.long 0x00 "SYSCREG_AHB_MPMC_MISC,Configuration register of MPMC" bitfld.long 0x00 8. " AHB_MPMC_MISC_REL1CONFIG ,Static memory address mode select" "Low,High" textline " " bitfld.long 0x00 7. " AHB_MPMC_MISC_STCS1PB ,Polarity of byte lane select for static memory CS1 (read/write)" "Active HIGH/Active Low,Active Low/Active Low" textline " " bitfld.long 0x00 4. " AHB_MPMC_MISC_STCS1POL ,Polarity of static memory CS1" "Active LOW,Active HIGH" textline " " bitfld.long 0x00 3. " AHB_MPMC_MISC_STCS0POL ,Polarity of static memory CS0" "Active LOW,Active HIGH" textline " " bitfld.long 0x00 0. " AHB_MPMC_MISC_SREFREQ ,Self refresh request" "Not requested,Requested" line.long 0x04 "SYSCREG_MPMP_DELAYMODES,Configuration of MPMC clock delay" bitfld.long 0x04 12.--17. " MPMC_DELAYMODES ,Configures the amount of delay cells used for delaying MPMCCLKOUT (WC Delay/BC Delay)" "0.44 / 0.16,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,5.12 / 2.61,6.43 / 3.14,7.60 / 3.59,8.91 / 4.12,10.01 / 4.61,11.32 / 5.14,12.49 / 5.59,13.80 / 6.12,14.75 / 6.56,16.06 / 7.09,17.23 / 7.54,18.54 / 8.07,19.64 / 8.56,20.95 / 9.09,22.12 / 9.54,23.43 / 10.07,24.15 / 10.40,25.46 / 10.93,26.63 / 11.38,27.94 / 11.91,29.04 / 12.40,30.35 / 12.93,31.52 / 13.38,32.83 / 13.91,33.78 / 14.35,35.09 / 14.88,36.26 / 15.33,37.57 / 15.86,38.67 / 16.35,39.98 / 16.88,41.15 / 17.33,42.46 / 17.86" textline " " bitfld.long 0x04 6.--11. " MPMC_DELAYMODES ,Configures the amount of delay cells, between MPMCCLK and MPMCCLKDELAY (WC Delay/BC Delay)" "0.44 / 0.16,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,5.12 / 2.61,6.43 / 3.14,7.60 / 3.59,8.91 / 4.12,10.01 / 4.61,11.32 / 5.14,12.49 / 5.59,13.80 / 6.12,14.75 / 6.56,16.06 / 7.09,17.23 / 7.54,18.54 / 8.07,19.64 / 8.56,20.95 / 9.09,22.12 / 9.54,23.43 / 10.07,24.15 / 10.40,25.46 / 10.93,26.63 / 11.38,27.94 / 11.91,29.04 / 12.40,30.35 / 12.93,31.52 / 13.38,32.83 / 13.91,33.78 / 14.35,35.09 / 14.88,36.26 / 15.33,37.57 / 15.86,38.67 / 16.35,39.98 / 16.88,41.15 / 17.33,42.46 / 17.86" textline " " bitfld.long 0x04 0.--5. " MPMC_DELAYMODES ,Configures the amount of delay cells between MPMCCLK and MPMCFBCLKIN (WC Delay/BC Delay)" "0.44 / 0.16,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,5.12 / 2.61,6.43 / 3.14,7.60 / 3.59,8.91 / 4.12,10.01 / 4.61,11.32 / 5.14,12.49 / 5.59,13.80 / 6.12,14.75 / 6.56,16.06 / 7.09,17.23 / 7.54,18.54 / 8.07,19.64 / 8.56,20.95 / 9.09,22.12 / 9.54,23.43 / 10.07,24.15 / 10.40,25.46 / 10.93,26.63 / 11.38,27.94 / 11.91,29.04 / 12.40,30.35 / 12.93,31.52 / 13.38,32.83 / 13.91,33.78 / 14.35,35.09 / 14.88,36.26 / 15.33,37.57 / 15.86,38.67 / 16.35,39.98 / 16.88,41.15 / 17.33,42.46 / 17.86" line.long 0x08 "SYSCREG_MPMC_WAITREAD_DELAY0,Configuration of the wait cycles for read transfers" bitfld.long 0x08 5. " ENABLE_EXTRA_OE_INACTIVE_CYCLE ,Enable the extra inactive OE cycle" "Disabled,Enabled" textline " " bitfld.long 0x08 0.--4. " STATIC_READ_WAIT_COUNTER ,Value should be as in MPMCStaticWaitRd0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0c "SYSCREG_MPMC_WAITREAD_DELAY1,Configuration of the wait cycles for read transfers" bitfld.long 0x0c 5. " ENABLE_EXTRA_OE_INACTIVE_CYCLE ,Enable the extra inactive OE cycle" "Disabled,Enabled" textline " " bitfld.long 0x0c 0.--4. " STATIC_READ_WAIT_COUNTER ,Value should be as in MPMCStaticWaitRd1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "SYSCREG_WIRE_EBI_MSIZE_INIT,Configuration of the memory width for MPMC" bitfld.long 0x10 0.--1. " WIRE_EBI_MSIZE_INIT ,Memory width of CS1" "8-bit,16-bit,?..." line.long 0x14 "SYSCREG_MPMC_TESTMODE0,Configuration for refresh generation of MPMC" bitfld.long 0x14 12. " EXTERNAL_REFRESH_ENABLE ,Source 0f the refresh generation of the MPMC" "Normal,External" textline " " hexmask.long.word 0x14 0.--11. 1. " EXTERNAL_REFRESH_COUNTER_VALUE ,Period of every external refresh" line.long 0x18 "SYSCREG_MPMC_TESTMODE1,Configuration for refresh generation of MPMC" hexmask.long.byte 0x18 0.--7. 1. " HIGH_SPEED_COUNTER_GEN ,Clock cycles CGU will be active at the moment of refresh request" tree.end width 27. tree "Pin Multiplexing Control" group.long 0x90++0x13 line.long 0x00 "SYSCREG_MUX_LCD_EBI_SEL,Selects between lcd_interface and EBI pins" bitfld.long 0x00 0. " MUX_LCD_EBI_SEL ,Selects between lcd_interface and EBI/MPMC pins" "LCD,EBI/MPMC" line.long 0x04 "SYSCREG_MUX_GPIO_MCI_SEL,Selects between GPIO and MCI pins" bitfld.long 0x04 0. " MUX_GPIO_MCI_SEL ,Selects between GPIO and MCI pins" "GPIO,MCI" line.long 0x08 "SYSCREG_MUX_NAND_MCI_SEL,Selects between NAND flash controller and MCI pins" bitfld.long 0x08 0. " MUX_NAND_MCI_SEL ,Selects between NANDI and MCI pins" "NAND,MCI" line.long 0x0c "SYSCREG_MUX_UART_SPI_SEL,Selects between UART and SPI pins" bitfld.long 0x0c 0. " MUX_UART_SPI_SEL ,Selects between SPI and UART pins" "UART,SPI" line.long 0x10 "SYSCREG_MUX_I2STX_PCM_SEL,Selects between I2STX and PCM pins" bitfld.long 0x10 0. " MUX_I2STX_0_PCM_SEL ,Selects between I2STX_0 and IPINT_1 pins" "I2STX_0,PCM" tree.end width 32. tree "Pad Configuration" group.long 0xa4++0x18f line.long 0x0 "SYSCREG_EBI_D_9_PCTRL," bitfld.long 0x0 0.--1. " MODE ,input to the programmable section of the EBI_D_9 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x4 "SYSCREG_EBI_D_10_PCTRL," bitfld.long 0x4 0.--1. " MODE ,input to the programmable section of the EBI_D_10 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x8 "SYSCREG_EBI_D_11_PCTRL," bitfld.long 0x8 0.--1. " MODE ,input to the programmable section of the EBI_D_11 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xC "SYSCREG_EBI_D_12_PCTRL," bitfld.long 0xC 0.--1. " MODE ,input to the programmable section of the EBI_D_12 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x10 "SYSCREG_EBI_D_13_PCTRL," bitfld.long 0x10 0.--1. " MODE ,input to the programmable section of the EBI_D_13 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x14 "SYSCREG_EBI_D_14_PCTRL," bitfld.long 0x14 0.--1. " MODE ,input to the programmable section of the EBI_D_14 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x18 "SYSCREG_I2SRX_BCK0_PCTRL," bitfld.long 0x18 0.--1. " MODE ,input to the programmable section of the I2SRX_BCK0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x1C "SYSCREG_MGPIO9_PCTRL," bitfld.long 0x1C 0.--1. " MODE ,input to the programmable section of the MGPIO9 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x20 "SYSCREG_MGPIO6_PCTRL," bitfld.long 0x20 0.--1. " MODE ,input to the programmable section of the MGPIO6 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x24 "SYSCREG_MLCD_DB_7_PCTRL," bitfld.long 0x24 0.--1. " MODE ,input to the programmable section of the MLCD_DB_7 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x28 "SYSCREG_MLCD_DB_4_PCTRL," bitfld.long 0x28 0.--1. " MODE ,input to the programmable section of the MLCD_DB_4 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x2C "SYSCREG_MLCD_DB_2_PCTRL," bitfld.long 0x2C 0.--1. " MODE ,input to the programmable section of the MLCD_DB_2 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x30 "SYSCREG_MNAND_RYBN0_PCTRL," bitfld.long 0x30 0.--1. " MODE ,input to the programmable section of the MNAND_RYBN0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x34 "SYSCREG_GPIO1_PCTRL," bitfld.long 0x34 0.--1. " MODE ,input to the programmable section of the GPIO1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x38 "SYSCREG_EBI_D_4_PCTRL," bitfld.long 0x38 0.--1. " MODE ,input to the programmable section of the EBI_D_4 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x3C "SYSCREG_MI2STX_CLK0_PCTRL," bitfld.long 0x3C 0.--1. " MODE ,input to the programmable section of the MI2STX_CLK0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x40 "SYSCREG_MI2STX_BCK0_PCTRL," bitfld.long 0x40 0.--1. " MODE ,input to the programmable section of the MI2STX_BCK0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x44 "SYSCREG_EBI_A_1_CLE_PCTRL," bitfld.long 0x44 0.--1. " MODE ,input to the programmable section of the EBI_A_1_CLE pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x48 "SYSCREG_EBI_NCAS_BLOUT_0_PCTRL," bitfld.long 0x48 0.--1. " MODE ,input to the programmable section of the EBI_NCAS_BLOUT_0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x4C "SYSCREG_NAND_NCS_3_PCTRL," bitfld.long 0x4C 0.--1. " MODE ,input to the programmable section of the NAND_NCS_3 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x50 "SYSCREG_MLCD_DB_0_PCTRL," bitfld.long 0x50 0.--1. " MODE ,input to the programmable section of the MLCD_DB_0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x54 "SYSCREG_EBI_DQM_0_NOE_PCTRL," bitfld.long 0x54 0.--1. " MODE ,input to the programmable section of the EBI_DQM_0_NOE pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x58 "SYSCREG_EBI_D_0_PCTRL," bitfld.long 0x58 0.--1. " MODE ,input to the programmable section of the EBI_D_0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x5C "SYSCREG_EBI_D_1_PCTRL," bitfld.long 0x5C 0.--1. " MODE ,input to the programmable section of the EBI_D_1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x60 "SYSCREG_EBI_D_2_PCTRL," bitfld.long 0x60 0.--1. " MODE ,input to the programmable section of the EBI_D_2 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x64 "SYSCREG_EBI_D_3_PCTRL," bitfld.long 0x64 0.--1. " MODE ,input to the programmable section of the EBI_D_3 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x68 "SYSCREG_EBI_D_5_PCTRL," bitfld.long 0x68 0.--1. " MODE ,input to the programmable section of the EBI_D_5 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x6C "SYSCREG_EBI_D_6_PCTRL," bitfld.long 0x6C 0.--1. " MODE ,input to the programmable section of the EBI_D_6 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x70 "SYSCREG_EBI_D_7_PCTRL," bitfld.long 0x70 0.--1. " MODE ,input to the programmable section of the EBI_D_7 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x74 "SYSCREG_EBI_D_8_PCTRL," bitfld.long 0x74 0.--1. " MODE ,input to the programmable section of the EBI_D_8 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x78 "SYSCREG_EBI_D_15_PCTRL," bitfld.long 0x78 0.--1. " MODE ,input to the programmable section of the EBI_D_15 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x7C "SYSCREG_I2STX_DATA1_PCTRL," bitfld.long 0x7C 0.--1. " MODE ,input to the programmable section of the I2STX_DATA1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x80 "SYSCREG_I2STX_BCK1_PCTRL," bitfld.long 0x80 0.--1. " MODE ,input to the programmable section of the I2STX_BCK1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x84 "SYSCREG_I2STX_WS1_PCTRL," bitfld.long 0x84 0.--1. " MODE ,input to the programmable section of the I2STX_WS1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x88 "SYSCREG_I2SRX_DATA0_PCTRL," bitfld.long 0x88 0.--1. " MODE ,input to the programmable section of the I2SRX_DATA0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x8C "SYSCREG_I2SRX_WS0_PCTRL," bitfld.long 0x8C 0.--1. " MODE ,input to the programmable section of the I2SRX_WS0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x90 "SYSCREG_I2SRX_DATA1_PCTRL," bitfld.long 0x90 0.--1. " MODE ,input to the programmable section of the I2SRX_DATA1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x94 "SYSCREG_I2SRX_BCK1_PCTRL," bitfld.long 0x94 0.--1. " MODE ,input to the programmable section of the I2SRX_BCK1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x98 "SYSCREG_I2SRX_WS1_PCTRL," bitfld.long 0x98 0.--1. " MODE ,input to the programmable section of the I2SRX_WS1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x9C "SYSCREG_SYSCLK_O_PCTRL," bitfld.long 0x9C 0.--1. " MODE ,input to the programmable section of the SYSCLK_O pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xA0 "SYSCREG_PWM_DATA_PCTRL," bitfld.long 0xA0 0.--1. " MODE ,input to the programmable section of the PWM_DATA pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xA4 "SYSCREG_UART_RXD_PCTRL," bitfld.long 0xA4 0.--1. " MODE ,input to the programmable section of the UART_RXD pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xA8 "SYSCREG_UART_TXD_PCTRL," bitfld.long 0xA8 0.--1. " MODE ,input to the programmable section of the UART_TXD pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xAC "SYSCREG_I2C_SDA1_PCTRL," bitfld.long 0xAC 0.--1. " MODE ,input to the programmable section of the I2C_SDA1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xB0 "SYSCREG_I2C_SCL1_PCTRL," bitfld.long 0xB0 0.--1. " MODE ,input to the programmable section of the I2C_SCL1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xB4 "SYSCREG_CLK_256FS_O_PCTRL," bitfld.long 0xB4 0.--1. " MODE ,input to the programmable section of the CLK_256FS_O pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xB8 "SYSCREG_GPIO0_PCTRL," bitfld.long 0xB8 0.--1. " MODE ,input to the programmable section of the GPIO0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xBC "SYSCREG_GPIO2_PCTRL," bitfld.long 0xBC 0.--1. " MODE ,input to the programmable section of the GPIO2 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xC0 "SYSCREG_GPIO3_PCTRL," bitfld.long 0xC0 0.--1. " MODE ,input to the programmable section of the GPIO3 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xC4 "SYSCREG_GPIO4_PCTRL," bitfld.long 0xC4 0.--1. " MODE ,input to the programmable section of the GPIO4 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xC8 "SYSCREG_GPIO11_PCTRL," bitfld.long 0xC8 0.--1. " MODE ,input to the programmable section of the GPIO11 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xCC "SYSCREG_GPIO12_PCTRL," bitfld.long 0xCC 0.--1. " MODE ,input to the programmable section of the GPIO12 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xD0 "SYSCREG_GPIO13_PCTRL," bitfld.long 0xD0 0.--1. " MODE ,input to the programmable section of the GPIO13 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xD4 "SYSCREG_GPIO14_PCTRL," bitfld.long 0xD4 0.--1. " MODE ,input to the programmable section of the GPIO14 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xD8 "SYSCREG_GPIO15_PCTRL," bitfld.long 0xD8 0.--1. " MODE ,input to the programmable section of the GPIO15 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xDC "SYSCREG_GPIO16_PCTRL," bitfld.long 0xDC 0.--1. " MODE ,input to the programmable section of the GPIO16 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xE0 "SYSCREG_GPIO17_PCTRL," bitfld.long 0xE0 0.--1. " MODE ,input to the programmable section of the GPIO17 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xE4 "SYSCREG_GPIO18_PCTRL," bitfld.long 0xE4 0.--1. " MODE ,input to the programmable section of the GPIO18 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xE8 "SYSCREG_GPIO19_PCTRL," bitfld.long 0xE8 0.--1. " MODE ,input to the programmable section of the GPIO19 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xEC "SYSCREG_GPIO20_PCTRL," bitfld.long 0xEC 0.--1. " MODE ,input to the programmable section of the GPIO20 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xF0 "SYSCREG_SPI_MISO_PCTRL," bitfld.long 0xF0 0.--1. " MODE ,input to the programmable section of the SPI_MISO pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xF4 "SYSCREG_SPI_MOSI_PCTRL," bitfld.long 0xF4 0.--1. " MODE ,input to the programmable section of the SPI_MOSI pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xF8 "SYSCREG_SPI_CS_IN_PCTRL," bitfld.long 0xF8 0.--1. " MODE ,input to the programmable section of the SPI_CS_IN pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0xFC "SYSCREG_SPI_SCK_PCTRL," bitfld.long 0xFC 0.--1. " MODE ,input to the programmable section of the SPI_SCK pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x100 "SYSCREG_SPI_CS_OUT0_PCTRL," bitfld.long 0x100 0.--1. " MODE ,input to the programmable section of the SPI_CS_OUT0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x104 "SYSCREG_NAND_NCS_0_PCTRL," bitfld.long 0x104 0.--1. " MODE ,input to the programmable section of the NAND_NCS_0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x108 "SYSCREG_NAND_NCS_1_PCTRL," bitfld.long 0x108 0.--1. " MODE ,input to the programmable section of the NAND_NCS_1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x10C "SYSCREG_NAND_NCS_2_PCTRL," bitfld.long 0x10C 0.--1. " MODE ,input to the programmable section of the NAND_NCS_2 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x110 "SYSCREG_MLCD_CSB_PCTRL," bitfld.long 0x110 0.--1. " MODE ,input to the programmable section of the MLCD_CSB pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x114 "SYSCREG_MLCD_DB_1_PCTRL," bitfld.long 0x114 0.--1. " MODE ,input to the programmable section of the MLCD_DB_1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x118 "SYSCREG_MLCD_E_RD_PCTRL," bitfld.long 0x118 0.--1. " MODE ,input to the programmable section of the MLCD_E_RD pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x11C "SYSCREG_MLCD_RS_PCTRL," bitfld.long 0x11C 0.--1. " MODE ,input to the programmable section of the MLCD_RS pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x120 "SYSCREG_MLCD_RW_WR_PCTRL," bitfld.long 0x120 0.--1. " MODE ,input to the programmable section of the MLCD_RW_WR pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x124 "SYSCREG_MLCD_DB_3_PCTRL," bitfld.long 0x124 0.--1. " MODE ,input to the programmable section of the MLCD_DB_3 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x128 "SYSCREG_MLCD_DB_5_PCTRL," bitfld.long 0x128 0.--1. " MODE ,input to the programmable section of the MLCD_DB_5 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x12C "SYSCREG_MLCD_DB_6_PCTRL," bitfld.long 0x12C 0.--1. " MODE ,input to the programmable section of the MLCD_DB_6 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x130 "SYSCREG_MLCD_DB_8_PCTRL," bitfld.long 0x130 0.--1. " MODE ,input to the programmable section of the MLCD_DB_8 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x134 "SYSCREG_MLCD_DB_9_PCTRL," bitfld.long 0x134 0.--1. " MODE ,input to the programmable section of the MLCD_DB_9 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x138 "SYSCREG_MLCD_DB_10_PCTRL," bitfld.long 0x138 0.--1. " MODE ,input to the programmable section of the MLCD_DB_10 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x13C "SYSCREG_MLCD_DB_11_PCTRL," bitfld.long 0x13C 0.--1. " MODE ,input to the programmable section of the MLCD_DB_11 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x140 "SYSCREG_MLCD_DB_12_PCTRL," bitfld.long 0x140 0.--1. " MODE ,input to the programmable section of the MLCD_DB_12 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x144 "SYSCREG_MLCD_DB_13_PCTRL," bitfld.long 0x144 0.--1. " MODE ,input to the programmable section of the MLCD_DB_13 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x148 "SYSCREG_MLCD_DB_14_PCTRL," bitfld.long 0x148 0.--1. " MODE ,input to the programmable section of the MLCD_DB_14 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x14C "SYSCREG_MLCD_DB_15_PCTRL," bitfld.long 0x14C 0.--1. " MODE ,input to the programmable section of the MLCD_DB_15 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x150 "SYSCREG_MGPIO5_PCTRL," bitfld.long 0x150 0.--1. " MODE ,input to the programmable section of the MGPIO5 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x154 "SYSCREG_MGPIO5_PCTRL," bitfld.long 0x154 0.--1. " MODE ,input to the programmable section of the MGPIO5 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x158 "SYSCREG_MGPIO8_PCTRL," bitfld.long 0x158 0.--1. " MODE ,input to the programmable section of the MGPIO8 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x15C "SYSCREG_MGPIO10_PCTRL," bitfld.long 0x15C 0.--1. " MODE ,input to the programmable section of the MGPIO10 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x160 "SYSCREG_MNAND_RYBN1_PCTRL," bitfld.long 0x160 0.--1. " MODE ,input to the programmable section of the MNAND_RYBN1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x164 "SYSCREG_MNAND_RYBN2_PCTRL," bitfld.long 0x164 0.--1. " MODE ,input to the programmable section of the MNAND_RYBN2 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x168 "SYSCREG_MNAND_RYBN3_PCTRL," bitfld.long 0x168 0.--1. " MODE ,input to the programmable section of the MNAND_RYBN3 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x16C "SYSCREG_MUART_CTS_N_PCTRL," bitfld.long 0x16C 0.--1. " MODE ,input to the programmable section of the MUART_CTS_N pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x170 "SYSCREG_MI2STX_DATA0_PCTRL," bitfld.long 0x170 0.--1. " MODE ,input to the programmable section of the MI2STX_DATA0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x174 "SYSCREG_MI2STX_DATA0_PCTRL," bitfld.long 0x174 0.--1. " MODE ,input to the programmable section of the MI2STX_DATA0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x178 "SYSCREG_MI2STX_DATA0_PCTRL," bitfld.long 0x178 0.--1. " MODE ,input to the programmable section of the MI2STX_DATA0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x17C "SYSCREG_MI2STX_WS0_PCTRL," bitfld.long 0x17C 0.--1. " MODE ,input to the programmable section of the MI2STX_WS0 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x180 "SYSCREG_EBI_NRAS_BLOUT_1_PCTRL," bitfld.long 0x180 0.--1. " MODE ,input to the programmable section of the EBI_NRAS_BLOUT_1 pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x184 "SYSCREG_EBI_A_0_ALE_PCTRL," bitfld.long 0x184 0.--1. " MODE ,input to the programmable section of the EBI_A_0_ALE pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x188 "SYSCREG_EBI_NWE_PCTRL," bitfld.long 0x188 0.--1. " MODE ,input to the programmable section of the EBI_NWE pad" "Pull-up,Plain input,Repeater,Weak pull-down" line.long 0x188 "SYSCREG_ESHCTRL_SUP4,Input to control the performance of the pad at 1.8 and 2.8 V (Nandflash/EBI pads)" bitfld.long 0x188 0. " SYSCREG_ESH_CTRL_SUP4 ,performance of all pads from the supply domain SUP4 (Nandflash and EBI pads)" "Less switching noise,High speed-performance" line.long 0x18c "SYSCREG_ESHCTRL_SUP8, Input to control the performance of the pad at 1.8 and 2.8 V (LCD interface/SDRAM pads)" bitfld.long 0x18c 0. " SYSCREG_ESH_CTRL_SUP8 ,performance of all pads from supply domain SUP8 (LCD interface/SDRAM pads)" "Less switching noise,High speed-performance" tree.end width 0xb tree.end tree "PCM (Pulse Code Modulation)" base ad:0x15000000 width 10. group.long 0x00++0x3 line.long 0x00 "GLOBAL,Global register" bitfld.long 0x00 4. " DMARXENABLE ,DMA rx enabled" "Disabled,Enabled" bitfld.long 0x00 3. " DMATXENABLE ,DMA tx enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " NORMAL ,PCM Mode" "Slave single slot,Normal" bitfld.long 0x00 0. " ON_OFF ,IPINT enable" "Disabled,Enabled" if (((d.l(ad:0x15000000))&0x4)==0x4) group.long 0x04++0x3 line.long 0x00 "CNTL0,Control register 0" bitfld.long 0x00 14. " MASTER ,PCM/IOM master mode" "Slave,Master" bitfld.long 0x00 11. " LOOPBACK ,Internal loop-back mode" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " TYP_OD ,Type of PCM_FCS an PCM_DCLK output port" "Open-drain,Push-pull" bitfld.long 0x00 8.--9. " TYP_DO_IP ,Type of PCM/IOM data output ports" "Tri-state,Open-drain/tri-state,Push-pull/tri-state,Push-pull" textline " " bitfld.long 0x00 6.--7. " TYP_FRMSYNC ,Shape of frame synchronization signal" "Short FR first rising edge,Short FF first falling edge,Short LF last falling edge,Long first slot (8 bit)" bitfld.long 0x00 3.--5. " CLK_SPD ,Port frequency selection" "PCM: 512 kHz,PCM: 768 kHz,PCM: 1.536 MHz,PCM: 2.048 MHz,IOM: 512 kHz,IOM: 768 kHz,IOM: 1.536 MHz,IOM: 4.096 MHz" else group.long 0x04++0x3 line.long 0x00 "CNTL0,Control register 0" bitfld.long 0x00 14. " MASTER ,PCM/IOM master mode" "Slave,Master" bitfld.long 0x00 11. " LOOPBACK ,Internal loop-back mode" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " TYP_OD ,Type of PCM_FCS an PCM_DCLK output port" "Open-drain,Push-pull" bitfld.long 0x00 8.--9. " TYP_DO_IP ,Type of PCM/IOM data output ports" "Tri-state,Open-drain/tri-state,Push-pull/tri-state,Push-pull" textline " " bitfld.long 0x00 6.--7. " TYP_FRMSYNC ,Shape of frame synchronization signal" "Reserved,Reserved,Short LF last falling edge,?..." bitfld.long 0x00 3.--5. " CLK_SPD ,Port frequency selection" "PCM: 512 kHz,PCM: 768 kHz,PCM: 1.536 MHz,PCM: 2.048 MHz,IOM: 512 kHz,IOM: 768 kHz,IOM: 1.536 MHz,IOM: 4.096 MHz" endif group.long 0x08++0x3 line.long 0x00 "CNTL1,Control register 1" bitfld.long 0x00 11. " ENSLT_11 ,Enable PCM/IOM Slot 11" "Disabled,Enabled" bitfld.long 0x00 10. " ENSLT_10 ,Enable PCM/IOM Slot 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ENSLT_9 ,Enable PCM/IOM Slot 9" "Disabled,Enabled" bitfld.long 0x00 8. " ENSLT_8 ,Enable PCM/IOM Slot 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ENSLT_7 ,Enable PCM/IOM Slot 7" "Disabled,Enabled" bitfld.long 0x00 6. " ENSLT_6 ,Enable PCM/IOM Slot 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ENSLT_5 ,Enable PCM/IOM Slot 5" "Disabled,Enabled" bitfld.long 0x00 4. " ENSLT_4 ,Enable PCM/IOM Slot 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ENSLT_3 ,Enable PCM/IOM Slot 3" "Disabled,Enabled" bitfld.long 0x00 2. " ENSLT_2 ,Enable PCM/IOM Slot 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENSLT_1 ,Enable PCM/IOM Slot 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENSLT_0 ,Enable PCM/IOM Slot 0" "Disabled,Enabled" if (((d.l(ad:0x15000000))&0x4)==0x4) wgroup.long 0x0c++0x17 line.long 0x00 "HPOUT[0],Transmit data register 0" hexmask.long.byte 0x00 8.--15. 1. " OUTSLOT_1 ,Outslot 1" hexmask.long.byte 0x00 0.--7. 1. " OUTSLOT_0 ,Outslot 0" line.long 0x04 "HPOUT[1],Transmit data register 1" hexmask.long.byte 0x04 8.--15. 1. " OUTSLOT_4 ,Outslot 4" hexmask.long.byte 0x04 0.--7. 1. " OUTSLOT_3 ,Outslot 3" line.long 0x08 "HPOUT[2],Transmit data register 2" hexmask.long.byte 0x08 8.--15. 1. " OUTSLOT_6 ,Outslot 6" hexmask.long.byte 0x08 0.--7. 1. " OUTSLOT_5 ,Outslot 5" line.long 0x0c "HPOUT[3],Transmit data register 3" hexmask.long.byte 0x0c 8.--15. 1. " OUTSLOT_8 ,Outslot 8" hexmask.long.byte 0x0c 0.--7. 1. " OUTSLOT_7 ,Outslot 7" line.long 0x10 "HPOUT[4],Transmit data register 4" hexmask.long.byte 0x10 8.--15. 1. " OUTSLOT_10 ,Outslot 10" hexmask.long.byte 0x10 0.--7. 1. " OUTSLOT_9 ,OutOutslot 9" line.long 0x14 "HPOUT[5],Transmit data register 5" hexmask.long.byte 0x14 8.--15. 1. " OUTSLOT_12 ,Outslot 12" hexmask.long.byte 0x14 0.--7. 1. " OUTSLOT_11 ,Outslot 11" else wgroup.long 0x0c++0x3 line.long 0x00 "HPOUT[0],Transmit data register 0" hexmask.long.byte 0x00 8.--15. 1. " OUTSLOT_1 ,Outslot 1" hexmask.long.byte 0x00 0.--7. 1. " OUTSLOT_0 ,Outslot 0" endif if (((d.l(ad:0x15000000))&0x4)==0x4) rgroup.long 0x24++0x17 line.long 0x00 "HPIN[0],Receive data register 0" hexmask.long.byte 0x00 8.--15. 1. " INSLOT_1 ,Inslot 1" hexmask.long.byte 0x00 0.--7. 1. " INSLOT_0 ,Inslot 0" line.long 0x04 "HPIN[1],Receive data register 1" hexmask.long.byte 0x04 8.--15. 1. " INSLOT_3 ,Inslot 3" hexmask.long.byte 0x04 0.--7. 1. " INSLOT_2 ,Inslot 2" line.long 0x08 "HPIN[2],Receive data register 2" hexmask.long.byte 0x08 8.--15. 1. " INSLOT_5 ,Inslot 5" hexmask.long.byte 0x08 0.--7. 1. " INSLOT_4 ,Inslot 4" line.long 0x0c "HPIN[3],Receive data register 3" hexmask.long.byte 0x0c 8.--15. 1. " INSLOT_7 ,Inslot 7" hexmask.long.byte 0x0c 0.--7. 1. " INSLOT_6 ,Inslot 6" line.long 0x10 "HPIN[4],Receive data register 4" hexmask.long.byte 0x10 8.--15. 1. " INSLOT_10 ,Inslot 10" hexmask.long.byte 0x10 0.--7. 1. " INSLOT_9 ,Inslot 9" line.long 0x14 "HPIN[5],Receive data register 5" hexmask.long.byte 0x14 8.--15. 1. " INSLOT_12 ,Inslot 12" hexmask.long.byte 0x14 0.--7. 1. " INSLOT_11 ,Inslot 11" else rgroup.long 0x30++0x3 line.long 0x00 "HPIN[3],Receive data register 3" hexmask.long.byte 0x00 8.--15. 1. " INSLOT_7 ,Inslot 7" hexmask.long.byte 0x00 0.--7. 1. " INSLOT_6 ,Inslot 6" endif group.long 0x03c++0x3 line.long 0x00 "CNTL2,Control register 2" bitfld.long 0x00 11. " SLOTDIRINV_11 ,PCM A/B port configuration slot 11" "A-output/B-input,A-input/B-output" bitfld.long 0x00 10. " SLOTDIRINV_10 ,PCM A/B port configuration slot 10" "A-output/B-input,A-input/B-output" textline " " bitfld.long 0x00 9. " SLOTDIRINV_9 ,PCM A/B port configuration slot 9" "A-output/B-input,A-input/B-output" bitfld.long 0x00 8. " SLOTDIRINV_8 ,PCM A/B port configuration slot 8" "A-output/B-input,A-input/B-output" textline " " bitfld.long 0x00 7. " SLOTDIRINV_7 ,PCM A/B port configuration slot 7" "A-output/B-input,A-input/B-output" bitfld.long 0x00 6. " SLOTDIRINV_6 ,PCM A/B port configuration slot 6" "A-output/B-input,A-input/B-output" textline " " bitfld.long 0x00 5. " SLOTDIRINV_5 ,PCM A/B port configuration slot 5" "A-output/B-input,A-input/B-output" bitfld.long 0x00 4. " SLOTDIRINV_4 ,PCM A/B port configuration slot 4" "A-output/B-input,A-input/B-output" textline " " bitfld.long 0x00 3. " SLOTDIRINV_3 ,PCM A/B port configuration slot 3" "A-output/B-input,A-input/B-output" bitfld.long 0x00 2. " SLOTDIRINV_2 ,PCM A/B port configuration slot 2" "A-output/B-input,A-input/B-output" textline " " bitfld.long 0x00 1. " SLOTDIRINV_1 ,PCM A/B port configuration slot 1" "A-output/B-input,A-input/B-output" bitfld.long 0x00 0. " SLOTDIRINV_0 ,PCM A/B port configuration slot 0" "A-output/B-input,A-input/B-output" width 0xb tree.end tree.open "I2S (Inter-IC Sound)" base ad:0x16000000 width 22. tree "I2S configuration" group.long 0x00++0x7 line.long 0x00 "I2S_FORMAT_SETTINGS,I2S formats" bitfld.long 0x00 9.--11. " I2SRX1_FORMAT ,I2SRX1 I2S output format" "Reserved,Reserved,Reserved,I2S,16 bits (LSB justified),18 bits (LSB justified),20 bits LSB (justified),24 bits(LSB justified)" textline " " bitfld.long 0x00 6.--8. " I2SRX0_FORMAT ,I2SRX0 I2S output format" "Reserved,Reserved,Reserved,I2S,LSB justified 16 bits,LSB justified 18 bits,LSB justified 20 bits,LSB justified 24 bits" textline " " bitfld.long 0x00 3.--5. " I2STX1_FORMAT ,I2STX1 I2S input format" "Reserved,Reserved,Reserved,I2S,LSB justified 16 bits,LSB justified 18 bits,LSB justified 20 bits,LSB justified 24 bits" textline " " bitfld.long 0x00 0.--2. " I2STX0_FORMAT ,I2STX0 I2S input format" "Reserved,Reserved,Reserved,I2S,LSB justified 16 bits,LSB justified 18 bits,LSB justified 20 bits,LSB justified 24 bits" line.long 0x04 "I2S_CFG_MUX_SETTINGS,Misc controls" bitfld.long 0x04 2. " I2SRX1_OE_N ,I2SRX1 mode" "Slave,Master" textline " " bitfld.long 0x04 1. " I2SRX0_OE_N ,I2SRX0 mode" "Slave,Master" tree.end width 15. tree "I2STX0" group.long 0x80++0x17 line.long 0x00 "LEFT_16BIT,16 bits left channel data" line.long 0x04 "RIGHT_16BIT,16 bits right channel data" line.long 0x08 "LEFT_24BIT,24 bits left channel data" line.long 0x0c "RIGHT_24BIT,24 bits right channel data" line.long 0x10 "INT_STATUS,FIFO status register" bitfld.long 0x10 9. " R_EMPTY ,FIFO right empty" "No interrupt,Interrupt" bitfld.long 0x10 8. " R_HALF_EMPTY ,FIFO right half_empty" "No interrupt,Interrupt" textline " " bitfld.long 0x10 7. " R_FULL ,FIFO right full" "No interrupt,Interrupt" bitfld.long 0x10 6. " L_EMPTY ,FIFO left empty" "No interrupt,Interrupt" textline " " bitfld.long 0x10 5. " L_HALF_EMPTY ,FIFO left half_empty" "No interrupt,Interrupt" bitfld.long 0x10 4. " L_FULL ,FIFO left full" "No interrupt,Interrupt" textline " " bitfld.long 0x10 3. " L_OVERRUN ,FIFO left overrun" "No interrupt,Interrupt" bitfld.long 0x10 2. " R_OVERRUN ,FIFO right overrun" "No interrupt,Interrupt" textline " " bitfld.long 0x10 1. " L_UNDERRUN ,FIFO left underrun" "No interrupt,Interrupt" bitfld.long 0x10 0. " R_UNDERRUN ,FIFO right underrun" "No interrupt,Interrupt" line.long 0x14 "INT_MASK,Interrupt Mask register" bitfld.long 0x14 9. " R_EMPTY ,FIFO right empty" "Masked,Not Masked" bitfld.long 0x14 8. " R_HALF_EMPTY ,FIFO right half_empty" "Masked,Not Masked" textline " " bitfld.long 0x14 7. " R_FULL ,FIFO right full" "Masked,Not Masked" bitfld.long 0x14 6. " L_EMPTY ,FIFO left empty" "Masked,Not Masked" textline " " bitfld.long 0x14 5. " L_HALF_EMPTY ,FIFO left half_empty" "Masked,Not Masked" bitfld.long 0x14 4. " L_FULL ,FIFO left full" "Masked,Not Masked" textline " " bitfld.long 0x14 3. " L_OVERRUN ,FIFO left overrun" "Masked,Not Masked" bitfld.long 0x14 2. " R_OVERRUN ,FIFO right overrun" "Masked,Not Masked" textline " " bitfld.long 0x14 1. " L_UNDERRUN ,FIFO left underrun" "Masked,Not Masked" bitfld.long 0x14 0. " R_UNDERRUN ,FIFO right underrun" "Masked,Not Masked" group.long (0x80+0x20)++0x5f line.long 0x00 "LEFT_32BIT_0,2x16 bits left channel data" line.long 0x04 "LEFT_32BIT_1,2x16 bits left channel data" line.long 0x08 "LEFT_32BIT_2,2x16 bits left channel data" line.long 0x0c "LEFT_32BIT_3,2x16 bits left channel data" line.long 0x10 "LEFT_32BIT_4,2x16 bits left channel data" line.long 0x14 "LEFT_32BIT_5,2x16 bits left channel data" line.long 0x18 "LEFT_32BIT_6,2x16 bits left channel data" line.long 0x1c "LEFT_32BIT_7,2x16 bits left channel data" line.long 0x20 "RIGHT_32BIT_0,2x16 bits right channel data" line.long 0x24 "RIGHT_32BIT_1,2x16 bits right channel data" line.long 0x28 "RIGHT_32BIT_2,2x16 bits right channel data" line.long 0x2c "RIGHT_32BIT_3,2x16 bits right channel data" line.long 0x30 "RIGHT_32BIT_4,2x16 bits right channel data" line.long 0x34 "RIGHT_32BIT_5,2x16 bits right channel data" line.long 0x38 "RIGHT_32BIT_6,2x16 bits right channel data" line.long 0x3c "RIGHT_32BIT_7,2x16 bits right channel data" line.long 0x40 "INTERLEAVED_0,Interleaved data" line.long 0x44 "INTERLEAVED_1,Interleaved data" line.long 0x48 "INTERLEAVED_2,Interleaved data" line.long 0x4c "INTERLEAVED_3,Interleaved data" line.long 0x50 "INTERLEAVED_4,Interleaved data" line.long 0x54 "INTERLEAVED_5,Interleaved data" line.long 0x58 "INTERLEAVED_6,Interleaved data" line.long 0x5c "INTERLEAVED_7,Interleaved data" tree.end tree "I2STX1" group.long 0x100++0x17 line.long 0x00 "LEFT_16BIT,16 bits left channel data" line.long 0x04 "RIGHT_16BIT,16 bits right channel data" line.long 0x08 "LEFT_24BIT,24 bits left channel data" line.long 0x0c "RIGHT_24BIT,24 bits right channel data" line.long 0x10 "INT_STATUS,FIFO status register" bitfld.long 0x10 9. " R_EMPTY ,FIFO right empty" "No interrupt,Interrupt" bitfld.long 0x10 8. " R_HALF_EMPTY ,FIFO right half_empty" "No interrupt,Interrupt" textline " " bitfld.long 0x10 7. " R_FULL ,FIFO right full" "No interrupt,Interrupt" bitfld.long 0x10 6. " L_EMPTY ,FIFO left empty" "No interrupt,Interrupt" textline " " bitfld.long 0x10 5. " L_HALF_EMPTY ,FIFO left half_empty" "No interrupt,Interrupt" bitfld.long 0x10 4. " L_FULL ,FIFO left full" "No interrupt,Interrupt" textline " " bitfld.long 0x10 3. " L_OVERRUN ,FIFO left overrun" "No interrupt,Interrupt" bitfld.long 0x10 2. " R_OVERRUN ,FIFO right overrun" "No interrupt,Interrupt" textline " " bitfld.long 0x10 1. " L_UNDERRUN ,FIFO left underrun" "No interrupt,Interrupt" bitfld.long 0x10 0. " R_UNDERRUN ,FIFO right underrun" "No interrupt,Interrupt" line.long 0x14 "INT_MASK,Interrupt Mask register" bitfld.long 0x14 9. " R_EMPTY ,FIFO right empty" "Masked,Not Masked" bitfld.long 0x14 8. " R_HALF_EMPTY ,FIFO right half_empty" "Masked,Not Masked" textline " " bitfld.long 0x14 7. " R_FULL ,FIFO right full" "Masked,Not Masked" bitfld.long 0x14 6. " L_EMPTY ,FIFO left empty" "Masked,Not Masked" textline " " bitfld.long 0x14 5. " L_HALF_EMPTY ,FIFO left half_empty" "Masked,Not Masked" bitfld.long 0x14 4. " L_FULL ,FIFO left full" "Masked,Not Masked" textline " " bitfld.long 0x14 3. " L_OVERRUN ,FIFO left overrun" "Masked,Not Masked" bitfld.long 0x14 2. " R_OVERRUN ,FIFO right overrun" "Masked,Not Masked" textline " " bitfld.long 0x14 1. " L_UNDERRUN ,FIFO left underrun" "Masked,Not Masked" bitfld.long 0x14 0. " R_UNDERRUN ,FIFO right underrun" "Masked,Not Masked" group.long (0x100+0x20)++0x5f line.long 0x00 "LEFT_32BIT_0,2x16 bits left channel data" line.long 0x04 "LEFT_32BIT_1,2x16 bits left channel data" line.long 0x08 "LEFT_32BIT_2,2x16 bits left channel data" line.long 0x0c "LEFT_32BIT_3,2x16 bits left channel data" line.long 0x10 "LEFT_32BIT_4,2x16 bits left channel data" line.long 0x14 "LEFT_32BIT_5,2x16 bits left channel data" line.long 0x18 "LEFT_32BIT_6,2x16 bits left channel data" line.long 0x1c "LEFT_32BIT_7,2x16 bits left channel data" line.long 0x20 "RIGHT_32BIT_0,2x16 bits right channel data" line.long 0x24 "RIGHT_32BIT_1,2x16 bits right channel data" line.long 0x28 "RIGHT_32BIT_2,2x16 bits right channel data" line.long 0x2c "RIGHT_32BIT_3,2x16 bits right channel data" line.long 0x30 "RIGHT_32BIT_4,2x16 bits right channel data" line.long 0x34 "RIGHT_32BIT_5,2x16 bits right channel data" line.long 0x38 "RIGHT_32BIT_6,2x16 bits right channel data" line.long 0x3c "RIGHT_32BIT_7,2x16 bits right channel data" line.long 0x40 "INTERLEAVED_0,Interleaved data" line.long 0x44 "INTERLEAVED_1,Interleaved data" line.long 0x48 "INTERLEAVED_2,Interleaved data" line.long 0x4c "INTERLEAVED_3,Interleaved data" line.long 0x50 "INTERLEAVED_4,Interleaved data" line.long 0x54 "INTERLEAVED_5,Interleaved data" line.long 0x58 "INTERLEAVED_6,Interleaved data" line.long 0x5c "INTERLEAVED_7,Interleaved data" tree.end tree "I2SRX0" hgroup.long 0x180++0x3 hide.long 0x00 "LEFT_16BIT,16 bits left channel data" in hgroup.long (0x180+0x4)++0x3 hide.long 0x04 "RIGHT_16BIT,16 bits right channel data" in hgroup.long (0x180+0x8)++0x3 hide.long 0x08 "LEFT_24BIT,24 bits left channel data" in hgroup.long (0x180+0xc)++0x3 hide.long 0x0c "RIGHT_24BIT,24 bits right channel data" in group.long (0x180+0x10)++0x7 line.long 0x00 "INT_STATUS,FIFO status register" bitfld.long 0x00 9. " R_NOT_EMPTY ,FIFO right not empty" "No interrupt,Interrupt" bitfld.long 0x00 8. " R_HALF_FULL ,FIFO right half_full" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " R_FULL ,FIFO right full" "No interrupt,Interrupt" bitfld.long 0x00 6. " L_NOT_EMPTY ,FIFO left not empty" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " L_HALF_FULL ,FIFO left half_full" "No interrupt,Interrupt" bitfld.long 0x00 4. " L_FULL ,FIFO left full" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " L_OVERRUN ,FIFO left overrun" "No interrupt,Interrupt" bitfld.long 0x00 2. " R_OVERRUN ,FIFO right overrun" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " L_UNDERRUN ,FIFO left underrun" "No interrupt,Interrupt" bitfld.long 0x00 0. " R_UNDERRUN ,FIFO right underrun" "No interrupt,Interrupt" line.long 0x04 "INT_MASK,Interrupt Mask register" bitfld.long 0x04 9. " R_NOT_EMPTY ,FIFO right not empty" "Masked,Not masked" bitfld.long 0x04 8. " R_HALF_FULL ,FIFO right half_full" "Masked,Not masked" textline " " bitfld.long 0x04 7. " R_FULL ,FIFO right full" "Masked,Not masked" bitfld.long 0x04 6. " L_NOT_EMPTY ,FIFO left not empty" "Masked,Not masked" textline " " bitfld.long 0x04 5. " L_HALF_FULL ,FIFO left half_full" "Masked,Not masked" bitfld.long 0x04 4. " L_FULL ,FIFO left full" "Masked,Not masked" textline " " bitfld.long 0x04 3. " L_OVERRUN ,FIFO left overrun" "Masked,Not masked" bitfld.long 0x04 2. " R_OVERRUN ,FIFO right overrun" "Masked,Not masked" textline " " bitfld.long 0x04 1. " L_UNDERRUN ,FIFO left underrun" "Masked,Not masked" bitfld.long 0x04 0. " R_UNDERRUN ,FIFO right underrun" "Masked,Not masked" hgroup.long (0x180+0x20)++0x3 hide.long 0x00 "LEFT_32BIT_0,2x16 bits left channel data" in hgroup.long (0x180+0x24)++0x3 hide.long 0x00 "LEFT_32BIT_1,2x16 bits left channel data" in hgroup.long (0x180+0x28)++0x3 hide.long 0x00 "LEFT_32BIT_2,2x16 bits left channel data" in hgroup.long (0x180+0x2c)++0x3 hide.long 0x00 "LEFT_32BIT_3,2x16 bits left channel data" in hgroup.long (0x180+0x30)++0x3 hide.long 0x00 "LEFT_32BIT_4,2x16 bits left channel data" in hgroup.long (0x180+0x34)++0x3 hide.long 0x00 "LEFT_32BIT_5,2x16 bits left channel data" in hgroup.long (0x180+0x38)++0x3 hide.long 0x00 "LEFT_32BIT_6,2x16 bits left channel data" in hgroup.long (0x180+0x3c)++0x3 hide.long 0x00 "LEFT_32BIT_7,2x16 bits left channel data" in hgroup.long (0x180+0x40)++0x3 hide.long 0x00 "RIGHT_32BIT_0,2x16 bits right channel data" in hgroup.long (0x180+0x44)++0x3 hide.long 0x00 "RIGHT_32BIT_1,2x16 bits right channel data" in hgroup.long (0x180+0x48)++0x3 hide.long 0x00 "RIGHT_32BIT_2,2x16 bits right channel data" in hgroup.long (0x180+0x4c)++0x3 hide.long 0x00 "RIGHT_32BIT_3,2x16 bits right channel data" in hgroup.long (0x180+0x50)++0x3 hide.long 0x00 "RIGHT_32BIT_4,2x16 bits right channel data" in hgroup.long (0x180+0x54)++0x3 hide.long 0x00 "RIGHT_32BIT_5,2x16 bits right channel data" in hgroup.long (0x180+0x58)++0x3 hide.long 0x00 "RIGHT_32BIT_6,2x16 bits right channel data" in hgroup.long (0x180+0x5c)++0x3 hide.long 0x00 "RIGHT_32BIT_7,2x16 bits right channel data" in hgroup.long (0x180+0x60)++0x3 hide.long 0x00 "INTERLEAVED_0,Interleaved data" in hgroup.long (0x180+0x64)++0x3 hide.long 0x00 "INTERLEAVED_1,Interleaved data" in hgroup.long (0x180+0x68)++0x3 hide.long 0x00 "INTERLEAVED_2,Interleaved data" in hgroup.long (0x180+0x6c)++0x3 hide.long 0x00 "INTERLEAVED_3,Interleaved data" in hgroup.long (0x180+0x70)++0x3 hide.long 0x00 "INTERLEAVED_4,Interleaved data" in hgroup.long (0x180+0x74)++0x3 hide.long 0x00 "INTERLEAVED_5,Interleaved data" in hgroup.long (0x180+0x78)++0x3 hide.long 0x00 "INTERLEAVED_6,Interleaved data" in hgroup.long (0x180+0x7c)++0x3 hide.long 0x00 "INTERLEAVED_7,Interleaved data" in tree.end tree "I2SRX1" hgroup.long 0x200++0x3 hide.long 0x00 "LEFT_16BIT,16 bits left channel data" in hgroup.long (0x200+0x4)++0x3 hide.long 0x04 "RIGHT_16BIT,16 bits right channel data" in hgroup.long (0x200+0x8)++0x3 hide.long 0x08 "LEFT_24BIT,24 bits left channel data" in hgroup.long (0x200+0xc)++0x3 hide.long 0x0c "RIGHT_24BIT,24 bits right channel data" in group.long (0x200+0x10)++0x7 line.long 0x00 "INT_STATUS,FIFO status register" bitfld.long 0x00 9. " R_NOT_EMPTY ,FIFO right not empty" "No interrupt,Interrupt" bitfld.long 0x00 8. " R_HALF_FULL ,FIFO right half_full" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " R_FULL ,FIFO right full" "No interrupt,Interrupt" bitfld.long 0x00 6. " L_NOT_EMPTY ,FIFO left not empty" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " L_HALF_FULL ,FIFO left half_full" "No interrupt,Interrupt" bitfld.long 0x00 4. " L_FULL ,FIFO left full" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " L_OVERRUN ,FIFO left overrun" "No interrupt,Interrupt" bitfld.long 0x00 2. " R_OVERRUN ,FIFO right overrun" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " L_UNDERRUN ,FIFO left underrun" "No interrupt,Interrupt" bitfld.long 0x00 0. " R_UNDERRUN ,FIFO right underrun" "No interrupt,Interrupt" line.long 0x04 "INT_MASK,Interrupt Mask register" bitfld.long 0x04 9. " R_NOT_EMPTY ,FIFO right not empty" "Masked,Not masked" bitfld.long 0x04 8. " R_HALF_FULL ,FIFO right half_full" "Masked,Not masked" textline " " bitfld.long 0x04 7. " R_FULL ,FIFO right full" "Masked,Not masked" bitfld.long 0x04 6. " L_NOT_EMPTY ,FIFO left not empty" "Masked,Not masked" textline " " bitfld.long 0x04 5. " L_HALF_FULL ,FIFO left half_full" "Masked,Not masked" bitfld.long 0x04 4. " L_FULL ,FIFO left full" "Masked,Not masked" textline " " bitfld.long 0x04 3. " L_OVERRUN ,FIFO left overrun" "Masked,Not masked" bitfld.long 0x04 2. " R_OVERRUN ,FIFO right overrun" "Masked,Not masked" textline " " bitfld.long 0x04 1. " L_UNDERRUN ,FIFO left underrun" "Masked,Not masked" bitfld.long 0x04 0. " R_UNDERRUN ,FIFO right underrun" "Masked,Not masked" hgroup.long (0x200+0x20)++0x3 hide.long 0x00 "LEFT_32BIT_0,2x16 bits left channel data" in hgroup.long (0x200+0x24)++0x3 hide.long 0x00 "LEFT_32BIT_1,2x16 bits left channel data" in hgroup.long (0x200+0x28)++0x3 hide.long 0x00 "LEFT_32BIT_2,2x16 bits left channel data" in hgroup.long (0x200+0x2c)++0x3 hide.long 0x00 "LEFT_32BIT_3,2x16 bits left channel data" in hgroup.long (0x200+0x30)++0x3 hide.long 0x00 "LEFT_32BIT_4,2x16 bits left channel data" in hgroup.long (0x200+0x34)++0x3 hide.long 0x00 "LEFT_32BIT_5,2x16 bits left channel data" in hgroup.long (0x200+0x38)++0x3 hide.long 0x00 "LEFT_32BIT_6,2x16 bits left channel data" in hgroup.long (0x200+0x3c)++0x3 hide.long 0x00 "LEFT_32BIT_7,2x16 bits left channel data" in hgroup.long (0x200+0x40)++0x3 hide.long 0x00 "RIGHT_32BIT_0,2x16 bits right channel data" in hgroup.long (0x200+0x44)++0x3 hide.long 0x00 "RIGHT_32BIT_1,2x16 bits right channel data" in hgroup.long (0x200+0x48)++0x3 hide.long 0x00 "RIGHT_32BIT_2,2x16 bits right channel data" in hgroup.long (0x200+0x4c)++0x3 hide.long 0x00 "RIGHT_32BIT_3,2x16 bits right channel data" in hgroup.long (0x200+0x50)++0x3 hide.long 0x00 "RIGHT_32BIT_4,2x16 bits right channel data" in hgroup.long (0x200+0x54)++0x3 hide.long 0x00 "RIGHT_32BIT_5,2x16 bits right channel data" in hgroup.long (0x200+0x58)++0x3 hide.long 0x00 "RIGHT_32BIT_6,2x16 bits right channel data" in hgroup.long (0x200+0x5c)++0x3 hide.long 0x00 "RIGHT_32BIT_7,2x16 bits right channel data" in hgroup.long (0x200+0x60)++0x3 hide.long 0x00 "INTERLEAVED_0,Interleaved data" in hgroup.long (0x200+0x64)++0x3 hide.long 0x00 "INTERLEAVED_1,Interleaved data" in hgroup.long (0x200+0x68)++0x3 hide.long 0x00 "INTERLEAVED_2,Interleaved data" in hgroup.long (0x200+0x6c)++0x3 hide.long 0x00 "INTERLEAVED_3,Interleaved data" in hgroup.long (0x200+0x70)++0x3 hide.long 0x00 "INTERLEAVED_4,Interleaved data" in hgroup.long (0x200+0x74)++0x3 hide.long 0x00 "INTERLEAVED_5,Interleaved data" in hgroup.long (0x200+0x78)++0x3 hide.long 0x00 "INTERLEAVED_6,Interleaved data" in hgroup.long (0x200+0x7c)++0x3 hide.long 0x00 "INTERLEAVED_7,Interleaved data" in tree.end width 0xb tree.end textline ""